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SH7708 Series
SH7708, SH7708S, SH7708R
Hardware Manual
ADE-602-105E Rev.6.0 5/5/99 Hitachi, Ltd.
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi's or any third party's patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party's rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi's sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi's sales office for any questions regarding this document or Hitachi semiconductor products.
Preface
The SH7708, SH7708S, and SH7708R(SH7708 Series) use a RISC (reduced instruction set computer) type CPU to achieve high-performance computational processing. Also incorporating the peripheral functions required for system configuration plus power-down features essential for microcontroller application systems, the SH7708 Series is a new-generation RISC microcontroller (SuperH RISC engine). The SH7708 Series have a RISC type instruction set, with basic instructions executed in one state, offering a drastic improvement in instruction execution speed. It also has an on-chip 32-bit multiplier (producing a 64-bit result) capable of high-speed multiply-and-accumulate operations. The SH7708 Series's instructions are upward-compatible with those of the SH-1 and SH-2, facilitating migration from these series to the SH7708 Series. SH7708R is completely pin compatible with the SH7708S. On-chip supporting modules that enable a user system to be configured with a minimum of components include oscillation circuits, an interrupt controller (INTC), timers, a realtime clock (RTC), and a serial communication interface (SCI). A user break controller (UBC) is provided as an on-chip module supporting program development, allowing easy configuration of a simple debugger. On-chip cache memory improves CPU processing performance, and a built-in memory management unit (MMU) performs address translation between a 4-gigabyte virtual space and physical space. An on-chip bus state controller (BSC) provides more efficient external memory access, and enables direct connection to synchronous DRAM, DRAM, and pseudo-SRAM without the need for glue logic. This hardware manual describes the hardware of the SH7708 Series. Details of instructions can be found in the programming manual. Related Manuals SH7708Series instructions SH-3/SH-3E/SH3-DSP Programming Manual Please consult your Hitachi sales representative for details of development environment system.
Contents
Section 1 Overview and Pin Functions............................................... 1
1.1 SH7708 Series Features ........................................................................................1 1.2 Block Diagram ....................................................................................................6 1.3 Pin Description ...................................................................................................7 1.3.1 Pin Arrangement ......................................................................................7 1.3.2 SH7708 Series Pin Functions.....................................................................8
Section 2 CPU .......................................................................... 13
2.1 Register Configuration..........................................................................................13 2.1.1 Privileged Mode and Banks.........................................................................13 2.1.2 General Registers .....................................................................................16 2.1.3 System Registers .....................................................................................17 2.1.4 Control Registers .....................................................................................17 2.2 Data Formats ......................................................................................................19 2.2.1 Data Format in Registers ...........................................................................19 2.2.2 Data Format in Memory............................................................................19 2.3 Instruction Features..............................................................................................20 2.3.1 Execution Environment.............................................................................20 2.3.2 Addressing Modes.....................................................................................22 2.3.3 Instruction Formats ..................................................................................26 2.4 Instruction Set.....................................................................................................29 2.4.1 Instruction Set Classified by Function..........................................................29 2.4.2 Instruction Code Map................................................................................45 2.5 Processor States and Processor Modes......................................................................48 2.5.1 Processor States.......................................................................................48 2.5.2 Processor Modes ......................................................................................49
Section 3 Memory Management Unit (MMU)....................................... 51
3.1 Overview............................................................................................................51 3.1.1 Features..................................................................................................51 3.1.2 Role of MMU .........................................................................................51 3.1.3 SH7708 Series MMU ...............................................................................54 3.1.4 Register Configuration ..............................................................................57 3.2 Register Description .............................................................................................58 3.3 TLB Functions ....................................................................................................60 3.3.1 Configuration of the TLB ..........................................................................60 3.3.2 TLB Indexing ..........................................................................................62 3.3.3 TLB Address Comparison ..........................................................................63 3.3.4 Page Management Information....................................................................65
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3.4 MMU Functions .................................................................................................66 3.4.1 MMU Hardware Management.....................................................................66 3.4.2 MMU Software Management .....................................................................66 3.4.3 MMU Instruction (LDLTB) .......................................................................67 3.4.4 Avoiding Synonym Problems ....................................................................68 3.5 MMU Exceptions................................................................................................70 3.5.1 TLB Miss Exception ................................................................................70 3.5.2 TLB Protection Violation Exception............................................................71 3.5.3 TLB Invalid Exception..............................................................................72 3.5.4 Initial Page Write Exception ......................................................................73 3.5.5 Processing Flow in Event of MMU Exception (Same Processing Flow for Address Error) .........................................................................................................75 3.6 Memory-Mapped TLB ..........................................................................................77 3.6.1 Address Array..........................................................................................77 3.6.2 Data Array..............................................................................................78 3.6.3 Usage Examples ......................................................................................80 3.7 Usage Note.........................................................................................................80
Section 4 Exception Handling.........................................................81
4.1 Overview ...........................................................................................................81 4.1.1 Features .................................................................................................81 4.1.2 Register Configuration..............................................................................81 4.2 Exception Handling Function.................................................................................81 4.2.1 Exception Handling Flow ..........................................................................81 4.2.2 Exception Handling Vector Addresses...........................................................82 4.2.3 Acceptance of Exceptions ..........................................................................84 4.2.4 Exception Codes ......................................................................................86 4.2.5 Exception Request Masks ..........................................................................87 4.2.6 Returning from Exception Handling ............................................................88 4.3 Register Description.............................................................................................88 4.4 Exception Handler Operation..................................................................................89 4.4.1 Reset .....................................................................................................89 4.4.2 Interrupts................................................................................................89 4.4.3 General Exceptions...................................................................................89 4.5 Individual Exception Operations .............................................................................90 4.5.1 Resets....................................................................................................90 4.5.2 General Exceptions...................................................................................91 4.5.3 Interrupts................................................................................................94 4.6 Cautions............................................................................................................95
Section 5 Cache .........................................................................97
5.1 Overview ...........................................................................................................97 5.1.1 Features .................................................................................................97
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5.1.2 Cache Structure........................................................................................97 5.1.3 Register Configuration ..............................................................................99 5.2 Register Description .............................................................................................99 5.2.1 Cache Control Register (CCR) ...................................................................99 5.3 Cache Operation ..................................................................................................100 5.3.1 Searching the Cache..................................................................................100 5.3.2 Read Access ............................................................................................102 5.3.3 Write Access ...........................................................................................102 5.3.4 Write-Back Buffer.....................................................................................102 5.3.5 Coherency of Cache and External Memory ....................................................103 5.3.6 RAM Mode.............................................................................................103 5.4 Memory-Mapped Cache.........................................................................................103 5.4.1 Address Array ..........................................................................................103 5.4.2 Data Array ..............................................................................................104 5.5 Usage Examples ..................................................................................................106 5.5.1 Invalidating Specific Entries .......................................................................106 5.5.2 Reading the Data of a Specific Entry ............................................................106
Section 6 Interrupt Controller (INTC)................................................ 107
6.1 Overview............................................................................................................107 6.1.1 Features..................................................................................................107 6.1.2 Block Diagram.........................................................................................108 6.1.3 Pin Configuration ....................................................................................109 6.1.4 Register Configuration ..............................................................................109 6.2 Interrupt Sources..................................................................................................109 6.2.1 NMI Interrupts.........................................................................................110 6.2.2 IRL Interrupts..........................................................................................110 6.2.3 On-Chip Supporting Module Interrupts ........................................................112 6.2.4 Interrupt Exception Handling and Priority .....................................................112 6.3 INTC Registers ...................................................................................................115 6.3.1 Interrupt Priority Registers A and B (IPRA-IPRB) .........................................115 6.3.2 Interrupt Control Register (ICR) .................................................................116 6.4 INTC Operation...................................................................................................117 6.4.1 Interrupt Sequence ....................................................................................117 6.4.2 Multiple Interrupts ...................................................................................119 6.5 Interrupt Response Time .......................................................................................120
Section 7 User Break Controller (UBC)............................................. 123
7.1 Overview............................................................................................................123 7.1.1 Features..................................................................................................123 7.1.2 Block Diagram.........................................................................................123 7.1.3 Register Configuration ..............................................................................125 7.1.4 Break Conditions and Register Settings ........................................................125
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7.2 UBC Register Functions .......................................................................................126 7.2.1 Break Address Register A (BARA)...............................................................126 7.2.2 Break Address Register B (BARB) ...............................................................126 7.2.3 Break ASID Register A (BASRA)...............................................................127 7.2.4 Break ASID Register B (BASRB)................................................................127 7.2.5 Break Address Mask Register A (BAMRA) ...................................................127 7.2.6 Break Address Mask Register B (BAMRB)....................................................128 7.2.7 Break Bus Cycle Register A (BBRA) ...........................................................128 7.2.8 Break Bus Cycle Register B (BBRB)............................................................129 7.2.9 Break Data Register B (BDRB) ...................................................................130 7.2.10 Break Data Mask Register B (BDMRB) ......................................................131 7.2.11 Break Control Register (BRCR) ................................................................132 7.3 UBC Operation ...................................................................................................134 7.3.1 User Break Operation Flow........................................................................134 7.3.2 Instruction Fetch Cycle Break.....................................................................135 7.3.3 Data Access Cycle Break ...........................................................................136 7.3.4 Saved Program Counter (PC) Value.............................................................137 7.3.5 Examples of Use......................................................................................138 7.3.6 Cautions ................................................................................................140
Section 8 Power-Down Modes........................................................141
8.1 Overview ...........................................................................................................141 8.1.1 Power-Down Modes .................................................................................141 8.1.2 Register Configuration..............................................................................142 8.1.3 Pin Configuration ....................................................................................143 8.2 Register Description.............................................................................................143 8.2.1 Standby Control Register (STBCR).............................................................143 8.3 Sleep Mode ........................................................................................................145 8.3.1 Transition to Sleep Mode ..........................................................................145 8.3.2 Canceling Sleep Mode ..............................................................................145 8.4 Standby Mode.....................................................................................................145 8.4.1 Transition to Standby Mode .......................................................................145 8.4.2 Canceling Standby Mode...........................................................................146 8.4.3 Clock Pause Function...............................................................................147 8.5 Module Standby Function .....................................................................................147 8.5.1 Transition to Module Standby Function .......................................................147 8.5.2 Clearing the Module Standby Function ........................................................148 8.6 Timing of STATUS Pin Changes...........................................................................148 8.6.1 Timing for Resets ....................................................................................148 8.6.2 Timing for Canceling Standbys ..................................................................150 8.6.3 Timing for Canceling Sleep Mode...............................................................151 8.7 Hardware Standby Mode........................................................................................153 8.7.1 Transition to Hardware Standby Mode..........................................................153
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8.7.2 Canceling Hardware Standby Mode ..............................................................154 8.7.3 Hardware Standby Mode Timing..................................................................154
Section 9 On-Chip Oscillation Circuits............................................... 157
9.1 Overview............................................................................................................157 9.1.1 Features..................................................................................................157 9.2 Overview of the CPG ...........................................................................................158 9.2.1 CPG Block Diagram .................................................................................158 9.2.2 CPG Pin Configuration.............................................................................161 9.2.3 CPG Register Configuration ......................................................................161 9.3 Clock Operating Modes.........................................................................................162 9.4 Register Descriptions............................................................................................170 9.4.1 Frequency Control Register (FRQCR)..........................................................170 9.5 Changing the Frequency........................................................................................174 9.5.1 Changing the Multiplication Rate ...............................................................174 9.5.2 Changing the Division Ratio......................................................................174 9.6 PLL Standby Function..........................................................................................175 9.6.1 Overview of the PLL Standby Function........................................................175 9.6.2 Usage.....................................................................................................175 9.7 Controlling Clock Output .....................................................................................176 9.7.1 Clock Modes 0-2.....................................................................................176 9.7.2 Clock Modes 3 and 4 ................................................................................176 9.8 Overview of the Watchbog Timer (WDT) .................................................................177 9.8.1 Block Diagram of the WDT........................................................................177 9.8.2 Register Configurations.............................................................................177 9.9 WDT Registers....................................................................................................178 9.9.1 Watchdog Timer Counter (WTCNT) ............................................................178 9.9.2 Watchdog Timer Control/Status Register (WTCSR) .......................................178 9.9.3 Notes on Register Access...........................................................................180 9.10 Using the WDT .................................................................................................181 9.10.1 Canceling Standbys.................................................................................181 9.10.2 Changing the Frequency...........................................................................181 9.10.3 Using Watchdog Timer Mode....................................................................182 9.10.4 Using Interval Timer Mode.......................................................................182 9.10.5 Usage Notes ..........................................................................................183 9.11 Notes on Board Design........................................................................................184
Section 10 Bus State Controller (BSC) .............................................. 187
10.1 Overview..........................................................................................................187 10.1.1 Features................................................................................................187 10.1.2 Block Diagram .......................................................................................188 10.1.3 Pin Configuration...................................................................................190 10.1.4 Register Configuration ............................................................................192
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10.1.5 Area Overview.......................................................................................193 10.1.6 PCMCIA Support ..................................................................................196 10.2 BSC Registers...................................................................................................200 10.2.1 Bus Control Register 1 (BCR1) ................................................................200 10.2.2 Bus Control Register 2 (BCR2) ................................................................203 10.2.3 Wait State Control Register 1 (WCR1) ......................................................204 10.2.4 Wait State Control Register 2 (WCR2) ......................................................205 10.2.5 Individual Memory Control Register (MCR) ...............................................208 10.2.6 DRAM Control Register (DCR) ...............................................................213 10.2.7 PCMCIA Control Register (PCR).............................................................215 10.2.8 Synchronous DRAM Mode Register (SDMR) .............................................216 10.2.9 Refresh Timer Control/Status Register (RTCSR) .........................................217 10.2.10 Refresh Timer Counter (RTCNT) ............................................................219 10.2.11 Refresh Time Constant Register (RTCOR)................................................220 10.2.12 Refresh Count Register (RFCR)..............................................................220 10.2.13 Cautions on Accessing Refresh Control Related Registers ............................221 10.3 BSC Operation..................................................................................................222 10.3.1 Endian/Access Size and Data Alignment .....................................................222 10.3.2 Description of Areas ...............................................................................228 10.3.3 Basic Interface........................................................................................231 10.3.4 DRAM Interface.....................................................................................237 10.3.5 Synchronous DRAM Interface ..................................................................253 10.3.6 Pseudo-SRAM Direct Connection .............................................................269 10.3.7 Burst ROM Interface...............................................................................278 10.3.8 PCMCIA Interface..................................................................................281 10.3.9 Waits between Access Cycles ...................................................................293 10.3.10 Bus Arbitration ....................................................................................294
Section 11 Timer (TMU)...............................................................297
11.1 Overview..........................................................................................................297 11.1.1 Features................................................................................................297 11.1.2 Block Diagram.......................................................................................297 11.1.3 Pin Configuration ..................................................................................299 11.1.4 Register Configuration ............................................................................299 11.2 TMU Registers..................................................................................................300 11.2.1 Timer Output Control Register (TOCR) .....................................................300 11.2.2 Timer Start Register (TSTR) ....................................................................301 11.2.3 Timer Control Register (TCR)..................................................................302 11.2.4 Timer Constant Register (TCOR)..............................................................305 11.2.5 Timer Counters (TCNT) ..........................................................................306 11.2.6 Input Capture Register (TCPR2)...............................................................307 11.3 TMU Operation.................................................................................................308 11.3.1 Overview ..............................................................................................308
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11.3.2 Basic Functions......................................................................................308 11.4 Interrupts......................................................................................................... .312 11.4.1 Status Flag Set Timing ...........................................................................312 11.4.2 Status Flag Clear Timing.........................................................................313 11.4.3 Interrupt Sources and Priorities..................................................................313 11.5 Usage Notes......................................................................................................314 11.5.1 Writing to Registers................................................................................314 11.5.2 Reading Registers ...................................................................................314 11.5.3 Clearing UNF in the TCR Register............................................................314
Section 12 Realtime Clock (RTC) .................................................... 315
12.1 Overview..........................................................................................................315 12.1.1 Features................................................................................................315 12.1.2 Block Diagram .......................................................................................315 12.1.3 Pin Configuration...................................................................................317 12.1.4 RTC Register Configuration.....................................................................318 12.2 RTC Registers...................................................................................................318 12.2.1 64-Hz Counter (R64CNT)........................................................................318 12.2.2 Second Counter (RSECCNT)....................................................................319 12.2.3 Minute Counter (RMINCNT) ...................................................................319 12.2.4 Hour Counter (RHRCNT)........................................................................320 12.2.5 Day of the Week Counter (RWKCNT)........................................................320 12.2.6 Date Counter (RDAYCNT) ......................................................................321 12.2.7 Month Counter (RMONCNT)...................................................................322 12.2.8 Year Counter (RYRCNT).........................................................................322 12.2.9 Second Alarm Register (RSECAR) ............................................................323 12.2.10 Minute Alarm Register (RMINAR)..........................................................323 12.2.11 Hour Alarm Register (RHRAR)...............................................................324 12.2.12 Day of the Week Alarm Register (RWKAR) ..............................................324 12.2.13 Date Alarm Register (RDAYAR) .............................................................325 12.2.14 Month Alarm Register (RMONAR) .........................................................326 12.2.15 RTC Control Register 1 (RCR1) .............................................................326 12.2.16 RTC Control Register 2 (RCR2) .............................................................328 12.3 RTC Operation..................................................................................................329 12.3.1 Initial Settings of Registers after Power-On.................................................329 12.3.2 Setting the Time ....................................................................................329 12.3.3 Reading the Time ...................................................................................331 12.3.4 Alarm Function......................................................................................332 12.3.5 Crystal Oscillator Circuit.........................................................................333 12.4 Usage Notes..................................................................................................... .334 12.4.1 Flag Clearing.........................................................................................334
Section 13 Serial Communication Interface (SCI).................................. 335
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13.1 Overview..........................................................................................................335 13.1.1 Features................................................................................................335 13.1.2 Block Diagram.......................................................................................336 13.1.3 Pin Configuration ..................................................................................337 13.1.4 Register Configuration ............................................................................337 13.2 Register Descriptions..........................................................................................338 13.2.1 Receive Shift Register (SCRSR)...............................................................338 13.2.2 Receive Data Register (SCRDR)...............................................................338 13.2.3 Transmit Shift Register (SCTSR) .............................................................338 13.2.4 Transmit Data Register (SCTDR)..............................................................339 13.2.5 Serial Mode Register (SCSMR)................................................................339 13.2.6 Serial Control Register (SCSCR)..............................................................342 13.2.7 Serial Status Register (SCSSR)................................................................345 13.2.8 Serial Port Register (SCSPTR).................................................................349 13.2.9 Bit Rate Register (SCBRR)......................................................................350 13.3 Operation .........................................................................................................358 13.3.1 Overview ..............................................................................................358 13.3.2 Operation in Asynchronous Mode..............................................................360 13.3.3 Multiprocessor Communication................................................................370 13.3.4 Synchronous Operation ...........................................................................378 13.4 SCI Interrupt Sources .........................................................................................388 13.5 Usage Notes......................................................................................................388
Section 14 Smart Card Interface.......................................................393
14.1 Overview..........................................................................................................393 14.1.1 Features................................................................................................393 14.1.2 Block Diagram.......................................................................................394 14.1.3 Pin Configuration ..................................................................................395 14.1.4 Register Configuration ............................................................................395 14.2 Register Descriptions..........................................................................................395 14.2.1 Smart Card Mode Register (SCSCMR) ......................................................396 14.2.2 Serial Status Register (SCSSR)................................................................397 14.3 Operation .........................................................................................................398 14.3.1 Overview ..............................................................................................398 14.3.2 Pin Connections ....................................................................................399 14.3.3 Data Format ..........................................................................................400 14.3.4 Register Settings....................................................................................401 14.3.5 Clock...................................................................................................403 14.3.6 Data Transmission and Reception ..............................................................405 14.4 Usage Notes......................................................................................................412 14.4.1 Receive Data Timing and Receive Margin in Asynchronous Mode...................412 14.4.2 Retransmission (Receive and Transmit Modes).............................................414
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Section 15 I/O Ports .................................................................... 417
15.1 Overview..........................................................................................................417 15.1.1 Features................................................................................................417 15.1.2 Block Diagram .......................................................................................417 15.1.3 Pin Configuration...................................................................................420 15.1.4 Register Configuration ............................................................................421 15.2 Register Descriptions ..........................................................................................421 15.2.1 Port Control Register (PCTR) ..................................................................421 15.2.2 Port Data Register (PDTR).......................................................................422 15.2.3 Serial Port Register (SCSPTR) .................................................................423
Section 16 Electrical Characteristics(-SH7708, SH7708S-)....................... 425
16.1 Absolute Maximum Ratings ................................................................................425 16.2 DC Characteristics..............................................................................................426 16.3 AC Characteristics..............................................................................................427 16.3.1 Clock Timing ........................................................................................428 16.3.2 Control Signal Timing............................................................................438 16.3.3 AC Bus Timing Specifications..................................................................442 16.3.4 Basic Timing.........................................................................................446 16.3.5 Burst ROM Timing ................................................................................449 16.3.6 DRAM Timing......................................................................................452 16.3.7 Synchronous DRAM Timing....................................................................462 16.3.8 Pseudo-SRAM Timing............................................................................473 16.3.9 PCMCIA Timing ...................................................................................478 16.3.10 Peripheral Module Signal Timing ............................................................485 16.3.11 AC Characteristics Test Conditions..........................................................488
Section 17 Electrical Characteristics (-SH7708R-) ................................. 489
17.1 Absolute Maximum Ratings ................................................................................489 17.2 DC Characteristics..............................................................................................490 17.3 AC Characteristics..............................................................................................491 17.3.1 Clock Timing ........................................................................................492 17.3.2 Control Signal Timing............................................................................498 17.3.3 AC Bus Timing Specifications..................................................................502 17.3.4 Basic Timing.........................................................................................506 17.3.5 Burst ROM Timing ................................................................................510 17.3.6 DRAM Timing......................................................................................513 17.3.7 Synchronous DRAM Timing....................................................................523 17.3.8 Pseudo-SRAM Timing............................................................................534 17.3.9 PCMCIA Timing ...................................................................................539 17.3.10 Peripheral Module Signal Timing ............................................................546 17.3.11 AC Characteristics Test Conditions..........................................................549
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Appendix A Pin Functions.............................................................551
A.1 Pin States..........................................................................................................551 A.2 Pin Specifications ...............................................................................................554 A.3 Handling of Unused Pins......................................................................................557 A.4 Pin States in Access to Each Address Space .............................................................558
Appendix B Control Registers.........................................................594
B.1 Register Address Map...........................................................................................594 B.2 Register Bit List .................................................................................................598 B.3 Register States in Reset and Power-Down States .......................................................604
Appendix C Delay Time Variation Due to Load Capacitance ......................608 Appendix D Package Dimensions.....................................................609
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Section 1 Overview and Pin Functions
1.1 SH7708 Series Features
The SH7708, SH7708S, and SH7708R(SH7708 Series) are 32-bit RISC (reduced instruction set computer) microcomputers, featuring object code upward-compatibility with SH-1 and SH-2 microcomputers. The SH7708R is completely pin compatible with the SH7708S. It includes an 8kbyte cache with a choice of write-back or write-through mode, and an MMU (memory management unit) with a 128-entry 4-way set associative TLB (translation lookaside buffer). The SH7708 Series have an on-chip bus state controller (BSC) that allows direct connection to DRAM, synchronous DRAM (SDRAM), and pseudo-SRAM (PSRAM) without external circuitry. Its 16-bit fixed-length instruction set enables program code size to be reduced by almost 50% compared with 32-bit instructions. The features of the SH7708 Series are summarized in table 1.1.
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Table 1.1 SH7708 Series Features
Item CPU Features * * * Original Hitachi SuperH RISC engine architecture 32-bit internal data bus General-register machine Sixteen 32-bit general registers (eight 32-bit bank registers) Five 32-bit control registers Four 32-bit system registers * RISC-type instruction set (upward compatibility with the SH-1 and SH-2 series) Instruction length: 16-bit fixed length for improved code efficiency Load-store architecture Delayed branch instructions C-oriented instruction set * * * * * Operating modes, * clock pulse generator * Instruction execution time: one instruction/cycle for basic instructions Logical address space: 4 Gbytes (448-Mbyte actual memory space) Space identifier ASID: 8 bits, 256 logical address spaces On-chip multiplier Five-stage pipeline Clock mode: selected from an on-chip oscillator module, a frequencydoubling circuit, or a clock output by combining them by PLL synchronization Processing states: Power-on reset state Manual reset state Exception processing state Program execution state Power-down state Bus-released state * Power-down modes: Sleep mode Standby mode Hardware Standby mode(SH7708S, SH7708R only) * * On-chip clock pulse generator One watchdog timer channel
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Table 1.1 SH7708 Series Features (cont)
Item Memory management unit (MMU) Features * * * * * * * Cache memory * 4 Gbytes of address space, 256 address spaces (8-bit ASID) Supports single virtual memory mode and multiple virtual memory mode Paging system Supports multiple page sizes: 1 or 4 kbytes 128-entry, 4-way set associative TLB Supports software selection of replacement method and random-replacement algorithms Contents of TLB are directly accessible by address mapping Choice of operating mode Normal mode (8-kbyte cache) RAM mode (4-kbyte cache + 4-kbyte RAM) * Mixed instruction/data, 128 entries, 16-byte block length 4-way set associative (8-kbyte cache) 2-way set associative (4-kbyte cache) * * * Interrupt controller (INTC) User break controller (UBC) * * * * * * * Selectable write method (write-back/write-through), LRU (least recently used) replacement algorithm Single-stage write-back buffer Contents of TLB can be accessed directly by address mapping (can be used as on-chip memory) 5 external interrupt pins (NMI, IRL0 to IRL3) Encoded input of 15 external interrupt sources via pins IRL0 to IRL3 On-chip peripheral interrupts: priority levels set for each module Supports debugging by user break interrupts 2 break channels Addresses, data values, type of access, and data size can all be set as break conditions Supports a sequential break function
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Table 1.1 SH7708 Series Features (cont)
Item Bus state controller (BSC) Features * * Supports external memory access 32/16/8-bit external data bus Physical address space divided into seven areas, each a maximum 64 Mbytes, with the following features settable for each area: Bus size (8, 16, or 32 bits) Number of wait cycles (also supports a hardware wait function) Setting the type of space enables direct connection to DRAM, synchronous DRAM, pseudo-SRAM, and burst ROM Supports fast page mode and EDO for DRAM Supports PCMCIA interface Outputs chip select signal (CS0-CS6) for corresponding area * DRAM/synchronous DRAM/pseudo-SRAM refresh function Programmable refresh interval Supports CAS-before-RAS refresh and self-refresh modes * * Timer * * * * Realtime clock (RTC) * * * * * * * Note: SH7708S only DRAM/synchronous DRAM/pseudo-SRAM burst access function Usable as either big- or little-endian machine 3-channel auto-reload type 32-bit timer Input capture function 6 types of counter input clock can be selected Maximum resolution: 2 MHz On-chip clock and calendar functions On-chip 32-kHz crystal oscillator circuit with a maximum resolution (interrupt cycle) of 1/256 second Selection of asynchronous or synchronous mode Full-duplex communication Supports smart card interface 144-pin plastic QFP(FP-144) 144-pin plastic TQFP (TFP-144) *
Serial communication interface (SCI) Package
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Table 1.1 SH7708 Series Features (cont)
Item Product Line-up Product Number SH7708 On-chip Voltage 3.3V0.3 V 3.3V0.3 V Operation Frequency 60MHz Model HD6417708F60 Package 144-pin Plastic LQFP (FP-144F) Features
SH7708S
60MHz
HD6417708SF60 HD6417708STF60 144-pin Plastic TQFP (TFP-144) 144-pin Plastic L-QFP (FP-144F)
SH7708R
3.15-3.6V (typ.)
100MHz
HD6417708RF100
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1.2
Block Diagram
Figure 1.1 shows a block diagram of the SH7708 Series.
Multiplier
CPU
32-bit virtual address bus
MMU (memory management unit)
32-bit data bus
Interrupt controller
Mixed instruction/ data TLB
User break controller (2 channels)
SCI (serial communication interface)
Peripheral address bus
peripheral data
bus
Cache controller
Realtime clock
Mixed instruction/ data cache memory
32-bit physical address bus
32-bit data bus
Bus state controller
PLL built-in clock oscillator WDT (watchdog timer)
External bus interface
I/O ports
Figure 1.1
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SH7708 Series Block Diagram
16-bit
Timer (3 channels)
1.3
1.3.1
Pin Description
Pin Arrangement
100
90
CS5/CE1A CS4 CS3 CS2 CS1 CS0 Vss Vcc WE3/DQMUU/ICIOWR WE2/DQMUL/ICIORD CASHH/CAS2H CASHL/CAS2L Vss Vcc WE1/DQMLU WE0/DQMLL CASLH CASLL/CAS/OE Vss Vcc RAS/CE MD5/RAS2 CKE WAIT Vss TCLK Vcc (RTC)*2 XTAL2 EXTAL2 Vss (RTC)*2 Vcc D31 D30 D29 D28 Vss
80
XTAL EXTAL Vcc (PLL2)*2 CAP2 Vss (PLL2)*2 Vcc (PLL1)*2 CAP1 Vss (PLL1)*2
CS6/CE1B RD RDWR BS MD3/CE2A MD4/CE2B Vcc CKIO Vss NC*1 STATUS0 STATUS1 BACK IRQOUT IOIS16 IRL0 IRL1 IRL2 IRL3 NMI RESET BREQ MD0/SCK MD1/TXD MD2/RXD Vcc Vss
*4
70
120 60 SH7708(FP-144F) SH7708S(TFP-144, FP-144F) SH7708R(FP-144F) Top view
130
50
140 40 144
10 20
D27 D26 D25 D24 D23/Port7 Vss Vcc D22/Port6 D21/Port5 D20/Port4 D19/Port3 D18/Port2 D17/Port1 D16/Port0 D15 D14 Vss Vcc Vss Vcc D13 D12 D11 D10 D9 D8 D7 D6 D5 Vss Vcc D4 D3 D2 D1 D0
Notes: 1.Make no connection. 2.Power supply pins for the on-chip RTC and on-chip PLL. These pins must be connected to the power supply even if the RTC or PLL are not used. 3.Power supply pins for the on-chip PLL. Except in hardware standby mode, these pins must be connected to the power supply even if the PLL is not used. 4. SH7708:Vcc SH7708S,SH7708R:CA
Figure 1.2
Pin Arrangement
7
30
A25 A24 A23 Vcc Vss A22 A21 A20 A19 A18 A17 A16 Vcc Vss A15 A14 A13 Vcc Vss A12 A11 A10 Vcc Vss A9 A8 A7 A6 A5 A4 Vcc Vss A3 A2 A1 A0
1
1.3.2
SH7708 Series Pin Functions
Table 1.2 SH7708 Series Pin Functions
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 Terminal D27 D26 D25 D24 D23/Port7 VSS VCC D22/Port6 D21/Port5 D20/Port4 D19/Port3 D18/Port2 D17/Port1 D16/Port0 D15 D14 VSS VCC VSS VCC D13 D12 D11 D10 D9 D8 D7 D6 D5 I/O I/O I/O I/O I/O I/O Power Power I/O I/O I/O I/O I/O I/O I/O I/O I/O Power Power Power Power I/O I/O I/O I/O I/O I/O I/O I/O I/O Description Data bus Data bus Data bus Data bus Data bus/port Power (0 V) Power (3.3 V) Data bus/port Data bus/port Data bus/port Data bus/port Data bus/port Data bus/port Data bus/port Data bus Data bus Power (0 V) Power (3.3 V) Power (0 V) Power (3.3 V) Data bus Data bus Data bus Data bus Data bus Data bus Data bus Data bus Data bus
8
Table 1.2 SH7708 Series Pin Functions (cont)
No. 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Terminal VSS VCC D4 D3 D2 D1 D0 A0 A1 A2 A3 VSS VCC A4 A5 A6 A7 A8 A9 VSS VCC A10 A11 A12 VSS VCC A13 A14 A15 VSS VCC I/O Power Power I/O I/O I/O I/O I/O O O O O Power Power O O O O O O Power Power O O O Power Power O O O Power Power Description Power (0 V) Power (3.3 V) Data bus Data bus Data bus Data bus Data bus Address bus Address bus Address bus Address bus Power (0 V) Power (3.3 V) Address bus Address bus Address bus Address bus Address bus Address bus Power (0 V) Power (3.3 V) Address bus Address bus Address bus Power (0 V) Power (3.3 V) Address bus Address bus Address bus Power (0 V) Power (3.3 V)
9
Table 1.2 SH7708 Series Pin Functions (cont)
No. 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81(SH7708) Terminal A16 A17 A18 A19 A20 A21 A22 VSS VCC A23 A24 A25 VSS (PLL1)*2 I/O O O O O O O O Power Power O O O Power O Power Power O Power I O Power I Power Power I I/O I/O I I I I Description Address bus Address bus Address bus Address bus Address bus Address bus Address bus Power (0 V) Power (3.3 V) Address bus Address bus Address bus Power (0 V) for PLL1 External capacitance pin for PLL1 Power (3.3 V) for PLL1 Power (0 V) for PLL2 External capacitance pin for PLL2 Power (3.3 V) for PLL2 External clock/crystal oscillator pin Crystal oscillator pin Power(3.3V) Chip active Power (0 V) Power (3.3 V) Operating mode pin/serial data input Operating mode pin/serial data output Operating mode pin/serial clock Bus request Reset Nonmaskable interrupt request External interrupt source input
CAP1 VCC VSS (PLL1)*2
(PLL2)*2
CAP2 VCC (PLL2)*2
EXTAL XTAL VCC
81(SH7708S, CA SH7708R) 82 83 84 85 86 87 88 89 90 VSS VCC MD2/RXD MD1/TXD MD0/SCK BREQ RESET NMI IRL3
10
Table 1.2 SH7708 Series Pin Functions (cont)
No. 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 Terminal IRL2 IRL1 IRL0 IOIS16 IRQOUT BACK STATUS1 STATUS0 NC VSS CKIO VCC MD4/CE2B MD3/CE2A BS RD/WR RD CS6/CE1B CS5/CE1A CS4 CS3 CS2 CS1 CS0 VSS VCC WE3 /DQMUU/ICIOWR WE2 /DQMUL/ICIORD CASHH/CAS2H CASHL /CAS2L VSS I/O I I I I O O O O O Power I/O Power I/O I/O O O O O O O O O O O Power Power O O O O Power Description External interrupt source input External interrupt source input External interrupt source input IO16-bit instruction Bus request notification output Bus acknowledge Processor status Processor status Leave unconnected Power (0 V) System clock I/O Power (3.3 V) Operating mode pin/PCMCIA CE pin Operating mode pin/PCMCIA CE pin Bus cycle start Read/write Read pulse Chip select 6/PCMCIA CE pin Chip select 5/PCMCIA CE pin Chip select 4 Chip select 3 Chip select 2 Chip select 1 Chip select 0 Power (0 V) Power (3.3 V) D31-D24 selection signal/IO write D23-D16 selection signal/IO read D31-D24/D15-D8 selection signal D23-D16/D7-D0 selection signal Power (0 V)
11
Table 1.2 SH7708 Series Pin Functions (cont)
No. 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 Terminal VCC WE1 /DQMLU WE0 /DQMLL CASLH CASLL/CAS/OE VSS VCC RAS/CE MD5/RAS2 CKE WAIT VSS TCLK VCC (RTC)*3 I/O Power O O O O Power Power O I/O O I Power I/O Power O I Power Power I/O I/O I/O I/O Power Description Power (3.3 V) D15-D8 selection signal D7-D0 selection signal D15-D8 selection signal D7-D0 selection/memory selection signal Power (0 V) Power (3.3 V) RAS for DRAM, SDRAM/CE for PSRAM Operating mode pin/RAS for DRAM Clock enable control for SDRAM Hardware wait request Power (0 V) Clock I/O for TMU/RTC Power (3.3 V) Crystal oscillator pin for on-chip RTC Crystal oscillator pin for on-chip RTC Power (0 V) Power (3.3 V) Data bus Data bus Data bus Data bus Power (0 V)
XTAL2 EXTAL2 VSS VCC D31 D30 D29 D28 VSS (RTC)*3
Notes: 1. Except in hardware standby mode, connect all VCC and VSS pins to the system power supply (power should be supplied constantly). In hardware standby mode, power should be supplied at least to VCC (RTC) and VSS (RTC). If power is not supplied to VCC and VSS pins other than VCC (RTC) and VSS (RTC), hold the CA pin low. 2. Power should be supplied regardless of whether or not the on-chip PLL is used. 3. Power should be supplied regardless of whether or not the RTC is used.
12
Section 2 CPU
2.1
2.1.1
Register Configuration
Privileged Mode and Banks
Processor Modes: There are two processor modes: user mode and privileged mode. The SH7708 Series normally operates in user mode, and enters privileged mode when an exception occurs or an interrupt is accepted. There are three kinds of registers--general registers, system registers, and control registers--and the registers that can be accessed differ in the two processor modes. General Registers: There are 16 general registers, designated R0 to R15. General registers R0 to R7 are banked registers which are switched by a processor mode change. In privileged mode, the register bank bit (RB) in the status register (SR) defines which banked register set is accessed as general registers, and which set is accessed only through the load control register (LDC) and store control register (STC) instructions. When the RB bit is 1, BANK1 general registers R0_BANK1-R7_BANK1 and non-banked general registers R8-R15 function as the general register set, with BANK0 general registers R0_BANK0- R7_BANK0 accessed only by the LDC/STC instructions. When the RB bit is 0, BANK0 general registers R0_BANK0-R7_BANK0 and nonbanked general registers R8-R15 function as the general register set, with BANK1 general registers R0_BANK1- R7_BANK1 accessed only by the LDC/STC instructions. In user mode, the 16 registers comprising bank 0 general registers R0_BANK0-R7_BANK0 and non-banked registers R8-R15 can be accessed as general registers R0-R15, and bank 1 general registers R0_BANK1- R7_BANK1 cannot be accessed. Control Registers: Control registers comprise the global base register (GBR) and status register (SR) which can be accessed in both processor modes, and the saved status register (SSR), saved program counter (SPC), and vector base register (VBR) which can only be accessed in privileged mode. Some bits of the status register (such as the RB bit) can only be accessed in privileged mode. System Registers: System registers comprise the multiply and accumulate registers (MACL/MACH), the procedure register (PR), and the program counter (PC). Access to these registers does not depend on the processor mode. The register configuration in each mode is shown in figures 2.1 and 2.2. Switching between user mode and privileged mode is controlled by the processor mode bit (MD) in the status register.
13
31 R0_BANK0*1, *2 R1_BANK0*2 R2_BANK0*2 R3_BANK0*2 R4_BANK0*2 R5_BANK0*2 R6_BANK0*2 R7_BANK0*2 R8 R9 R10 R11 R12 R13 R14 R15 SR GBR MACH MACL PR
0
PC User mode register configuration
Notes: 1. 2.
R0 functions as an index register in the indexed register-indirect addressing mode and indexed GBR-indirect addressing mode. Banked register
Figure 2.1
User Mode Register Configuration
14
31 R0_BANK1*1, *2 R1_BANK1*2 R2_BANK1*2 R3_BANK1*2 R4_BANK1*2 R5_BANK1*2 R6_BANK1*2 R7_BANK1*2 R8 R9 R10 R11 R12 R13 R14 R15 SR SSR GBR MACH MACL PR VBR PC SPC R0_BANK0*1, *3 R1_BANK0*3 R2_BANK0*3 R3_BANK0*3 R4_BANK0*3 R5_BANK0*3 R6_BANK0*3 R7_BANK0*3
0
31 R0_BANK0*1, *3 R1_BANK0*3 R2_BANK0*3 R3_BANK0*3 R4_BANK0*3 R5_BANK0*3 R6_BANK0*3 R7_BANK0*3 R8 R9 R10 R11 R12 R13 R14 R15 SR SSR GBR MACH MACL PR VBR PC SPC R0_BANK1*1, *2 R1_BANK1*2 R2_BANK1*2 R3_BANK1*2 R4_BANK1*2 R5_BANK1*2 R6_BANK1*2 R7_BANK1*2
0
Notes: 1. R0 functions as an index register in the indexed register-indirect addressing mode and indexed GBRindirect addressing mode. 2. Banked register When the RB bit of the SR register is 1, the register can be accessed for general use. When the RB bit is 0, it can only be accessed with the LDC/STC instruction. 3. Banked register When the RB bit of the SR register is 0, the register can be accessed for general use. When the RB bit is 1, it can only be accessed with the LDC/STC instruction.
a. Privileged mode register configuration (RB = 1)
b. Privileged mode register configuration (RB = 0)
Figure 2.2
Privileged Mode Register Configuration
15
Register values after a reset are shown in table 2.1. Table 2.1 Initial Register Values
Type General registers Control registers Registers R0 to R15 SR Initial Value Undefined MD bit = 1, RB bit = 1, BL bit = 1, I3- I0 = 1111 (H'F), reserved bits = 0, others undefined Undefined H'00000000 Undefined H'A0000000
GBR, SSR, SPC VBR System registers MACH, MACL, PR PC Note: Initialized by a power-on reset or manual reset.
2.1.2
General Registers
There are 16 general registers, designated R0 to R15 (figure 2.3). General registers R0 to R7 are banked registers, with a different R0-R7 register bank (R0_BANK0-R7_BANK0 or R0_BANK1- R7_BANK1) being accessed according to the processor mode. For details, see section 2.1.1, Privileged Mode and Banks.
General Registers 31 R0*1, *2 R1*2 R2*2 R3*2 R4*2 R5*2 R6*2 R7*2 R8 R9 R10 R11 R12 R13 R14 R15 0 Notes: 1. R0 functions as an index register in the indexed register-indirect addressing mode and indexed GBR-indirect addressing mode. In some instructions, only R0 can be used as the source register or destination register. 2. R0-R7 are banked registers. In privileged mode, SR.RB specifies which banked registers are accessed as general registers (R0_BANK0-R7_BANK0 or R0_BANK1-R7_BANK1).
Figure 2.3
General Registers
16
2.1.3
System Registers
System registers can be accessed by the LDS and STS instructions. When an exception occurs, the contents of the program counter (PC) are saved in the saved program counter (SPC). The SPC contents are restored to the PC by the RTE instruction used at the end of the exception handling. There are four system registers, as follows. * * * * Multiply and accumulate high register (MACH) Multiply and accumulate low register (MACL) Procedure register (PR) Program counter (PC)
The system register configuration is shown in figure 2.4.
System Registers 31 MACH MACL 0 Multiply and Accumulate High and Low Registers (MACH/L) Store the results of multiply-and-accumulate operations. Its contents are undefined after a reset. 0 PR Procedure Register (PR) Stores the return address for exiting a subroutine procedure. Its contents are undefined after a reset. Program Counter (PC) Indicates the address four addresses (two instructions) ahead of the currently executing instruction. Initialized to H'A0000000 by a reset.
31
31 PC
0
Figure 2.4 2.1.4 Control Registers
System Registers
Control registers can be accessed in privileged mode using the LDC and STC instructions. The GBR register can also be accessed in user mode. There are five control registers, as follows: * * * * * Status register (SR) Saved status register (SSR) Saved program counter (SPC) Global base register (GBR) Vector base register (VBR)
17
31 SSR
0 Saved Status Register (SSR)
Stores current SR value at time of exception to indicate processor status in return to instruction stream from exception handler. Its contents are undefined after a reset.
31 SPC
0 Saved Program Counter (SPC)
Stores current PC value at time of exception to indicate return address at completion of exception handling. Its contents are undefined after a reset.
31 GBR
0 Global Base Register (GBR)
Stores base address of GBR-indirect addressing mode. The GBR-indirect addressing mode is used for on-chip supporting module register area data transfers and logic operations. The GBR register can also be accessed in user mode. Its contents are undefined after a reset.
31 VBR 31 30 29 28 27
0 Vector Base Register (VBR)
Stores base address of exception handling vector area. Initialized to H'0000000 by a reset.
1 0 Status 0 MD RB BL 0----------------------------0 M Q I3 I2 I1 I0 0 0 S T register (SR)
10 9 8 7
3
MD: Processor operation mode bit: Indicates the processor operation mode as follows: MD =1: Privileged mode; MD = 0: User mode MD is set to 1 on generation of an exception or interrupt , and is initialized to 1 by a reset. RB: Register bank bit: Determines the bank of general registers R0-R7 used in processing mode. RB = 1: R0_BANK1-R7_BANK1 and R8-R15 are general registers, and R0_BANK0- R7_BANK0 can be accessed by LDC/STC instructions. RB = 0: R0_BANK0-R7_BANK0 and R8-R15 are general registers, and R0_BANK1- R7_BANK1 can be accessed by LDC/STC instructions. RB is set to 1 on generation of an exception or interrupt , and is initialized to 1 by a reset. BL: Block bit BL = 1: Exceptions and interrupts are suppressed. See section 4, Exception Handling, for details. BL = 0: Exceptions and interrupts are accepted. BL is set to 1 on generation of an exception or interrupt , and is initialized to 1 by a reset. M and Q bits: Used by the DIV0S/U and DIV1 instructions. I3-I0 bits: Interrupt mask bits: 4-bit field indicating the interrupt request mask level. I3-I0 do not change to the interrupt acceptance level when an interrupt is generated. Initialized to B'1111 by a reset. S bit: Used by the MAC instruction. T bit: Used by the MOVT, CMP/cond, TAS, TST, BT, BF, SETT, CLRT, and DT instructions to indicate true (1) or false (0). Used by the ADDV/C, SUBV/C, DIV0U/S, DIV1, NEGC, SHAR/L, SHLR/L, ROTR/L, and ROTCR/L instructions to indicate a carry, borrow, overflow, or underflow. 0 bits: These bits always read 0, and the write value should always be 0. Note: The M, Q, S, and T bits can be set or cleared by special instructions in user mode. Their values are undefined after a reset. All other bits can be read or written in privileged mode.
Figure 2.5
Register Set Overview, Control Registers
18
2.2
2.2.1
Data Formats
Data Format in Registers
Register operands are always longwords (32 bits, figure 2.6). When a memory operand is only a byte (8 bits) or a word (16 bits), it is sign-extended into a longword when loaded into a register.
31 Longword 0
Figure 2.6 2.2.2 Data Format in Memory
Longword
Memory data formats are classified into bytes, words, and longwords. Memory can be accessed in 8-bit byte, 16-bit word, or 32-bit longword form. A memory operand less than 32 bits in length is sign-extended before being stored in a register. A word operand must be accessed starting from a word boundary (even address of a 2-byte unit: address 2n), and a longword operand starting from a longword boundary (even address of a 4-byte unit: address 4n). An address error will result if this rule is not observed. A byte operand can be accessed from any address. Big-endian or little-endian byte order can be selected for the data format. The endian mode should be set with the MD5 external pin in a power-on reset. Big-endian mode is selected when the MD5 pin is low, and little-endian when high. The endian mode cannot be changed dynamically. Bit positions are numbered left to right from most-significant to least-significant. Thus, in a 32-bit longword, the leftmost bit, bit 31, is the most significant bit and the rightmost bit, bit 0, is the least significant bit. The data format in memory is shown in figure 2.7. In little-endian mode, data written in byte-size (8-bit) units should be read in byte-size units, and data written in word-size (16-bit) units should be read in word-size units.
19
Address A + 1 Address A + 3
Address A + 10 Address A + 8
Address A Address A + 2 Address A + 11 Address A + 9 23 70 23 70 31 15 31 15 Address A Byte0 Byte1 Byte2 Byte3 Byte3 Byte2 Byte1 Byte0 Address A + 4 Word0 Word1 Word1 Word0 Address A + 8 Longword Longword Big-endian mode Little-endian mode
Address A + 8 Address A + 4 Address A
Figure 2.7
Byte, Word, and Longword Alignment
2.3
2.3.1
Instruction Features
Execution Environment
Data Length: The SH7708 Series instruction set is implemented with fixed-length 16-bit wide instructions executed in a pipelined sequence with single-cycle execution for most instructions. All operations are executed in 32-bit longword units. Memory can be accessed in 8-bit byte, 16-bit word, or 32-bit longword units, with byte or word units sign-extended into 32-bit longwords. Literals are sign-extended in arithmetic operations (MOV, ADD, and CMP/EQ instructions) and zero-extended in logical operations (TST, AND, OR, and XOR instructions). Load/Store Architecture: The SH7708 Series features a load-store architecture in which basic operations are executed in registers. Operations requiring memory access are executed in registers following register loading, except for bit-manipulation operations such as logical AND functions, which are executed directly in memory. Delayed Branching: Unconditional branching is implemented as delayed branch operations. Pipeline disruptions due to branching are minimized by the execution of the instruction following the delayed branch instruction prior to branching. Conditional branch instructions are of two kinds, delayed and normal. BRA ADD TRGET R1, R0
;ADD is executed prior to branching to TRGET
20
T bit: The T bit in the status register (SR) is used to indicate the result of compare operations, and is read as a TRUE/FALSE condition determining if a conditional branch is taken or not. To improve processing speed, the T bit logic state is modified only by specific operations. An example of how the T bit may be used in a sequence of operations is shown below. ADD CMP/EQ BT #1, R0 R1, R0 TRGET ;T bit not modified by ADD operation ;T bit set to 1 when R0 = 0 ;branch taken to TRGET when T bit = 1 (R0 = 0)
Literals: Byte-length literals are inserted directly into the instruction code as immediate data. To maintain the 16-bit fixed-length instruction code, word or longword literals are stored in a table in main memory rather than inserted directly into the instruction code. The memory table is accessed by the MOV instruction using PC-relative addressing with displacement, as follows: MOV.W @(disp, PC), R0
Absolute Addresses: As with word and longword literals, absolute addresses must also be stored in a table in main memory. The value of the absolute address is transferred to a register and the operand access is specified by indexed register-indirect addressing, with the absolute address loaded (like word and longword immediate data) during instruction execution. 16-Bit and 32-Bit Displacements: In the same way, 16-bit and 32-bit displacements also must be stored in a table in main memory. Exactly like absolute addresses, the displacement value is transferred to a register and the operand access is specified by indexed register-indirect addressing, loading the displacement (like word and longword immediate data) during instruction execution.
21
2.3.2
Addressing Modes
Addressing modes and effective address calculation methods are shown in table 2.2. Table 2.2 Addressing Modes and Effective Addresses
Addressing Instructio Mode n Format Effective Address Calculation Method Calculation Formula Register direct Rn Register indirect @Rn Effective address is register Rn. (Operand is register Rn contents.) Effective address is register Rn contents. Rn Rn Rn After instruction execution Byte: Rn + 1 Rn Word: Rn + 2 Rn Longword: Rn + 4 Rn -- Rn
Register @Rn+ indirect with post-increment
Effective address is register Rn contents. A constant is added to Rn after instruction execution: 1 for a byte operand, 2 for a word operand, 4 for a longword operand. Rn Rn + 1/2/4 1/2/4 + Rn
Register @-Rn indirect with pre-decrement
Effective address is register Rn contents, Byte: Rn - 1 Rn decremented by a constant beforehand: 1 for Word: Rn - 2 Rn a byte operand, 2 for a word operand, 4 for a Longword: Rn - 4 Rn longword operand. (Instruction executed Rn with Rn after calculation) Rn - 1/2/4 - Rn - 1/2/4 1/2/4
22
Table 2.2 Addressing Modes and Effective Addresses (cont)
Addressing Instructio Mode n Format Effective Address Calculation Method Calculation Formula Register @(disp:4, indirect with Rn) displacement Effective address is register Rn contents with 4-bit displacement disp added. After disp is zero-extended, it is multiplied by 1 (byte), 2 (word), or 4 (longword), according to the operand size.
Rn disp (zero-extended) x 1/2/4 + Rn + disp x 1/2/4
Byte: Rn + disp Word: Rn + disp x 2 Longword: Rn + disp x 4
Indexed @(R0, Rn) Effective address is sum of register Rn and register indirect R0 contents. Rn + R0 GBR indirect @(disp:8, with GBR) displacement Effective address is register GBR contents with 8-bit displacement disp added. After disp is zero-extended, it is multiplied by 1 (byte), 2 (word), or 4 (longword), according to the operand size.
GBR disp (zero-extended) x 1/2/4 + GBR + disp x 1/2/4
Rn + R0
Rn + R0
Byte: GBR + disp Word: GBR + disp x 2 Longword: GBR + disp x 4
Indexed GBR @(R0, GBR)Effective address is sum of register GBR and GBR + R0 indirect R0 contents. GBR + R0 GBR + R0
23
Table 2.2 Addressing Modes and Effective Addresses (cont)
Addressing Instructio Mode n Format Effective Address Calculation Method Calculation Formula PC-relative @(disp:8, with PC) displacement Effective address is register PC contents with 8-bit displacement disp added. After disp is zero-extended, it is multiplied by 2 (word), or 4 (longword), according to the operand size. With a longword operand, the lower 2 bits of PC are masked.
PC (for longword) & H'FFFFFFFC + disp (zero-extended) x 2/4 PC + disp x 2 or PC&H'FFFFFFFC + disp x 4
Word: PC + disp x 2 Longword: PC & H'FFFF FFFC + disp x 4
PC-relative
disp:8
Effective address is register PC contents with 8-bit displacement disp added after being sign-extended and multiplied by 2.
PC disp (sign-extended) x 2 + PC + disp x 2
PC + disp x 2
disp:12
Effective address is register PC contents with 12-bit displacement disp added after being sign-extended and multiplied by 2.
PC disp (sign-extended) x 2 + PC + disp x 2
PC + disp x 2
24
Table 2.2 Addressing Modes and Effective Addresses (cont)
Addressing Instructio Mode n Format Effective Address Calculation Method Calculation Formula PC-relative Rn Effective address is sum of register PC and Rn contents. PC + Rn Immediate #imm:8 #imm:8 #imm:8 8-bit immediate data imm of TST, AND, OR, or -- XOR instruction is zero-extended. 8-bit immediate data imm of MOV, ADD, or CMP/EQ instruction is sign-extended. 8-bit immediate data imm of TRAPA instruction is zero-extended and multiplied by 4. -- -- PC + Rn PC + Rn
Note: For the addressing modes below that use a displacement (disp), the assembler descriptions in this manual show the value before scaling (x1, x2, or x4) is performed according to the operand size. This is done to clarify the operation of the IC. Refer to the relevant assembler notation rules for the actual assembler descriptions. @ (disp:4, Rn) ; Register indirect with displacement @ (disp:8, Rn) ; GBR indirect with displacement @ (disp:8, PC) ; PC-relative with displacement disp:8, disp:12; PC-relative
25
2.3.3
Instruction Formats
Table 2.3 explains the meaning of instruction formats and source and destination operands. The meaning of the operands depends on the operation code. The following symbols are used. xxxx: mmmm: nnnn: iiii: dddd: Operation code Source register Destination register Immediate data Displacement
Table 2.3 Instruction Formats
Instruction Format 0 format 15 xxxx n format 15 xxxx nnnn xxxx xxxx Control register or system register Control register or system register m format 15 xxxx mmmm xxxx xxxx 0 mmmm: register direct mmmm: register indirect with postincrement mmmm: register indirect mmmm: PCrelative using Rm xxxx xxxx xxxx 0 -- nnnn: register direct nnnn: register direct nnnn: register indirect with pre-decrement Control register or system register Control register or system register -- -- MOVT Rn 0 S our ce Operand -- Destination Operand -- Instruction Example NOP
STS MACH,Rn STC.L SR,@-Rn LDC Rm,SR LDC.L @Rm+,SR JMP BRAF @Rm Rm
26
Table 2.3 Instruction Formats (cont)
Instruction Format nm format 15 xxxx nnnn mmmm xxxx S our ce Operand 0 mmmm: register direct mmmm: register direct mmmm: register indirect with postincrement (multiply-andaccumulate operation) nnnn: * register indirect with postincrement (multiply-andaccumulate operation) mmmm: register indirect with postincrement mmmm: register direct mmmm: register direct md format 15 xxxx nd4 format 15 xxxx xxxx nnnn dddd xxxx mmmm dddd 0 mmmmdddd: register indirect with displacement 0 R0 (register direct) nnnn: register direct nnnn: register indirect with pre-decrement nnnn: indexed register indirect R0 (register direct) nnnndddd: register indirect with displacement MOV.L @Rm+,Rn MOV.L Rm,@-Rn MOV.L Rm,@(R0,Rn) MOV.B @(disp,Rm),R0 MOV.B R0,@(disp,Rn) Destination Operand nnnn: register direct nnnn: register indirect MACH,MACL Instruction Example ADD Rm,Rn
MOV.L Rm,@Rn MAC.W @Rm+,@Rn+
27
Table 2.3 Instruction Formats (cont)
Instruction Format nmd format 15 xxxx S our ce Operand Destination Operand nnnndddd: register indirect with displacement nnnn: register direct R0 (register direct) dddddddd: GBR indirect with displacement R0 (register direct) -- -- Instruction Example MOV.L Rm,@(disp,Rn)
0 mmmm: register direct nnnn mmmm dddd
mmmmdddd: register indirect with displacement d format 15 xxxx xxxx dddd dddd 0 dddddddd: GBR indirect with displacement R0 (register direct)
MOV.L @(disp,Rm),Rn MOV.L @(disp,GBR),R0 MOV.L R0,@(disp,GBR)
dddddddd: PC-relative with displacement dddddddd: PC-relative d12 format 15 xxxx nd8 format 15 xxxx i format 15 xxxx xxxx iiii iiii iiiiiiii: immediate iiiiiiii: immediate ni format 15 xxxx nnnn iiii iiii 0 iiiiiiii: immediate nnnn dddd dddd dddd dddd dddd 0 dddddddddddd: PC-relative 0 dddddddd: PC-relative with displacement 0 iiiiiiii: immediate
MOVA @(disp,PC),R0 BF label
BRA label (label = disp + PC) MOV.L @(disp,PC),Rn AND.B #imm, @(R0,GBR) AND #imm,R0 TRAPA #imm ADD #imm,Rn
nnnn: register direct Indexed GBR indirect R0 (register direct) -- nnnn: register direct
Note: In a multiply-and-accumulate instruction, nnnn is the source register.
28
2.4
2.4.1
Instruction Set
Instruction Set Classified by Function
The SH7708 Series instruction set includes 68 basic instruction types, as listed in table 2.4. Table 2.4 Classification of Instructions
Classificati on Data transfer Types 5 Operatio n Code MOV MOVA MOVT SWAP XTRCT Arithmetic operations 21 ADD ADDC ADDV CMP/cond DIV1 DIV0S DIV0U DMULS DMULU DT EXTS EXTU MAC Function Data transfer Effective address transfer T bit transfer Swap of upper and lower bytes Extraction of middle of linked registers Binary addition Binary addition with carry Binary addition with overflow check Comparison Division Initialization of signed division Initialization of unsigned division Signed double-precision multiplication Unsigned double-precision multiplication Decrement and test Sign extension Zero extension Multiply-and-accumulate operation, double-precision multiply-and-accumulate operation 33 No. of Instructio ns 39
29
Table 2.4 Classification of Instructions (cont)
Classificati on Arithmetic operations (cont) Types 21 Operatio n Code Function MUL MULS MULU NEG NEGC SUB SUBC SUBV Logic operations 6 AND NOT OR TAS TST XOR Shift 12 ROTL ROTR ROTCL ROTCR SHAL SHAR SHLL SHLLn SHLR SHLRn SHAD SHLD Double-precision multiplication Signed multiplication Unsigned multiplication Negation Negation with borrow Binary subtraction Binary subtraction with borrow Binary subtraction with underflow check Logical AND Bit inversion Logical OR Memory test and bit set Logical AND and T bit set Exclusive OR One-bit left rotation One-bit right rotation One-bit left rotation with T bit One-bit right rotation with T bit One-bit arithmetic left shift One-bit arithmetic right shift One-bit logical left shift n-bit logical left shift One-bit logical right shift n-bit logical right shift Dynamic arithmetic shift Dynamic logical shift 16 14 No. of Instructio ns 33
30
Table 2.4 Classification of Instructions (cont)
Classificati on Branch Type s 9 Operatio n Code BF BT BRA BRAF BSR BSRF JMP JSR RTS System control 15 CLRT CLRMAC CLRS LDC LDS LDTLB NOP PREF RTE SETS SETT SLEEP STC STS TRAPA Total: 68 Function Conditional branch, delayed conditional branch (T = 0) Conditional branch, delayed conditional branch (T = 1) Unconditional branch Unconditional branch Branch to subroutine procedure Branch to subroutine procedure Unconditional branch Branch to subroutine procedure Return from subroutine procedure T bit clear MAC register clear Clear S bit Load to control register Load to system register Load PTE to TLB No operation Prefetch data to cache Return from exception handling Set S bit Set T bit Shift to power-down mode Store from control register Store from system register Trap exception handling 188 75 No. of Instructio ns 11
Table 2.5 lists the SH7708 Series instruction code formats.
31
Table 2.5 Instruction Code Format
Item Instruction mnemonic Format OP.Sz SRC,DEST Explanation OP: Operation code Sz: Size SRC: Source DEST: Destination Rm: Source register Rn: Destination register imm: Immediate data disp: Displacement mmmm: Source register nnnn: Destination register 0000: R0 0001: R1 ........... 1111: R15 iiii: Immediate data dddd: Displacement Direction of transfer Memory operand Flag bits in SR Logical AND of each bit Logical OR of each bit Exclusive OR of each bit Logical NOT of each bit n-bit shift Indicates whether privileged mode applies Value when no wait states are inserted The execution cycles listed in the table are minimums. The actual number of cycles may be increased in cases such as the following: 1. When contention occurs between instruction fetches and data access 2. When the destination register of the load instruction (memory register) and the register used by the next instruction are the same T bit Value of T bit after instruction is executed --: No change Note: Scaling (x1, x2, x4) is performed according to the instruction operand size.
Instruction code
MSB LSB
Operation
, (xx) M/Q/T & | ~ <>n
Privileged mode Execution cycles
32
Table 2.6 lists the SH7708 Series data transfer instructions Table 2.6 Data Transfer Instructions
Privileged Mode -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Instruction MOV #imm,Rn
Operation imm Sign extension Rn (disp x 2 + PC) Sign extension Rn (disp x 4 + PC) Rn Rm Rn Rm (Rn) Rm (Rn) Rm (Rn) (Rm) Sign extension Rn (Rm) Sign extension Rn (Rm) Rn Rn-1 Rn, Rm (Rn) Rn-2 Rn, Rm (Rn) Rn-4 Rn, Rm (Rn) (Rm) Sign extension Rn, Rm + 1 Rm (Rm) Sign extension Rn, Rm + 2 Rm
Code 1110nnnniiiiiiii
Cycles 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
T Bit -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
MOV.W
@(disp,PC),Rn
1001nnnndddddddd
MOV.L MOV MOV.B MOV.W MOV.L MOV.B
@(disp,PC),Rn Rm,Rn Rm,@Rn Rm,@Rn Rm,@Rn @Rm,Rn
1101nnnndddddddd 0110nnnnmmmm0011 0010nnnnmmmm0000 0010nnnnmmmm0001 0010nnnnmmmm0010 0110nnnnmmmm0000
MOV.W
@Rm,Rn
0110nnnnmmmm0001
MOV.L MOV.B MOV.W MOV.L MOV.B
@Rm,Rn Rm,@-Rn Rm,@-Rn Rm,@-Rn @Rm+,Rn
0110nnnnmmmm0010 0010nnnnmmmm0100 0010nnnnmmmm0101 0010nnnnmmmm0110 0110nnnnmmmm0100
MOV.W
@Rm+,Rn
0110nnnnmmmm0101
MOV.L MOV.B MOV.W MOV.L MOV.B
@Rm+,Rn R0,@(disp,Rn) R0,@(disp,Rn) Rm,@(disp,Rn) @(disp,Rm),R0
(Rm) Rn,Rm + 4 Rm 0110nnnnmmmm0110 R0 (disp + Rn) R0 (disp x 2 + Rn) Rm (disp x 4 + Rn) (disp + Rm) Sign extension R0 (disp x 2 + Rm) Sign extension R0 (disp x 4 + Rm) Rn Rm (R0 + Rn) Rm (R0 + Rn) 10000000nnnndddd 10000001nnnndddd 0001nnnnmmmmdddd 10000100mmmmdddd
MOV.W
@(disp,Rm),R0
10000101mmmmdddd
MOV.L MOV.B MOV.W
@(disp,Rm),Rn Rm,@(R0,Rn) Rm,@(R0,Rn)
0101nnnnmmmmdddd 0000nnnnmmmm0100 0000nnnnmmmm0101
33
Table 2.6 Data Transfer Instructions (cont)
Privileged Mode -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Instruction MOV.L MOV.B Rm,@(R0,Rn) @(R0,Rm),Rn
Operation Rm (R0 + Rn)
Code 0000nnnnmmmm0110
Cycles 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
T Bit -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
(R0 + Rm) Sign extension 0000nnnnmmmm1100 Rn (R0 + Rm) Sign extension 0000nnnnmmmm1101 Rn (R0 + Rm) Rn 0000nnnnmmmm1110 11000000dddddddd 11000001dddddddd 11000010dddddddd 11000100dddddddd
MOV.W
@(R0,Rm),Rn
MOV.L MOV.B MOV.W MOV.L MOV.B
@(R0,Rm),Rn
R0,@(disp,GBR) R0 (disp + GBR) R0,@(disp,GBR) R0 (disp x2 + GBR) R0,@(disp,GBR) R0 (disp x 4 + GBR) @(disp,GBR),R0 (disp + GBR) Sign extension R0 @(disp,GBR),R0 (disp x 2 + GBR) Sign extension R0 @(disp,GBR),R0 (disp x 4 + GBR) R0 @(disp,PC),R0 Rn disp x 4 + PC R0 T Rn Rm Swap the bottom two bytes Rn
MOV.W
11000101dddddddd
MOV.L MOVA MOVT
11000110dddddddd 11000111dddddddd 0000nnnn00101001 0110nnnnmmmm1000
SWAP.B Rm,Rn
SWAP.W Rm,Rn
Rm Swap two consecutive0110nnnnmmmm1001 words Rn Rm: Middle 32 bits of Rn Rn 0010nnnnmmmm1101
XTRCT
Rm,Rn
34
Table 2.7 lists the SH7708 Series arithmetic instructions. Table 2.7 Arithmetic Instructions
Privileged Mode -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Instruction ADD ADD ADDC Rm,Rn #imm,Rn Rm,Rn
Operation Rn + Rm Rn Rn + imm Rn Rn + Rm + T Rn, Carry T Rn + Rm Rn, Overflow T If R0 = imm, 1 T If Rn = Rm, 1 T If Rn Rm with unsigned data, 1 T
Code 0011nnnnmmmm1100 0111nnnniiiiiiii 0011nnnnmmmm1110
Cycles 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
T Bit -- -- Carry Overflow Comparison result Comparison result Comparison result Comparison result Comparison result Comparison result Comparison result Comparison result Comparison result Calculation result Calculation result 0
ADDV
Rm,Rn
0011nnnnmmmm1111
CMP/EQ
#imm,R0
10001000iiiiiiii
CMP/EQ
Rm,Rn
0011nnnnmmmm0000
CMP/HS
Rm,Rn
0011nnnnmmmm0010
CMP/GE
Rm,Rn
If Rn Rm with signed data,0011nnnnmmmm0011 1T If Rn > Rm with unsigned data, 1 T If Rn > Rm with signed data, 1 T If Rn 0, 1 T If Rn > 0, 1 T If Rn and Rm have an equivalent byte, 1 T Single-step division (Rn/Rm) MSB of Rn Q, MSB of Rm M, M^ Q T 0 M/Q/T 0011nnnnmmmm0110
CMP/HI
Rm,Rn
CMP/GT
Rm,Rn
0011nnnnmmmm0111
CMP/PZ
Rn
0100nnnn00010001
CMP/PL
Rn
0100nnnn00010101
CMP/STR Rm,Rn
0010nnnnmmmm1100
DIV1
Rm,Rn
0011nnnnmmmm0100
DIV0S
Rm,Rn
0010nnnnmmmm0111
DIV0U
0000000000011001
35
Table 2.7 Arithmetic Instructions (cont)
Privileged Mode --
Instruction DMULS.L Rm,Rn
Operation Signed operation of Rn x Rm MACH, MACL 32 x 32 64 bits Unsigned operation of Rn x Rm MACH, MACL 32 x 32 64 bits Rn - 1 Rn, if Rn = 0, 1 T, else 0 T A byte in Rm is signextended Rn A word in Rm is signextended Rn A byte in Rm is zeroextended Rn A word in Rm is zeroextended Rn Signed operation of (Rn) x (Rm) + MAC MAC, Rn + 4 Rn, Rm + 4 Rm 32 x 32 + 64 64 bits Signed operation of (Rn) x (Rm) + MAC MAC, Rn + 2 Rn, Rm + 2 Rm 16 x 16 + 64 64 bits Rn x Rm MACL 32 x 32 32 bits Signed operation of Rn x Rm MAC 16 x 16 32 bits Unsigned operation of Rn x Rm MAC 16 x 16 32 bits
Code 0011nnnnmmmm1101
Cycles 2(-5)*
T Bit --
DMULU.L Rm,Rn
0011nnnnmmmm0101
--
2(-5)*
--
DT
Rn
0100nnnn00010000
-- -- -- -- -- --
1 1 1 1 1 2(-5)*
Comparison result -- -- -- -- --
EXTS.B Rm,Rn
0110nnnnmmmm1110
EXTS.W Rm,Rn
0110nnnnmmmm1111
EXTU.B Rm,Rn
0110nnnnmmmm1100
EXTU.W Rm,Rn
0110nnnnmmmm1101
MAC.L
@Rm+,@Rn+
0000nnnnmmmm1111
MAC.W
@Rm+,@Rn+
0100nnnnmmmm1111
--
2(-5)*
--
MUL.L
Rm,Rn
0000nnnnmmmm0111
-- --
2(-5)* 1(-3)*
-- --
MULS.W Rm,Rn
0010nnnnmmmm1111
MULU.W Rm,Rn
0010nnnnmmmm1110
--
1(-3)*
--
36
Table 2.7 Arithmetic Instructions (cont)
Privileged Mode -- -- -- -- --
Instruction NEG NEGC Rm,Rn Rm,Rn
Operation 0-Rm Rn 0-Rm-T Rn, Borrow T Rn-Rm Rn Rn-Rm-T Rn, Borrow T Rn-Rm Rn, Underflow T
Code 0110nnnnmmmm1011 0110nnnnmmmm1010
Cycles 1 1 1 1 1
T Bit -- Borrow -- Borrow Underflow
SUB SUBC
Rm,Rn Rm,Rn
0011nnnnmmmm1000 0011nnnnmmmm1010
SUBV
Rm,Rn
0011nnnnmmmm1011
Note: The normal number of execution cycles is shown. The value in parentheses is the number of cycles required in case of contention with the preceding or following instruction.
37
Table 2.8 lists the SH7708 Series logic operation instructions. Table 2.8 Logic Operation Instructions
Privileged Mode -- -- -- -- -- -- -- -- -- -- -- -- -- --
Instruction AND AND Rm,Rn #imm,R0
Operation Rn & Rm Rn R0 & imm R0 (R0 + GBR) & imm (R0 + GBR) ~Rm Rn Rn | Rm Rn R0 | imm R0 (R0 + GBR) | imm (R0 + GBR) If (Rn) is 0, 1 T; 1 MSB of (Rn) Rn & Rm; if the result is 0, 1 T R0 & imm; if the result is 0, 1 T (R0 + GBR) & imm; if the result is 0, 1 T Rn ^ Rm Rn R0 ^ imm R0 (R0 + GBR) ^ imm (R0 + GBR)
Code 0010nnnnmmmm1001 11001001iiiiiiii 11001101iiiiiiii
Cycles 1 1 3 1 1 1 3 3 1 1 3 1 1 3
T Bit -- -- -- -- -- -- -- Test result Test result Test result Test result -- -- --
AND.B #imm,@(R0,GBR)
NOT OR OR OR.B
Rm,Rn Rm,Rn #imm,R0 #imm,@(R0,GBR)
0110nnnnmmmm0111 0010nnnnmmmm1011 11001011iiiiiiii 11001111iiiiiiii
TAS.B @Rn
0100nnnn00011011
TST
Rm,Rn
0010nnnnmmmm1000
TST
#imm,R0
11001000iiiiiiii
TST.B #imm,@(R0,GBR)
11001100iiiiiiii
XOR XOR
Rm,Rn #imm,R0
0010nnnnmmmm1010 11001010iiiiiiii 11001110iiiiiiii
XOR.B #imm,@(R0,GBR)
38
Table 2.9 lists the SH7708 Series shift instructions. Table 2.9 Shift Instructions
Privileged Mode -- -- -- -- --
Instruction ROTL ROTR ROTCL ROTCR SHAD Rn Rn Rn Rn Rm,Rn
Operation T Rn MSB LSB Rn T T Rn T T Rn T Rn 0: Rn << Rm Rn Rn < 0: Rn >> Rm [MSB Rn] T Rn 0 MSB Rn T Rn 0: Rn << Rm Rn Rn < 0: Rn >> Rm [0 Rn] T Rn 0 0 Rn T Rn << 2 Rn Rn >> 2 Rn Rn << 8 Rn Rn >> 8 Rn Rn << 16 Rn Rn >> 16 Rn
Code 0100nnnn00000100 0100nnnn00000101 0100nnnn00100100 0100nnnn00100101 0100nnnnmmmm1100
Cycles 1 1 1 1 1
T Bit MSB LSB MSB LSB --
SHAL SHAR SHLD
Rn Rn Rm,Rn
0100nnnn00100000 0100nnnn00100001 0100nnnnmmmm1101
-- -- --
1 1 1
MSB LSB --
SHLL SHLR SHLL2 SHLR2 SHLL8 SHLR8
Rn Rn Rn Rn Rn Rn
0100nnnn00000000 0100nnnn00000001 0100nnnn00001000 0100nnnn00001001 0100nnnn00011000 0100nnnn00011001 0100nnnn00101000 0100nnnn00101001
-- -- -- -- -- -- -- --
1 1 1 1 1 1 1 1
MSB LSB -- -- -- -- -- --
SHLL16 Rn SHLR16 Rn
39
Table 2.10 lists the SH7708 Series branch instructions. Table 2.10Branch Instructions
Privileged Mode --
Instruction BF label
Operation If T = 0, disp x 2 + PC AE PC; if T = 1, nop (where label is disp + PC) Delayed branch, if T = 0, disp x 2 + PC PC; if T = 1, nop Delayed branch, if T = 1, disp x 2 + PC PC; if T = 0, nop If T = 1, disp x 2 + PC PC; if T = 0, nop Delayed branch, disp x 2 + PC PC Delayed branch, Rm + PC PC Delayed branch, PC PR, disp x 2 + PC PC Delayed branch, PC PR, Rm + PC PC Delayed branch, Rm PC Delayed branch, PC PR, Rm PC Delayed branch, PR PC
Code 10001011dddddddd
Cycles 3/1*
T Bit --
BF/S
label
10001111dddddddd
--
2/1*
--
BT
label
10001001dddddddd
--
3/1*
--
BT/S
label
10001101dddddddd
-- -- -- -- -- -- -- --
2/1* 2 2 2 2 2 2 2
-- -- -- -- -- -- -- --
BRA
label
1010dddddddddddd
BRAF
Rm
0000mmmm00100011
BSR
label
1011dddddddddddd
BSRF
Rm
0000mmmm00000011
JMP JSR
@Rm @Rm
0100mmmm00101011 0100mmmm00001011
RTS
0000000000001011
Note: One state when there is no branch.
40
Table 2.11 lists the SH7708 Series system control instructions. Table 2.11System Control Instructions
Privileged Mode -- -- --
Instruction CLRMAC CLRS CLRT LDC LDC LDC LDC LDC LDC LDC LDC LDC LDC LDC LDC LDC Rm,SR Rm,GBR Rm,VBR Rm,SSR Rm,SPC Rm,R0_BANK Rm,R1_BANK Rm,R2_BANK Rm,R3_BANK Rm,R4_BANK Rm,R5_BANK Rm,R6_BANK Rm,R7_BANK
Operation 0 MACH, MACL 0S 0T Rm SR Rm GBR Rm VBR Rm SSR Rm SPC Rm R0_BANK Rm R1_BANK Rm R2_BANK Rm R3_BANK Rm R4_BANK Rm R5_BANK Rm R6_BANK Rm R7_BANK (Rm) SR, Rm + 4 Rm (Rm) GBR, Rm + 4 Rm (Rm) VBR, Rm + 4 Rm (Rm) SSR, Rm + 4 Rm (Rm) SPC, Rm + 4 Rm (Rm) R0_BANK, Rm + 4 Rm (Rm) R1_BANK, Rm + 4 Rm (Rm) R2_BANK, Rm + 4 Rm (Rm) R3_BANK, Rm + 4 Rm
Code 0000000000101000 0000000001001000 0000000000001000 0100mmmm00001110 0100mmmm00011110 0100mmmm00101110 0100mmmm00111110 0100mmmm01001110 0100mmmm10001110 0100mmmm10011110 0100mmmm10101110 0100mmmm10111110 0100mmmm11001110 0100mmmm11011110 0100mmmm11101110 0100mmmm11111110 0100mmmm00000111 0100mmmm00010111 0100mmmm00100111 0100mmmm00110111 0100mmmm01000111 0100mmmm10000111
Cycles 1 1 1 5 1 1 1 1 1 1 1 1 1 1 1 1 7 1 1 1 1 1 1 1 1
T Bit -- -- 0 LSB -- -- -- -- -- -- -- -- -- -- -- -- LSB -- -- -- -- -- -- -- --
--

--
LDC.L @Rm+,SR LDC.L @Rm+,GBR LDC.L @Rm+,VBR LDC.L @Rm+,SSR LDC.L @Rm+,SPC LDC.L @Rm+, R0_BANK LDC.L @Rm+, R1_BANK LDC.L @Rm+, R2_BANK LDC.L @Rm+, R3_BANK

0100mmmm10010111
0100mmmm10100111
0100mmmm10110111
41
Table 2.11System Control Instructions (cont)
Privileged Mode
Instruction LDC.L @Rm+, R4_BANK LDC.L @Rm+, R5_BANK LDC.L @Rm+, R6_BANK LDC.L @Rm+, R7_BANK LDS LDS LDS Rm,MACH Rm,MACL Rm,PR
Operation (Rm) R4_BANK, Rm + 4 Rm (Rm) R5_BANK, Rm + 4 Rm (Rm) R6_BANK, Rm + 4 Rm (Rm) R7_BANK, Rm + 4 Rm Rm MACH Rm MACL Rm PR (Rm) MACH, Rm + 4 Rm (Rm) MACL, Rm + 4 Rm (Rm) PR, Rm + 4 Rm PTEH/PTEL TLB No operation
Code 0100mmmm11000111
Cycles 1 1 1 1 1 1 1 1 1 1 1 1 1 4 1 1 4* 1 1 1 1 1 1 1 1 1
T Bit -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1 -- -- -- -- -- -- -- -- -- --

-- -- -- -- -- --
0100mmmm11010111
0100mmmm11100111
0100mmmm11110111
0100mmmm00001010 0100mmmm00011010 0100mmmm00101010 0100mmmm00000110 0100mmmm00010110 0100mmmm00100110 0000000000111000 0000000000001001 0000mmmm10000011 0000000000101011
LDS.L @Rm+,MACH LDS.L @Rm+,MACL LDS.L @Rm+,PR LDTLB NOP PREF RTE @Rm
--
(Rm) cache Delayed branch, SSR/SPC SR/PC 1S 1T Sleep
--
-- --
SETS SETT SLEEP STC STC STC STC STC STC STC STC STC SR,Rn GBR,Rn VBR,Rn SSR,Rn SPC,Rn R0_BANK,Rn R1_BANK,Rn R2_BANK,Rn R3_BANK,Rn
0000000001011000 0000000000011000 0000000000011011 0000nnnn00000010 0000nnnn00010010 0000nnnn00100010 0000nnnn00110010 0000nnnn01000010 0000nnnn10000010 0000nnnn10010010 0000nnnn10100010 0000nnnn10110010

--
SR Rn GBR Rn VBR Rn SSR Rn SPC Rn R0_BANK Rn R1_BANK Rn R2_BANK Rn R3_BANK Rn

Note: The number of cycles until the sleep state is entered.
42
Table 2.11System Control Instructions (cont)
Privileged Mode
Instruction STC STC STC STC R4_BANK,Rn R5_BANK,Rn R6_BANK,Rn R7_BANK,Rn
Operation R4_BANK Rn R5_BANK Rn R6_BANK Rn R7_BANK Rn Rn-4 Rn, SR (Rn) Rn-4 Rn, GBR (Rn) Rn-4 Rn, VBR (Rn) Rn-4 Rn, SSR (Rn) Rn-4 Rn, SPC (Rn) Rn-4 Rn, R0_BANK (Rn) Rn-4 Rn, R1_BANK (Rn) Rn-4 Rn, R2_BANK (Rn) Rn-4 Rn, R3_BANK (Rn) Rn-4 Rn, R4_BANK (Rn) Rn-4 Rn, R5_BANK (Rn) Rn-4 Rn, R6_BANK (Rn) Rn-4 Rn, R7_BANK (Rn) MACH Rn MACL Rn PR Rn Rn-4 Rn, MACH (Rn) Rn-4 Rn, MACL (Rn) Rn-4 Rn, PR (Rn) PC SPC, SR SSR, imm TRA
Code 0000nnnn11000010 0000nnnn11010010 0000nnnn11100010 0000nnnn11110010 0100nnnn00000011 0100nnnn00010011 0100nnnn00100011 0100nnnn00110011 0100nnnn01000011 0100nnnn10000011
Cycles 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 1 1 1 1 1 1 6
T Bit -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --

--
STC.L SR,@-Rn STC.L GBR,@-Rn STC.L VBR,@-Rn STC.L SSR,@-Rn STC.L SPC,@-Rn STC.L R0_BANK, @-Rn STC.L R1_BANK, @-Rn STC.L R2_BANK, @-Rn STC.L R3_BANK, @-Rn STC.L R4_BANK, @-Rn STC.L R5_BANK, @-Rn STC.L R6_BANK, @-Rn STC.L R7_BANK, @-Rn STS STS STS MACH,Rn MACL,Rn PR,Rn

-- -- -- -- -- -- --
0100nnnn10010011
0100nnnn10100011
0100nnnn10110011
0100nnnn11000011
0100nnnn11010011
0100nnnn11100011
0100nnnn11110011
0000nnnn00001010 0000nnnn00011010 0000nnnn00101010 0100nnnn00000010 0100nnnn00010010 0100nnnn00100010 11000011iiiiiiii
STS.L MACH,@-Rn STS.L MACL,@-Rn STS.L PR,@-Rn TRAPA #imm
43
Notes: 1. The table shows the minimum number of execution cycles. The actual number of instruction execution cycles will increase in cases such as the following: * When there is contention between an instruction fetch and data access * When the destination register in a load (memory-to-register) instruction is also used by the next instruction 2. With the addressing modes using displacement (disp) listed below, the assembler descriptions in this manual show the value before scaling (x1, x2, or x4) is performed. This is done to clarify the operation of the chip. For the actual assembler descriptions, refer to the individual assembler notation rules. @ (disp:4, Rn) ; Register-indirect with displacement @ (disp:8, Rn) ; GBR-indirect with displacement @ (disp:8, PC) ; PC-relative with displacement disp:8, disp:12 ; PC-relative
44
2.4.2
Instruction Code Map
Table 2.12 shows the instruction code map. Table 2.12 Instruction Code Map
Instruction Code MSB 0000 Rn 0000 Rn Fx Fx LSB 0000 0001 SR,Rn SPC,Rn R0_BANK,Rn STC R4_BANK,Rn STC Rm @Rm Rm,@(R0,Rn) MOV.W SETT SETS DIV0U Rm,@(R0,Rn) MOV.L CLRMAC Rm,@(R0,Rn) MUL.L LDTLB Rm,Rn R1_BANK,Rn STC R5_BANK,Rn STC BRAF R2_BANK,Rn STC R6_BANK,Rn STC Rm R3_BANK,Rn R7_BANK,Rn STC GBR,Rn STC VBR,Rn STC SSR,Rn Fx: 0000 MD: 00 Fx: 0001 MD: 01 Fx: 0010 MD: 10 Fx: 0011 to 1111 MD: 11
0000 Rn 00MD 0010 STC 0000 Rn 01MD 0010 STC 0000 Rn 10MD 0010 STC 0000 Rn 11MD 0010 STC 0000 Rm 00MD 0011 BSRF 0000 Rm 10MD 0011 PREF 0000 Rn Rm 01MD MOV.B
0000 0000 00MD 1000 CLRT 0000 0000 01MD 1000 CLRS 0000 0000 0000 0000 0000 0000 0000 Rn 0000 Rn 0000 Rn 0000 Rn 0000 Rn 0001 Rn 0010 Rn 0010 Rn 0010 Rn 0010 Rn 0011 Rn 0011 Rn 0011 Rn 0011 Rn Fx Fx Fx Fx Fx Fx Fx 1001 NOP 1010 1011 RTS 1000 1001 1010 STS 1011 MACH,Rn
SLEEP
RTE
MOVT STS MACL,Rn STS
Rn PR,Rn
Rm 11MD MOV.B Rm disp MOV.L
@(R0,Rm),Rn MOV.W Rm,@(disp:4,Rn) Rm,@Rn Rm,@-Rn Rm,Rn MOV.W MOV.W AND XTRCT
@(R0,Rm),Rn MOV.L
@(R0,Rm),Rn MAC.L
@Rm+,@Rn+
Rm 00MD MOV.B Rm 01MD MOV.B Rm 10MD TST
Rm,@Rn Rm,@-Rn Rm,Rn Rm,Rn
MOV.L MOV.L XOR
Rm,@Rn Rm,@-Rn Rm,Rn DIV0S OR Rm,Rn Rm,Rn
Rm 11MD CMP/STR Rm,Rn Rm 00MD CMP/EQ Rm,Rn Rm 01MD DIV1 Rm 10MD SUB Rm 11MD ADD Rm,Rn Rm,Rn Rm,Rn
MULU.W Rm,Rn CMP/HS Rm,Rn
MULSW Rm,Rn CMP/GE Rm,Rn CMP/GT Rm,Rn SUBV ADDV Rm,Rn Rm,Rn
DMULU.L Rm,Rn
CMP/HI SUBC
Rm,Rn Rm,Rn Rm,Rn
DMULS.L Rm,Rn
ADDC
45
Table 2.12 Instruction Code Map (cont)
Instruction Code MSB 0100 Rn 0100 Rn 0100 Rn Fx Fx Fx LSB 0000 SHLL 0001 SHLR 0010 STS.L Fx: 0000 MD: 00 Rn Rn MACH,@-Rn SR,@-Rn SPC,@-Rn
R0_BANK,@-Rn R4_BANK,@-Rn
Fx: 0001 MD: 01 DT Rn SHAL SHAR STS.L STC.L
Fx: 0010 MD: 10 Rn Rn PR,@-Rn VBR,@-Rn
Fx: 0011 to 1111 MD: 11
CMP/PZ Rn STS.L STC.L MACL,@-Rn GBR,@-Rn
0100 Rn 00MD 0011 STC.L 0100 Rn 01MD 0011 STC.L 0100 Rn 10MD 0011 STC.L 0100 Rn 11MD 0011 STC.L 0100 Rn 0100 Rn 0100 Rm Fx Fx Fx 0100 ROTL 0101 ROTR 0110 LDS.L
STC.L
SSR,@-Rn
STC.L STC.L
R1_BANK,@-Rn R5_BANK,@-Rn
STC.L STC.L ROTCL
R2_BANK,@-Rn R6_BANK,@-Rn
STC.L STC.L
R3_BANK,@-Rn R7_BANK,@-Rn
Rn Rn CMP/PL Rn @Rm+,MACL @Rm+,GBR
Rn Rn @Rm+,PR @Rm+,VBR LDC.L @Rm+,SSR
ROTCR LDS.L LDC.L
@Rm+,MACH LDS.L @Rm+,SR @Rm+,SPC
@Rm+,R0_BANK LDC.L @Rm+,R4_BANK LDC.L
0100 Rm 00MD 0111 LDC.L 0100 Rm 01MD 0111 LDC.L 0100 Rm 10MD 0111 LDC.L 0100 Rm 11MD 0111 LDC.L 0100 Rn 0100 Rn 0100 Rm 0100 Rm/ Rn 0100 Rn 0100 Rn Fx Fx Fx Fx 1000 SHLL2 1001 SHLR2 1010 LDS 1011 JSR
LDC.L
@Rm+,R1_BANK LDC.L @Rm+,R5_BANK LDC.L
@Rm+,R2_BANK LDC.L @Rm+,R6_BANK LDC.L
@Rm+,R3_BANK @Rm+,R7_BANK
Rn Rn Rm,MACH @Rm
SHLL8 SHLR8 LDS TAS.B
Rn Rn Rm,MACL @Rn
SHLL16 Rn SHLR16 Rn LDS JMP Rm,PR @Rm
Rm Rm
1100 1101 Rm,SR Rm,SPC Rm,R0_BANK LDC Rm,R4_BANK LDC LDC Rm,GBR
SHAD SHLD
Rm,Rn Rm,Rn LDC Rm,VBR LDC Rm,SSR
0100 Rm 00MD 1110 LDC 0100 Rm 01MD 1110 LDC 0100 Rm 10MD 1110 LDC 0100 Rm 11MD 1110 LDC 0100 Rn 0101 Rn 0110 Rn 0110 Rn 0110 Rn 0110 Rn 0111 Rn Rm Rm 1111 disp
Rm,R1_BANK LDC Rm,R5_BANK LDC
Rm,R2_BANK LDC Rm,R6_BANK LDC
Rm,R3_BANK Rm,R7_BANK
MAC.W @Rm+,@Rn+ MOV.L @Rm,Rn @Rm+,Rn MOV.W @Rm,Rn MOV.W @Rm+,Rn SWAP.W Rm,Rn EXTU.W Rm,Rn ADD @(disp:4,Rm),Rn MOV.L MOV.L NEGC @Rm,Rn @Rm+,Rn Rm,Rn MOV NOT NEG Rm,Rn Rm,Rn Rm,Rn
Rm 00MD MOV.B Rm 01MD MOV.B
Rm 10MD SWAP.B Rm,Rn Rm 11MD EXTU.B Rm,Rn imm
EXTS.B Rm,Rn #imm:8,Rn
EXTS.W Rm,Rn
46
Table 2.12 Instruction Code Map (cont)
Instruction Code MSB 1000 00MD Rn LSB Fx: 0000 MD: 00 Fx: 0001 MD: 01 MOV.W R0,@(disp:4,Rn) MOV.W @(disp:4,Rm),R0 BT BT/S MOV.W @(DISP:8,PC),RN BRA BSR MOV.W R0,@(disp:8,GBR) MOV.W @(disp:8,GBR),R0 AND #imm:8,R0 label:12 label:12 MOV.L R0,@(disp:8,GBR) MOV.L @(disp:8,GBR),R0 XOR #imm:8,R0 TRAPA #imm:8 label:8 label:8 BF BF/S label:8 label:8 Fx: 0010 MD: 10 Fx: 0011 to 1111 MD: 11
disp MOV.B R0,@(disp:4,Rn) disp MOV.B @(disp:4,Rm),R0
1000 01MD Rm
1000 10MD imm/disp CMP/EQ #imm:8,R0 1000 11MD imm/disp 1001 Rn 1010 1011 disp disp disp
1100 00MD imm/disp MOV.B R0,@(disp:8,GBR) 1100 01MD disp MOV.B @(disp:8,GBR),R0 TST #imm:8,R0
MOVA @(disp:8,PC),R0 OR #imm:8,R0
1100 10MD 1100 11MD
imm imm
TST.B #imm:8,@(R0,GBR) MOV.L MOV
AND.B #imm:8,@(R0,GBR)
XOR.B #imm:8,@(R0,GBR)
OR.B #imm:8,@(R0,GBR)
1101 Rn 1110 Rn 1111 Note:
disp imm
@(disp:8,PC),Rn #imm:8,Rn
************ See the SH-3/SH-3E/SH3-DSP Programming Manual for details.
47
2.5
2.5.1
Processor States and Processor Modes
Processor States
The SH7708 Series has five processor states: the reset state, exception-handling state, bus-released state, program execution state, and power-down state. Reset State: In this state the CPU is reset. The reset state is entered when the RESET pin goes low. The CPU enters the power-on reset state if the BREQ pin is high, or the manual reset state if the BREQ pin is low. See section 4, Exception Handling, for more information on resets. In the power-on reset state, the internal states of the CPU and the on-chip supporting module registers are initialized. In the manual reset state, the internal states of the CPU and registers of onchip supporting modules other than the bus state controller (BSC) are initialized. Since the BSC is not initialized in the manual reset state, refreshing operations continue. Refer to the register configurations in the relevant sections for further details. Exception-Handling State: This is a transient state during which the CPU's processor state flow is altered by a reset, general exception, or interrupt exception handling. In the case of a reset, the CPU branches to address H'A0000000 and starts executing the user-coded exception handling program. In the case of a general exception or interrupt, the program counter (PC) contents are saved in the saved program counter (SPC) and the status register (SR) contents are saved in the saved status register (SSR). The CPU branches to the start address of the user-coded exception service routine found from the sum of the contents of the vector base address and the vector offset. See section 4, Exception Processing, for more information on resets, general exceptions, and interrupts. Program Execution State: In this state the CPU executes program instructions in sequence. Power-Down State: In the power-down state, CPU operation halts and power consumption is reduced. The power-down state is entered by means of the SLEEP instruction or the CA pin*. There are three modes in the power-down state: sleep mode, standby mode and hardware standby mode. See section 8, Power-Down Modes, for more information. Note:SH7708S,SH7708R only Bus-Released State: In this state the CPU has released the bus to a device that requested it. Transitions between the states are shown in figure 2.8.
48
From any state except hardware standby mode when RESET = 0 and BREQ = 1
From any state except hardware standby mode when RESET = 0 and BREQ = 0
Power-on reset state
RESET = 0, BREQ = 1
Manual reset state Reset state RESET = 1, BREQ = 0
RESET = 1, BREQ = 1
Exception-handling state
sr eq u t es
Interrupt
Bu
B
r us
eq
u
cl est
ea
ran
ce
Bus-released state
Bu cle s requ ara nce est Bus req Program execution state ues t
Exception interrupt
End of exception transition processing Interrupt
Bus request
Bus request clearance
SLEEP instruction with STBY bit cleared
SLEEP instruction with STBY bit set
Sleep mode Hardware standby mode*
Standby mode
CA = 1, RESET = 0, BREQ = 1
Power-down state
Note: Driving the CA pin low in any state will cause a transition to hardware standby mode (SH7708S,SH7708R only).
Figure 2.8 2.5.2 Processor Modes
Processor State Transitions
There are two processor modes: privileged mode and user mode. The processor mode is determined by the processor mode bit (MD) in the status register (SR). User mode is selected when the MD bit is 0, and privileged mode when the MD bit is 1. When the reset state or exception state is entered, the MD bit is set to 1. When exception handling ends, the MD bit is cleared to 0 and user mode is entered. There are certain registers and bits which can only be accessed in privileged mode.
49
50
Section 3 Memory Management Unit (MMU)
3.1
3.1.1
Overview
Features
The SH7708 Series has an on-chip memory management unit (MMU) that implements address translation. The SH7708 Series features a resident translation lookaside buffer (TLB) that caches information for user-created address translation tables located in external memory. It enables highspeed translation of virtual addresses into physical addresses. Address translation uses the paging system and supports two page sizes (1 kbyte and 4 kbytes). The access right to virtual address space can be set for privileged and user modes to provide memory protection. 3.1.2 Role of MMU
The MMU is a feature designed to make efficient use of physical memory. As shown in figure 3.1, if a process is smaller in size than the physical memory, the entire process can be mapped onto physical memory. However, if the process increases in size to the extent that it no longer fits into physical memory, it becomes necessary to partition the process and to map those parts requiring execution onto memory as occasion demands ((1)). Having the process itself consider this mapping onto physical memory would impose a large burden on the process. To lighten this burden, the idea of virtual memory was born as a means of performing en bloc mapping onto physical memory ((2)). In a virtual memory system, substantially more virtual memory than physical memory is provided, and the process is mapped onto this virtual memory. Thus a process only has to consider operation in virtual memory. Mapping from virtual memory to physical memory is handled by the MMU. The MMU is normally controlled by the operating system, switching physical memory to allow the virtual memory required by a process to be mapped onto physical memory in a smooth fashion. Switching of physical memory is carried out via secondary storage, etc. The virtual memory system that came into being in this way is particularly effective in a timesharing system (TSS) in which a number of processes are running simultaneously ((3)). If processes running in a TSS had to take mapping onto virtual memory into consideration while running, it would not be possible to increase efficiency. Virtual memory is thus used to reduce this load on the individual processes and so improve efficiency ((4)). In the virtual memory system, virtual memory is allocated to each process. The task of the MMU is to perform efficient mapping of these virtual memory areas onto physical memory. It also has a memory protection feature that prevents one process from inadvertently accessing another process's physical memory. When address translation from virtual memory to physical memory is performed using the MMU, it may happen that the relevant translation information is not recorded in the MMU, with the result that one process may inadvertently access the virtual memory allocated to another process. In
51
this case, the MMU will generate an exception, change the physical memory mapping, and record the new address translation information. Although the functions of the MMU could also be implemented by software alone, the need for translation to be performed by software each time a process accesses physical memory would result in poor efficiency. For this reason, a buffer for address translation (translation lookaside buffer: TLB) is provided in hardware to hold frequently used address translation information. The TLB can be described as a cache for storing address translation information. Unlike cache memory, however, if address translation fails--that is, if an exception is generated--switching of address translation information is normally performed by software. This makes it possible for memory management to be performed flexibly by software. The MMU has two methods of mapping from virtual memory to physical memory: a paging method using fixed-length address translation, and a segment method using variable-length address translation. With the paging method, the unit of translation is a fixed-size address space (usually of 1 to 64 kbytes) called a page. In the following text, SH7708 Series address space in virtual memory is referred to as virtual address space, and address space in physical memory as physical memory space.
Virtual memory Process 1 Physical memory Process 1 Process 1 Physical memory MMU Physical memory
(1)
(2)
Process 1 Physical memory Process 2
Process 1
Virtual memory MMU Physical memory
Process 2
Process 3
Process 3
(3)
(4)
Figure 3.1
52
MMU Functions
3.1.3
SH7708 Series MMU
Virtual Address Map: The SH7708 Series uses 32-bit virtual addresses to access a 4-Gbyte virtual address space that is divided into several areas. Address space mapping is shown in figure 3.2. In privileged mode, there are five areas, P0-P4. The P0 and P3 areas are mapped onto physical address space in page units, in accordance with address translation table information. Addresses H'7F000000-H'7FFFFFFF in the P0 area can be used as on-chip RAM space by making a setting in the cache control register (CCR) (see section 5, Cache). In this case, mapping by means of the address translation table is not performed for the on-chip RAM space. Write-back or write-through can be selected for write access by means of a CCR setting. Mapping of the P1 area is fixed to physical address space (H'00000000 to H'1FFFFFFF). In the P1 area, setting a virtual address MSBs (bit 31) to 0 generates the corresponding physical address. P1 area access can be cached, and the cache control register (CCR) is set to indicate whether to cache or not. Write access is processed as write-through (SH7708). A CCR setting can be made to select write-back or write-through. Mapping of the P2 area is fixed to physical address space (H'00000000 to H'1FFFFFFF). In the P2 area, setting the top three virtual address bits (bits 31, 30, and 29) to 0 generates the corresponding physical address. P2 area access cannot be cached. The P1 and P2 areas are not mapped by the address translation table, so the TLB is not used and no exceptions like TLB misses occur. Initialization of MMU-related registers, exception processing handling, and the like are located in the P1 and P2 areas. Because the P1 area is cached, handlers that require high-speed processing are placed there. The P4 area is used for mapping on-chip control register addresses. In user mode, the 2 Gbytes of virtual address space from H'00000000 to H'7FFFFFFF (area U0) can be accessed. U0 is mapped onto physical address space in page units. As with the P0 area, addresses H'7000000-H'7FFFFFFF can be used as on-chip RAM space by making a setting in the cache control register (CCR). In this case, mapping by means of the address translation table is not performed for the on-chip RAM space. The 2 Gbytes of virtual address space from H'80000000 to H'FFFFFFFF cannot be accessed in user mode. Attempting to do so creates an address error. Write-back or write-through mode can be selected for write accesses by means of a CCR setting.
53
H'00000000
H'00000000
2 Gbyte virtual space, cacheable (write-back/write-through)
Area P0
2 Gbyte virtual space, cacheable (write-back/write-through)
Area U0
H'7F000000 H'80000000
On-chip RAM space 0.5 Gbyte fixed physical space, cacheable (write-through: SH7708) (write-back/write-through: SH7708S, SH7708R) 0.5 Gbyte fixed physical space, non-cacheable 0.5 Gbyte virtual space, cacheable (write-back/write-through) 0.5 Gbyte control space, non-cacheable
H'7F000000 H'80000000
On-chip RAM space
Area P1
H'A0000000
Area P2
Address error
H'C0000000
Area P3
H'E0000000 Area P4 H'FFFFFFFF Privileged mode User mode
H'FFFFFFFF
Figure 3.2
Virtual Address Space Mapping
54
Physical Address Space: The SH7708 Series supports a 32-bit physical address space, but the upper 3 bits are actually ignored and treated as a shadow. See section 10, Bus State Controller, for details. Single Address Translation: When the MMU is enabled, the virtual address space is divided into units called pages. Physical addresses are translated in page units. Address translation tables in external memory hold information such as the physical address that corresponds to the virtual address and memory protection codes. With the TLB, the contents of address translation tables in external memory are cached to speed up address translation. When an access to areas P1 or P2 occurs, there is no TLB access and the physical address is defined uniquely by the hardware. If it belongs to areas P0, P3 or U0, the TLB is searched by virtual address and, if that virtual address is registered in the TLB, the access hits the TLB. The corresponding physical address and the page control information are read from the TLB and the physical address is determined. If the virtual address is not registered in the TLB, a TLB miss exception occurs and processing will shift to the TLB miss handler. In the TLB miss handler, the TLB address translation table in external memory is searched and the corresponding physical address and the page control information are registered in the TLB. After returning from the handler, the instruction that caused the TLB miss is re-executed. When the MMU is enabled, address translation information that results in a physical address space of H'80000000-H'FFFFFFFF should not be registered in the TLB. When the MMU is disabled, the virtual address is used directly as the physical address. As the SH7708 Series supports a 29-bit address space as the physical address space, the top 3 bits of the physical address are ignored, and constitute a shadow space (see section 10, Bus State Controller (BSC)). For example, addresses H'00001000 in the P0 area, H'80001000 in the P1 area, H'A0001000 in the P2 area, and H'C0001000 in the P3 area are all mapped onto the same physical address. When access to these addresses is performed with the cache enabled, an address with the top 3 bits of the physical address masked to 0 is stored in the cache address array to ensure data congruity. Single Virtual Memory Mode and Multiple Virtual Memory Mode: There are two virtual memory modes: single virtual memory mode and multiple virtual memory mode. In single virtual memory mode, multiple processes run in parallel using the virtual address space exclusively and the physical address corresponding to a given virtual address is specified uniquely. In multiple virtual memory mode, multiple processes run in parallel sharing the virtual address space, so a given virtual address may be translated into different physical addresses depending on the process. Either single or multiple virtual mode is selected according to the value set in the MMU control register. The items used in address comparison are the VPN and ASID. The VPN of the virtual address used to access external memory is compared with the VPN of the TLB entry selected by the index number.
55
Address Space Identifier (ASID): When multiple processes run in parallel sharing the same virtual address space and the processes have unique address translation tables, the virtual space can be multiplexed. The ASID is 8 bits in length and is held in PTEH within the MMU indicating the current process. With ASID, the TLB need not be purged when the process is switched. When multiple processes run in parallel using the virtual address space exclusively, the physical address corresponding to a given virtual address is specified uniquely. For this kind of single virtual memory, the ASID becomes a key to protect memory (see section 3.4.2). 3.1.4 Register Configuration
A register that has an undefined initial value must be initialized by the software. Table 3.1 shows the configuration of the MMU control registers. Table 3.1 Register Configuration
Name Page table entry register high Page table entry register low Translation table base register TLB exception address register MMU control register Abbreviatio n PTEH PTEL TTB TEA MMUCR R/ W R/W R/W R/W R/W R/W Size Longword Longword Longword Longword Longword Initial Value* 1 Undefined Undefined Undefined Undefined *2 Address H'FFFFFFF0 H'FFFFFFF4 H'FFFFFFF8 H'FFFFFFFC H'FFFFFFE0
Notes: 1. Initialized by a power-on reset or manual reset. 2. SV bit: undefined Other bits: 0
56
3.2
Register Description
There are five registers for MMU processing. These are all peripheral module registers, so they are located in address space area P4 and can only be accessed from privileged mode by specifying the address. These registers consist of: 1. The page table entry register high (PTEH) register residing at address H'FFFFFFF0, which consists of a virtual page number (VPN) and ASID. The VPN set is the VPN of the virtual address at which the exception is generated in the case of an MMU exception or address error exception. When the page size is 4 kbytes, the VPN is the upper 20 bits of the virtual address, but in this case the upper 22 bits of the virtual address are set. The VPN can also be modified by software. As the ASID, software sets the number of the currently executing process. The VPN and ASID are recorded in the TLB by the LDTLB instruction. 2. The page table entry register low (PTEL) register residing at address H'FFFFFFF4, and used to store the physical page number and page management information to be recorded in the TLB by the LDTLB instruction. The contents of this register are only modified in response to a software command. 3. The translation table base register (TTB) residing at address H'FFFFFFF8, which points to the base address of the current page table. The hardware does not set any value in TTB automatically. TTB is available to software for general purposes. 4. The TLB exception address register (TEA) register residing at address H'FFFFFFFC, which stores the virtual address corresponding to a TLB or address error exception. This value remains valid until the next exception or interrupt. 5. The MMU control register (MMUCR) residing at address H'FFFFFFF0, which makes the MMU settings described in figure 3.3. Any program that modifies MMUCR should reside in the P1 or P2 area.
57
The MMU registers are shown in figure 3.3.
31 VPN PTEH 31 PPN PTEL 31 TTB TTB 31 Virtual address causing TLB-related or address error exception TEA 31 0 MMUCR 0: Reserved bits (except MMUCR): Always read as 0. Writing is ignored. (MMUCR) :Except bit 3 is read as 0. Bit 3 is don't care. Writing is should be 0. SV: Single virtual memory mode bit. Set to 1 for single virtual memory mode, cleared to 0 for multiple virtual memory mode. RC: A 2-bit random counter, automatically updated by hardware according to the following rules in the event of an MMU exception. When a TLB miss exception occurs, all TLB entry ways corresponding to the virtual address at which the exception occurred are checked, and if all ways are valid, 1 is added to RC; if there is one or more invalid way, they are set by priority from way 0, in the order: way 0, way 1, way 2, way 3. In the event of an MMU exception other than a TLB miss exception, the way which caused the exception is set in RC. TF: TLB flush bit. Write 1 to flush the TLB (clear all valid bits of the TLB to 0). Always reads 0. IX: Index mode bit. When 0, VPN bits 16-12 are used as the TLB index number. When 1, the value obtained by EX-ORing ASID bits 4-0 in PTEH and VPN bits 16-12 are used as the TLB index number. AT: Address translation bit. Enables/disables the MMU. 0: MMU disabled 8 7 6543 2 1 0 SV 00 RC 0 TF IX AT 0 0 10 9 8 7 6 4 321 0 10 0 7 ASID 0
0 V 0 PR SZ C D SH 0
Figure 3.3
MMU Register Contents
58
3.3
3.3.1
TLB Functions
Configuration of the TLB
The TLB caches address translation table information located in external memory. The address translation table stores the physical page number translated from the virtual page number and the control information for the page, which is the unit of address translation. Figure 3.4 shows the overall TLB configuration. The TLB is 4-way set associative with 128 entries. There are 32 entries for each way. Figure 3.5 shows the configuration of virtual addresses and TLB entries.
Way 0-3 Way 0-3
Entry 0 Entry 1
VPN(31-17)
VPN(11-10) ASID(7-0)
V
Entry 0 PPN(31-10) PR(1-0) SZ C D SH Entry 1
Entry 31 Address array
Entry 31 Data array
Figure 3.4
Overall Configuration of the TLB
59
31 VPN
10
9 Offset
0
Virtual address (1-kbyte page) 31 VPN Virtual address (4-kbyte page) (15) (2) (8) (1) (1) (1) (22) PPN (2) (1) (1) PR C D 12 11 Offset 0
VPN (31-17) VPN (11-10) ASID SH SZ V TLB entry
VPN: Virtual page number. Top 22 bits of virtual address for a 1-kbyte page, or top 20 bits of virtual address for a 4-kbyte page. Since VPN bits 16-12 are used as the index number, they are not stored in the TLB entry. ASID: Address space identifier. Indicates the process that can access a virtual page. In single virtual memory mode and user mode, or in multiple virtual memory mode, if the SH bit is 0, the address is compared with the ASID in PTEH when address comparison is performed. SH: Share status bit 0 = Page not shared between processes 1 = Page shared between processes SZ: Page size bit 0 = 1-kbyte page 1 = 4-kbyte page V: Valid bit. Indicates whether entry is valid. 0 = Invalid 1 = Valid Cleared to 0 by a power-on reset. Not affected by a manual reset. PPN: Physical page number. Top 22 bits of physical address. PPN bits 11-10 are not used in the case of a 4-kbyte page. Attention must be paid to the synonym problem in the case of a 1-kbyte page (see section 3.4.4). Set the most significant bit to 0. PR: Protection key field. 2-bit field encoded to define the access rights to the page. 00: Reading only is possible in privileged mode. 01: Reading/writing is possible in privileged mode. 10: Reading only is possible in privileged/user mode. 11: Reading/writing is possible in privileged/user mode. C: Cacheable bit. Indicates whether the page is cacheable. 0: Non-cacheable 1: Cacheable D: Dirty bit. Indicates whether the page has been written to. 0 = Not written to 1 = Written to
Figure 3.5
Virtual Address and TLB Structure
60
3.3.2
TLB Indexing
The TLB uses a 4-way set associative scheme, so entries must be selected by index. VPN bits 16 to 12 are used as the index number regardless of the page size. The index number can be generated in two different ways depending on the setting of the IX bit in MMUCR. 1. When IX = 0, VPN bits 16-12 alone are used as the index number 2. When IX = 1, VPN bits 16-12 are EX-ORed with ASID bits 4-0 to generate a 5-bit index number The second method is used to prevent lowered TLB efficiency that results when multiple processes run simultaneously in the same virtual address space and a specific entry is selected by indexing of each process. Figures 3.6 and 3.7 show the indexing schemes.
Virtual address 31
17 16 12 11
0
PTEH register 31 VPN
10 0 ASID(4-0)
7 ASID
0
Exclusive-OR Index Way 0-3
0
VPN(31-17)
VPN(11-10)
ASID(7-0)
V
PPN(31-10) PR(1-0) SZ C
D SH
31 Address array Data array
Figure 3.6
TLB Indexing (IX = 1)
61
Virtual address 31
17 16 12 11
0
Index Way 0-3
0
VPN(31-17)
VPN(11-10)
ASID(7-0)
V
PPN(31-10) PR(1-0) SZ C
D SH
31 Address array Data array
Figure 3.7 3.3.3 TLB Address Comparison
TLB Indexing (IX = 0)
The results of address comparison determine whether a specific virtual page number is registered in the TLB. The virtual page number of the virtual address that accesses external memory is compared to the virtual page number of the indexed TLB entry. The ASID within the PTEH is compared to the ASID of the indexed TLB entry. All four ways are searched simultaneously. If the compared values match, and the indexed TLB entry is valid (V bit = 1), the hit is registered. It is necessary to have the software ensure that TLB hits do not occur simultaneously in more than one way, as hardware operation is not guaranteed if this happens. For example, if there are two identical TLB entries with the same VPN and a setting is made such that a TLB hit is made only by a process with ASID = H'FF when one is in the shared state (SH = 1) and the other in the nonshared state (SH = 0), then if the ASID in PHE is set to H'FF, there is a possibility of simultaneous TLB hits in both these ways. It is therefore necessary to ensure that this kind of setting is not made by the software. The object compared varies depending on the page management information (SZ, SH) in the TLB entry. It also varies depending on whether the system supports multiple virtual memory or single virtual memory. The page size information determines whether VPN (11-10) is compared. VPN (11-10) is compared for 1 kbyte pages (SZ = 0) but not for 4 kbyte pages (SZ = 1).
62
The sharing information (SH) determines whether the PTEH.ASID and the ASID in the TLB entry are compared. ASIDs are compared when there is no sharing between processes (SH = 0) but not when there is sharing (SH = 1). When single virtual memory is supported (MMUCR.SV = 1) and privileged mode is engaged (SR.MD = 1), all process resources can be accessed. This means that ASIDs are not compared when single virtual memory is supported and privileged mode is engaged. The objects of address comparison are shown in figure 3.8.
SH = 1 or (SR.MD = 1 and MMUCR.SV = 1)? Yes
No
No (4 kbytes) SZ = 0? Yes (1 kbyte) Bits compared: VPN (31-17) VPN (11-10) Bits compared: VPN (31-17) SZ = 0?
No (4 kbytes)
Yes (1 kbyte) Bits compared: VPN (31-17) VPN (11-10) ASID (7-0) Bits compared: VPN (31-17) ASID (7-0)
Figure 3.8
Objects of Address Comparison
63
3.3.4
Page Management Information
In addition to the SH and SZ bits, the page management information of TLB entries also includes D, C, and PR bits. The D bit of a TLB entry indicates whether the page is dirty (i.e., has been written to). If the D bit is 0, an attempt to write to the page results in an initial page write exception. For physical page swapping between secondary memory and main memory, for example, pages are controlled so that a dirty page is paged out of main memory only after that page is written back to secondary memory. To record that there has been a write to a given page in the address translation table in memory, an initial page write exception is used. The C bit in the entry indicates whether the referenced page resides in a cacheable or non-cacheable area of memory. The PR field specifies the access rights for the page in privileged and user modes and is used to protect memory. Attempts at nonpermitted accesses result in TLB protection violation exceptions. Access states designated by the D, C, and PR bits are shown in table 3.2. Table 3.2 Access States Designated by D, C, and PR Bits
Privileged Mode Reading D bit 0 1 C bit 0 1 PR bit 00 Permitted Permitted Permitted (no caching) Permitted (with caching) Permitted Writing Initial page write exception Permitted Permitted (no caching) Permitted (with caching) TLB protection violation exception Permitted Reading Permitted Permitted Permitted (no caching) Permitted (with caching) TLB protection violation exception TLB protection violation exception Permitted User Mode Writing Initial page write exception Permitted Permitted (no caching) Permitted (with caching) TLB protection violation exception TLB protection violation exception TLB protection violation exception Permitted
01
Permitted
10
Permitted
TLB protection violation exception Permitted
11
Permitted
Permitted
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3.4
3.4.1
MMU Functions
MMU Hardware Management
MMU hardware management is of the following two kinds. 1. The MMU decodes the virtual address accessed by a process and performs address translation by controlling the TLB in accordance with the MMUCR settings. 2. In address translation, the MMU receives page management information from the TLB, and determines the MMU exception and whether the cache is to be accessed (using the C bit). For details of the determination method and the hardware processing, see section 3.5, MMU Exceptions. 3.4.2 MMU Software Management
There are three kinds of MMU software management, as follows. 1. MMU register setting. MMUCR setting, in particular, should be performed in areas P1 and P2 for which address translation is not performed. Also, since SV and IX bit changes constitute address translation system changes, in this case, TLB flushing should be performed by simultaneously writing 1 to the TF bit also. Since MMU exceptions are not generated in the MMU disabled state with the AT bit cleared to 0, use in the disabled state must be avoided with software that does not use the MMU. 2. TLB entry recording, deletion, and reading. TLB entry recording can be done in two ways--by using the LDTLB instruction, or by writing directly to the memory-mapped TLB. For TLB entry deletion and reading, the memory allocation TLB can be accessed. See section 3.4.3, MMU Instruction (LDTLB), for details of the LDTLB instruction, and section 3.6, MemoryMapped TLB Configuration, for details of the memory-mapped TLB. 3. MMU exception handling. When an MMU exception is generated, it is handled on the basis of information set from the hardware side. See section 3.5, MMU Exceptions, for details. When single virtual memory mode is used, it is possible to create a state in which physical memory access is enabled in privileged mode only by clearing the share status bit (SH) to 0 to specify recording of all TLB entries. This strengthens inter-process memory protection, and enables special access levels to be created in privileged mode only. Recording a 1-kbyte page TLB entry may result in a synonym problem. See section 3.4.4, Avoiding Synonym Problems.
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3.4.3
MMU
Instruction (LDLTB)
The load TLB instruction (LDTLB) is used to record TLB entries. When the IX bit in MMUCR is 0, the LDTLB instruction changes the TLB entry in the way specified by the RC bit in MMUCR to the value specified by PTEH and PTEL, using VPN bits 16-12 specified in PTEH as the index number. When the IX bit in MMUCR is 1, the EX-OR of VPN bits 16-12 specified in PTEH and ASID bits 4-0 in PTEH are used as the index number. Figure 3.9 shows the case where the IX bit in MMUCR is 0. When an MMU exception occurs, the virtual page number of the virtual address that caused the exception is set in PTEH by hardware. The way is set in the RC bit of MMUCR for each exception according to the rules shown in figure 3.9. Consequently, if the LDTLB instruction is issued after setting only PTEL in the MMU exception handling routine, TLB entry recording is possible. Any TLB entry can be updated by software rewriting of PTEH and the RC bits in MMUCR. As the LDTLB instruction changes address translation information, there is a risk of destroying address translation information if this instruction is issued in the P0, U0, or P3 area. Make sure, therefore, that this instruction is issued in the P1 or P2 area. Also, an instruction associated with an access to the P0, U0, or P3 area (such as the RTE instruction) should be issued at least two instructions after the LDLTB instruction.
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MMUCR 31 0 Index
9
0 SV 0 0 RC 0 TF IX AT Way selection PTEL register 31 10 PPN
PTEH register 31 17 VPN
12
10 VPN
8 0 ASID
0
0 0 V 0 PR SZ C D SH 0
Write Way 0 to 3
Write
0
VPN(31-17)
VPN(11-10)
ASID(7-0)
V
PPN(31-10) PR(1-0) SZ C
D SH
31 Address array Data array
Figure 3.9 3.4.4
Operation of LDTLB Instruction
Avoiding Synonym Problems
When a 1-kbyte page is recorded in a TLB entry, a synonym problem may arise. If a number of virtual addresses are mapped onto a single physical address, the same physical address data will be recorded in a number of cache entries, and it will not be possible to guarantee data congruity. The reason why this problem only occurs when using a 1-kbyte page is explained below with reference to figure 3.10. To achieve high-speed operation of the SH7708 Series cache, an index number is created using virtual address bits 10-4. When a 4-kbyte page is used, virtual address bits 10-4 are included in the offset, and since they are not subject to address translation, they are the same as physical address bits 10-4. In cache-based address comparison and recording in the address array, since the cache tag address is a physical address, physical address bits 31-10 are recorded. When a 1-kbyte page is used, also, a cache index number is created using virtual address bits 10-4. However, in the case of a 1-kbyte page, virtual address bit 10 is subject to address translation and therefore may not be the same as physical address bit 10. Consequently, the physical address is recorded in a different entry from that of the index number indicated by the physical address in the cache address array.
67
For example, assume that, with 1-kbyte page TLB entries, TLB entries for which the following translation has been performed are recorded in two TLBs: Virtual address 1 H'00000000 physical address Virtual address 2 H'00000400 physical address H'00000400 H'00000400
Virtual address 1 is recorded in cache entry H'00, and virtual address 2 in cache entry H'40. Since the two virtual addresses are recorded in different cache entries despite the fact that the physical addresses are the same, memory inconsistency will occur as soon as a write is performed to either virtual address. Therefore, when recording a 1-kbyte TLB entry, if the physical address is the same as a physical address already used in another TLB entry, it should be recorded in such a way that physical address bit 10 is the same.
68
When using a 4-kbyte page Virtual address 31 VPN 12 11 10 Offset 0
Physical address 31 PPN 12 11 10
Virtual address (10-4) 0 Offset Cache address array
Physical address (31-10)
When using a 1-kbyte page Virtual address 31 VPN 10 9 Offset 0
Physical address 31 PPN 10 9
Virtual address (10-4) 0 Offset Cache address array
Physical address (31-10)
Figure 3.10
Synonym Problem
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3.5
MMU Exceptions
There are four MMU exceptions: TLB miss, TLB protection violation, TLB invalid, and initial page write. 3.5.1 TLB Miss Exception
A TLB miss results when the virtual address and the address array of the selected TLB entry are compared and no match is found. TLB miss exception handling includes both hardware and software operations. Hardware Operations: In a TLB miss, the SH7708 Series hardware executes a set of prescribed operations, as follows: 1. The VPN field of the virtual address causing the exception is written to the PTEH register. 2. The virtual address causing the exception is written to the TEA register. 3. Either exception code H'040 for a load access, or H'060 for a store access, is written to the EXPEVT register. 4. The PC value indicating the address of the instruction in which the exception occurred is written to the save program counter (SPC). If the exception occurred in a delay slot, the PC value indicating the address of the related delayed branch instruction is written to the SPC. 5. The contents of the status register (SR) at the time of the exception are written to the save status register (SSR). 6. The mode (MD) bit in SR is set to 1 to place the SH7708 Series in privileged mode. 7. The block (BL) bit in SR is set to 1 to mask any further exception requests. 8. The register bank (RB) bit in SR is set to 1. 9. The RC field in the MMU control register (MMUCR) is incremented by 1 when all entries indexed are valid. When some entries indexed are invalid, the smallest way number of them is set in RC. 10.Execution branches to the address obtained by adding the value of the VBR contents and H'00000400 to invoke the user-written TLB miss exception handler. Software (TLB Miss Handler) Operations: The software searches the page tables in external memory and allocates the required page table entry. Upon retrieving the required page table entry, the software must execute the following operations: 1. Write the value of the physical page number (PPN) field and the protection key (PR), page size (SZ), cacheable (C), dirty (D), share status (SH), and valid (V) bits of the page table entry recorded in the address translation table in external memory into the PTEL register in the SH7708 Series.
70
2. If using software for way selection for entry replacement, write the desired value to the RC field in MMUCR. 3. Issue the LDTLB instruction to load the contents of PTEH and PTEL into the TLB. 4. Issue the return from exception handler (RTE) instruction to terminate the handler routine and return to the instruction stream. The RTE instruction should be issued at least two instructions after the LDTLB instruction. 3.5.2 TLB Protection Violation Exception
A TLB protection violation exception results when the virtual address and the address array of the selected TLB entry are compared and a valid entry is found to match, but the type of access is not permitted by the access rights specified in the PR field. TLB protection violation exception handling includes both hardware and software operations. Hardware Operations: In a TLB protection violation exception, the SH7708 Series hardware executes a set of prescribed operations, as follows: 1. The VPN field of the virtual address causing the exception is written to the PTEH register. 2. The virtual address causing the exception is written to the TEA register. 3. Either exception code H'0A0 for a load access, or H'0C0 for a store access, is written to the EXPEVT register. 4. The PC value indicating the address of the instruction in which the exception occurred is written into SPC (if the exception occurred in a delay slot, the PC value indicating the address of the related delayed branch instruction is written into SPC). 5. The contents of SR at the time of the exception are written to SSR. 6. The MD bit in SR is set to 1 to place the SH7708 Series in privileged mode. 7. The BL bit in SR is set to 1 to mask any further exception requests. 8. The register bank (RB) bit in SR is set to 1. 9. The way that generated the exception is set in the RC field in MMUCR. 10.Execution branches to the address obtained by adding the value of the VBR contents and H'00000100 to invoke the TLB protection violation exception handler. Software (TLB Protection Violation Handler) Operations: The software resolves the TLB protection violation and issues the RTE (return from exception handler) instruction to terminate the handler and return to the instruction stream. The RTE instruction should be issued at least two instructions after the LDTLB instruction.
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3.5.3
TLB
Invalid Exception
A TLB invalid exception results when the virtual address is compared to a selected TLB entry address array and a match is found but the entry is not valid (the V bit is 0). TLB invalid exception handling includes both hardware and software operations. Hardware Operations: In a TLB invalid exception, the SH7708 Series hardware executes a set of prescribed operations, as follows: The VPN number of the virtual address causing the exception is written to the PTEH register. The virtual address causing the exception is written to the TEA register. The way number causing the exception is written to RC in MMUCR. Either exception code H'040 for a load access, or H'060 for a store access, is written to the EXPEVT register. 5. The PC value indicating the address of the instruction in which the exception occurred is written to the SPC. If the exception occurred in a delay slot, the PC value indicating the address of the delayed branch instruction is written to the SPC. 6. The contents of SR at the time of the exception are written into SSR. 7. The mode (MD) bit in SR is set to 1 to place the SH7708 Series in privileged mode. 8. The block (BL) bit in SR is set to 1 to mask any further exception requests. 9. The register bank (RB) bit in SR is set to 1. 10.Execution branches to the address obtained by adding the value of the VBR contents and H'00000100, and the TLB protection violation exception handler starts. Software (TLB Invalid Exception Handler) Operations: The software searches the page tables in external memory and assigns the required page table entry. Upon retrieving the required page table entry, the software must execute the following operations: 1. Write the values of the physical page number (PPN) field and the values of the protection key (PR), page size (SZ), cacheable (C), dirty (D), share status (SH), and valid (V) bits of the page table entry recorded in external memory to the PTEL register. 2. If using software for way selection for entry replacement, write the desired value to the RC field in MMUCR. 3. Issue the LDTLB instruction to load the contents of PTEH and PTEL into the TLB. 4. Issue the RTE instruction to terminate the handler and return to the instruction stream. The RTE instruction should be issued after two LDTLB instructions. 1. 2. 3. 4.
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3.5.4
Initial Page Write Exception
An initial page write exception results in a write access when the virtual address and the address array of the selected TLB entry are compared and a valid entry with the appropriate access rights is found to match, but the D (dirty) bit of the entry is 0 (the page has not been written to). Initial page write exception handling includes both hardware and software operations. Hardware Operations: In an initial page write exception, the SH7708 Series hardware executes a set of prescribed operations, as follows: 1. 2. 3. 4. The VPN field of the virtual address causing the exception is written to the PTEH register. The virtual address causing the exception is written to the TEA register. Exception code H'080 is written to the EXPEVT register. The PC value indicating the address of the instruction in which the exception occurred is written to the SPC. If the exception occurred in a delay slot, the PC value indicating the address of the related delayed branch instruction is written to the SPC. 5. The contents of SR at the time of the exception are written to SSR. 6. The MD bit in SR is set to 1 to place the SH7708 Series in privileged mode. 7. The BL bit in SR is set to 1 to mask any further exception requests. 8. The register bank (RB) bit in SR is set to 1. 9. The way that caused the exception is set in the RC field in MMUCR. 10.Execution branches to the address obtained by adding the value of the VBR contents and H'00000100 to invoke the user-written initial page write exception handler. Software (Initial Page Write Handler) Operations: The software must execute the following operations: 1. Retrieve the required page table entry from external memory. 2. Set the D bit of the page table entry in external memory to 1. 3. Write the value of the PPN field and the PR, SZ, C, D, SH, and V bits of the page table entry in external memory to the PTEL register. 4. If using software for way selection for entry replacement, write the desired value to the RC field in MMUCR. 5. Issue the LDTLB instruction to load the contents of PTEH and PTEL into the TLB. 6. Issue the RTE instruction to terminate the handler and return to the instruction stream. The RTE instruction should be issued after two LDTLB instructions. Figure 3.11 shows the flowchart for MMU exceptions.
73
Start SH = 0 and (MMUCR.SV = 0 or SR.MD = 0)? Yes VPNs match? No Yes VPNs and ASIDs match? Yes No TLB invalid exception Privileged mode
No
No
V = 1? TLB miss exception User mode Yes User or privileged?
PR check 00/01 W 10 R/W? R 11 R/W? R No D = 1? Yes TLB protection violation exception Initial page write exception No (noncacheable) Memory access C = 1? W W
PR check 01/11 R/W? R 00/10 W R/W? R
TLB protection violation
Yes (cacheable) Cache access
Figure 3.11
MMU Exception Generation Flowchart
74
3.5.5
Processing Flow in Event of MMU Exception (Same Processing Flow for Address Error)
Figure 3.12 shows the MMU exception signals in instruction fetch mode.
IF
ID
EX ID
MA EX ID
WB MA EX WB MA NOP NOP WB
Handler transition processing
MMU exception handler
IF
ID
EX
MA
WB
: Exception source stage IF ID EX MA WB NOP = Instruction fetch = Instruction decode = Instruction execution = Memory access = Write back = No operation
Figure 3.12
MMU Exception Signals in Instruction Fetch
75
Figure 3.13 shows the MMU exception signals in data access mode.
IF
ID IF
EX ID IF
MA WB EX MA WB ID EX ID MA WB EX ID MA WB EX MA ID EX WB MA WB NOP NOP MMU exception handler IF ID EX MA WB Handler transition processing
: Exception source stage : Stage cancellation for instruction that has begun execution IF ID EX MA WB NOP = Instruction fetch = Instruction decode = Instruction execution = Memory access = Write back = No operation
Figure 3.13
MMU Exception Signals in Data Access
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3.6
Memory-Mapped TLB
In order for TLB operations to be managed by software, TLB contents can be read or written to in privileged mode using the MOV instruction. The TLB is assigned to the P4 area in virtual address space. The TLB address array (VPN, V bit, and ASID) is assigned to H'F2000000-H'F2FFFFFF, and the data array (PPN, PR, SZ, C, D, and SH bits) to H'F3000000-H'F3FFFFFF. The V bit in the address array can also be accessed from the data array. Only longword access is possible for both the address array and the data array. 3.6.1 Address Array
The address array is assigned to H'F2000000 to H'F2FFFFFF. To access an address array, the 32-bit address field (for read/write operations) and 32-bit data field (for write operations) must be specified. The address field specifies information for selecting the entry to be accessed; the data field specifies the VPN, V bit and ASID to be written to the address array (figure 3.14 (1)). In the address field, specify the entry address for selecting the entry (bits 16-12), W for selecting the way (bits 9-8: 00 is way 0, 01 is way 1, 10 is way 2, 11 is way 3) and H'F2 to indicate address array access (bits 31-24). The IX bit in MMUCR indicates whether an EX-OR is taken of the entry address and ASID. When writing, specify bit 7 as the A bit. The A bit indicates whether addresses are compared during writing. When the A bit is 1, the VPNs of the four entries selected by the entry addresses are compared to the VPN to be written into the address array specified in the data field. Writing takes place to the way that has a hit. When a miss occurs, nothing is written to the address array and no operation occurs. The way number specified in bits 9-8 is not used. The item compared is determined by the SZ and SH bits of the entry selected by the entry address, the SV bit in MMUCR and the MD bit in SR, just as in ordinary operations (see section 3.3.3). When the A bit is 0, it is written to the entry selected with the entry address and way number without comparing addresses. When reading, the VPN (31-17, 11-10), V bit, and ASID of the entry specified by the entry address and way number are read in the format of the data field in figure 3.14 without comparing addresses. Zero is read in the data field (16-12). To invalidate a specific entry, specify the entry and write 0 to its V bit. When 1 is specified for the A bit, only the required VPN entry is invalidated.
77
3.6.2
Data Array
The data array is assigned to H'F3000000 to H'F3FFFFFF. To access a data array, the 32-bit address field (for read/write operations), and 32-bit data field (for write operations) must be specified. These are specified in the general register. The address section specifies information for selecting the entry to be accessed; the data section specifies the longword data to be written to the data array (figure 3.14 (2)). In the address section, specify the entry address for selecting the entry (bits 16-12), W for selecting the way (bits 9-8: 00 is way 0, 01 is way 1, 10 is way 2, 11 is way 3), and H'F3 to indicate data array access (bits 31-24). The IX bit in MMUCR indicates whether an EX-OR is taken of the entry address and ASID. Both reading and writing use the longword of the data array specified by the entry address and way number. The access size of the data array is fixed at longword.
78
(1) TLB Address Array Access Read access 31 Address field 31 Data field VPN 11110010 24 23 17 16 12 11 10 9 8 7 6 0
*
*
17 16 0
VPN
**
W
0
*
ASID
*
0
12 11 10 9 8 7 0 VPN 0 V
Write access 31 Address field 31 Data field VPN: V: A: W: VPN 11110010 24 23 17 16 12 11 10 9 8 7 6 VPN 0
*
*
17 16
** *
VPN
W
A
*
ASID
*
0
12 11 10 9 8 7
*
*
V
ASID: Address space identifier Virtual page number : Don't care bit Valid bit Association bit Way (00: Way 0, 01: Way 1, 10: Way 2, 11: Way 3)
*
(2) TLB Data Array Access Read/write access 31 Address field 31 Data field PPN 11110011 24 23 17 16 12 11 10 9 8 7 VPN 0
*
*
**
W
*
32 1
*
0
10 9 8 7 6 5 4
X V X PR SZ C D SH X
PPN: PR: C: SH: VPN: X: W:
V: Valid bit Physical page number SZ: Page size bit Protection key field D: Dirty bit Cacheable bit : Don't care bit Share status bit Virtual page number 0 for read, don't care bit for write Way (00: Way 0, 01: Way 1, 10: Way 2, 11: Way 3)
*
Figure 3.14
Specifying Address and Data for Memory-Mapped TLB Access
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3.6.3
Usage Examples
Invalidating Specific Entries: Specific TLB entries can be invalidated by writing 0 to the entry's V bit. When the A bit is 1, the VPN and ASID specified by the write data is compared to the VPN and ASID within the TLB entry selected by the entry address and data is written to the matching way. If no match is found, there is no operation. R0 specifies the write data and R1 specifies the address.
; R0=H'1547 381C ; MMUCR.IX=0 ; VPN(31-17)=B'0001 0101 0100 011 VPN(11-10)=B'10 ASID=B'0001 1100 R1=H'F201 3080
; corresponding entry association is made from the entry selected by ; the VPN(16-12)=B'1 0011 index, the V bit of the hit way is cleared to ; 0,achieving invalidation. MOV.L R0,@R1
Reading the Data of a Specific Entry: This example reads the data section of a specific TLB entry. The bit order indicated in the data field in figure 3.14 (2) is read. R0 specifies the address and the data section of a selected entry is read to R1.
; R0=H'F300 4300 ; MOV.L @R0,R1 VPN(16-12)=B'00100 Way 3
3.7
Usage Note
Instructions that manipulate the MD or BL bit in register SR (the LDC Rm, SR instruction, LDC @Rm+, SR instruction, and RTE instruction) and the following instruction, or the LDTLB instruction, should be used with the TLB disabled or in a fixed physical address space (the P1 or P2 space).
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Section 4 Exception Handling
4.1
4.1.1
Overview
Features
Exceptions are deviations from normal program execution that require special handling. The processor responds to an exception by aborting execution of the current instruction (execution is allowed to continue to completion in all interrupt requests) and passing control from the instruction stream to the appropriate user-written exception handling routine. Here, all exceptions other than resets and interrupts will be called general exceptions. There are thus three types of exceptions: resets, general exceptions, and interrupts. 4.1.2 Register Configuration
A register with an undefined initial value should be initialized by software. Table 4.1 lists the registers used for exception handling. Table 4.1 Register Configuration
Register Abbr. R/W Size R/W R/W R/W Longword Longword Longword Initial Value Undefined Address H'FFFFFFD0
TRAPA exception register TRA Exception event register Interrupt event register EXPEVT INTEVT
Power-on reset: H'000 H'FFFFFFD4 Manual reset: H'020 Undefined H'FFFFFFD8
4.2
4.2.1
Exception Handling Function
Exception Handling Flow
Usually the contents of the program counter (PC) and status register (SR) are saved in the saved program counter (SPC) and saved status register (SSR), respectively, and execution of the exception handler is invoked from a vector address. The return from exception handler (RTE) instruction is issued by the exception handler routine at the completion of the routine, restoring the contents of the PC and SR to return to the processor status at the point of interruption and the address where the exception occurred.
81
A basic exception processing sequence consists of the following operations: * * * * * The contents of the PC and SR are saved in the SPC and SSR, respectively. The block (BL) bit in SR is set to 1, masking any subsequent exceptions. The mode (MD) bit in SR is set to 1 to place the SH7708 Series in privileged mode. The register bank (RB) bit in SR is set to 1. An encoded value identifying the exception event is written to bits 11-0 of the exception event (EXPEVT) or interrupt event (INTEVT) register. * Instruction execution jumps to the designated exception processing vector address to invoke the handler routine. 4.2.2 Exception Handling Vector Addresses
The reset vector address is fixed at H'A0000000. The other three events are assigned offsets from the vector base address by software. Translation lookaside buffer (TLB) miss exceptions have an offset from the vector base address of H'00000400. The vector address offset for general exception events other than TLB miss exceptions is H'00000100. The interrupt vector address offset is H'00000600. The vector base address is loaded into the vector base register (VBR) by software. The vector base address should reside in P1 or P2 fixed physical address space. Figure 4.1 shows the relationship between the vector base address, the vector offset, and the vector table.
VBR
+ Vector offset
H'A000 0000
Vector table
Figure 4.1
Vector Table
In table 4.2, exceptions and their vector addresses are listed by exception type, instruction completion status, relative acceptance priority, relative order of occurrence within an instruction execution sequence and vector address for exceptions and their vector addresses.
82
Table 4.2 Vectored Exception Events
Exception Current Exceptio Vector Type Instructio Exception Event Priority*n Order Address 1 n Reset Aborted Power-on Manual reset General exception events Aborted and retried 1 1 -- -- 1 2 3 4 Vector Offset
H'A00000000 -- H'A00000000 -- -- -- -- -- H'00000100 H'00000400 H'00000100 H'00000100
Address error 2 (instruction access) TLB miss (instruction 2 access) TLB invalid 2 (instruction access) TLB protection 2 violation (instruction access) Reserved instruction 2 code exception Illegal slot 2 instruction exception Address error (data access) TLB miss (data access) TLB invalid (data access) TLB protection violation (data access) Initial page write 2 2 2 2
5 5 6 7 8 9
-- -- -- -- -- --
H'00000100 H'00000100 H'00000100 H'00000400 H'00000100 H'00000100
2
10 5 n*2
-- -- --
H'00000100 H'00000100 H'00000100
Completed
Unconditional trap 2 (TRAPA instruction) User breakpoint trap 2
83
Table 4.2 Vectored Exception Events (cont)
Exception Current Exceptio Vector Type Instructio Exception Event Priority*n Order Address 1 n General interrupt requests Completed Nonmaskable interrupt External hardware interrupt Peripheral module interrupt 3 4*3 4*3 -- -- -- -- -- -- Vector Offset H'00000600 H'00000600 H'00000600
Notes: 1. Priorities are indicated from high to low, 1 being highest and 4 being lowest. 2. The user defines the break point traps. 1 is a break point before instruction execution and 11 is a break point after instruction execution. For an operand break point, use 11. 3. Use software to specify relative priorities of external hardware interrupts and peripheral module interrupts (see section 6, Interrupt Controller (INTC)).
4.2.3
Acceptance of Exceptions
Processor resets and interrupts are asynchronous events unrelated to the instruction stream. All exception events are prioritized to establish an acceptance order whenever two or more exception events occur simultaneously. The power-on reset and manual reset may not occur simultaneously, so they have the same priority. All general exception events occur in a relative order in the execution sequence of an instruction (i.e., execution order), but are handled at priority level 2 in instruction-stream order (i.e., program order), where an exception detected in a preceding instruction is accepted prior to an exception detected in a subsequent instruction. Three general exception events (reserved instruction code exception, unconditional trap, and illegal slot instruction exception) are detected in the decode stage of different instructions and are mutually exclusive events in the instruction pipeline. They have the same execution priority. Figure 4.2 shows the order of general exception acceptance.
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Pipeline Sequence: Instruction n IF ID EX MA WB
TLB miss (data access) Instruction n + 1 IF ID EX MA WB
TLB miss (instruction access) Instruction n + 2 Detection Order: TLB miss (instruction n+1) IF ID EX MA WB
RIE (reserved instruction exception)
TLB miss (instruction n) and RIE (instruction n + 2) = simultaneous detection Handling Order: TLB miss (instruction n) 1 Re-execution of instruction n Program Order:
TLB miss (instruction n + 1) 2 Re-execution of instruction n + 1
RIE (instruction n + 2)
3
IF ID EX MA WB
= Instruction fetch = Instruction decode = Instruction execution = Memory access = Write back
Figure 4.2
Example of Acceptance Order of General Exceptions
All exceptions other than a reset are detected in the pipeline ID stage, and accepted on instruction boundaries. However, an exception is not accepted between a delayed branch instruction and the delay slot. A re-execution type exception detected in a delay slot is accepted before execution of the delayed branch instruction. A completion type exception detected in a delayed branch instruction or delay slot is accepted after execution of the delayed branch instruction. The delay slot here refers to
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the next instruction after a delayed unconditional branch instruction, or the next instruction when a delayed conditional branch instruction is true. 4.2.4 Exception Codes
Table 4.3 lists the exception codes written to bits 11-0 of the EXPEVT register (for reset or general exceptions) or the INTEVT register (for general interrupt requests) to identify each specific exception event. An additional exception register, the TRAPA (TRA) register, is used to hold the 8-bit immediate data in an unconditional trap (TRAPA instruction). Table 4.3 Exception Codes
Exception Type Reset Exception Event Power-on Manual reset General exception events TLB miss/invalid (load) TLB miss/invalid (store) Initial page write TLB protection violation (load) TLB protection violation (store) Address error (load) Address error (store) Unconditional trap (TRAPA instruction) Reserved instruction code exception Illegal slot instruction exception User break point trap General interrupt requests Nonmaskable interrupt External hardware interrupts: IRL3-IRL0 = 0000 IRL3-IRL0 = 0001 IRL3-IRL0 = 0010 IRL3-IRL0 = 0011 IRL3-IRL0 = 0100 IRL3-IRL0 = 0101 IRL3-IRL0 = 0110 IRL3-IRL0 = 0111 IRL3-IRL0 = 1000 86 H'200 H'220 H'240 H'260 H'280 H'2A0 H'2C0 H'2E0 H'300 Exception Code H'000 H'020 H'040 H'060 H'080 H'0A0 H'0C0 H'0E0 H'100 H'160 H'180 H'1A0 H'1E0 H'1C0
Table 4.3 Exception Codes (cont)
Exception Type General interrupt requests (cont) Exception Event External hardware interrupts (cont): IRL3-IRL0 = 1001 IRL3-IRL0 = 1010 IRL3-IRL0 = 1011 IRL3-IRL0 = 1100 IRL3-IRL0 = 1101 IRL3-IRL0 = 1110 Peripheral module interrupt: TMU0 TMU1 TMU2 TUNI0 TUNI1 TUNI2 TICPI2 RTC ATI PRI CUI SCI ERI RXI TXI TEI WDT REF ITI RCMI ROVI Note: Exception codes H'120, H'140, and H'3E0 are reserved. H'400 H'420 H'440 H'460 H'480 H'4A0 H'4C0 H'4E0 H'500 H'520 H'540 H'560 H'580 H'5A0 H'320 H'340 H'360 H'380 H'3A0 H'3C0 Exception Code
4.2.5
Exception Request Masks
When the BL bit in SR is cleared to 0, exceptions and interrupts are accepted. If a general exception event occurs when the BL bit in SR is 1, the CPU's internal registers are set to their post-reset state, other module registers retain their contents prior to the general exception, and a branch is made to the same address (H'A0000000) as for a reset.
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If a general interrupt occurs when BL = 1, the request is masked (held pending) and not accepted until the BL bit is cleared to 0 by software. For reentrant exception handling, the SPC and SSR must be saved and the BL bit in SR cleared to 0. 4.2.6 Returning from Exception Handling
The RTE instruction is used to return from exception handling. When RTE is executed, the SPC value is set in the PC, and the SSR value in SR, and the return from exception handling is performed by branching to the SPC address. If the SPC and SSR have been saved in external memory, set the BL bit in SR to 1, then restore the SPC and SSR, and issue an RTE instruction.
4.3
Register Description
There are three registers related to exception handling. These are peripheral module registers, and therefore reside in area P4. They can be accessed by specifying the address in privileged mode only. 1. The exception event register (EXPEVT) resides at address H'FFFFFFD4, and contains a 12-bit exception code. The exception code set in EXPEVT is that for a reset or general exception event. The exception code is set automatically by hardware when an exception occurs. EXPEVT can also be modified by software. 2. The interrupt event register (INTEVT) resides at address H'FFFFFFD8, and contains a 12-bit exception code. The exception code set in EXPEVT is that for an interrupt request. The exception code is set automatically by hardware when an exception occurs. INTEVT can also be modified by software. 3. The TRAPA exception register (TRA) resides at address H'FFFFFFD0, and contains 8-bit immediate data (imm) for the TRAPA instruction. TRA is set automatically by hardware when a TRAPA instruction is executed. TRA can also be modified by software. The bit configurations of the EXPEVT, INTEVT, and TRA registers are shown in figure 4.3.
EXPEVT register and INTEVT register 31 0 11 0 0 Exception code TRA register 31 0 0 9 imm 20 00
0: Reserved bits, always read as zero imm: 8-bit immediate data in TRAPA instruction
Figure 4.3
Bit Configurations of EXPEVT, INTEVT, and TRA Registers
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4.4
4.4.1
Exception Handler Operation
Reset
The reset sequence is used to power up or restart the SH7708 Series from the initialization state. The RESET signal is sampled every clock cycle, and in the case of a power-on reset, all processing being executed (excluding the RTC) is suspended, all unfinished events are canceled, and reset processing is executed immediately. In the case of a manual reset, however, processing to retain external memory contents is continued. The BREQ (bus request) signal is used to distinguish between a power-on reset (high-level input) and manual reset (low-level input). The reset sequence consists of the following operations: * * * * The MD bit in SR is set to 1 to place the SH7708 Series in privileged mode. The BL bit in SR is set to 1, masking any subsequent exceptions. The RB bit in SR is set to 1. An encoded value of H'000 in a power-on reset or H'020 in a manual reset is written to bits 11-0 of the EXPEVT register to identify the exception event. * Instruction execution jumps to the user-written exception handler at address H'A0000000. 4.4.2 Interrupts
An interrupt processing request is accepted on completion of the current instruction. The interrupt acceptance sequence consists of the following operations: * * * * * The contents of the PC and SR are saved in SPC and SSR, respectively. The BL bit in SR is set to 1, masking any subsequent exceptions. The MD bit in SR is set to 1 to place the SH7708 Series in privileged mode. The RB bit in SR is set to 1. An encoded value identifying the exception event is written to bits 11-0 of the INTEVT register. * Instruction execution jumps to the vector location designated by the sum of the value of the contents of the vector base register (VBR) and H'00000600 to invoke the exception handler. 4.4.3 General Exceptions
When the SH7708 Series encounters any exception condition other than a reset or interrupt request, it executes the following operations: * The contents of the PC and SR are saved in the SPC and SSR, respectively. * The BL bit in SR is set to 1, masking any subsequent exceptions. * The MD bit in SR is set to 1 to place the SH7708 Series in privileged mode.
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* The RB bit in SR is set to 1. * An encoded value identifying the exception event is written to bits 11-0 of the EXPEVT register. * Instruction execution jumps to the vector location designated by either the sum of the vector base address and offset H'00000400 in the vector table in a TLB miss trap, or by the sum of the vector base address and offset H'00000100 for exceptions other than TLB miss traps, to invoke the exception handler.
4.5
Individual Exception Operations
This section describes the conditions for specific exception handling, and the processor operations. 4.5.1 Resets
* Power-On Reset Conditions: BREQ pin high and RESET low Operations: EXPEVT set to H'000, VBR and SR initialized, branch to PC = H'A0000000. Initialization sets the VBR register to H'0000000. In SR, the MD, RB and BL bits are set to 1 and the IMASK field is set to B'1111. The CPU and on-chip supporting modules are initialized. See the register descriptions in the relevant sections for details. A power-on reset must always be performed when powering on. * Manual Reset Conditions: BREQ pin low and RESET low Operations: EXPEVT set to H'020, VBR and SR initialized, branch to PC = H'A0000000. Initialization sets the VBR register to H'0000000. In SR, the MD, RB, and BL bits are set to 1 and the IMASK field is set to B'1111. The CPU and on-chip supporting modules are initialized. See the register descriptions in the relevant sections for details. Table 4.4 Types of Reset
Conditions for Transition to Reset State Type Power-on reset Manual reset BREQ High Low RESET Low Low CPU Initialized Initialized Internal State On-Chip Supporting Modules (See register configuration in relevant sections)
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4.5.2
General Exceptions
* TLB miss exception Conditions: Comparison of TLB addresses shows no address match Operations: The virtual address (32 bits) that caused the exception is set in TEA and the corresponding virtual page number (22 bits) is set in PTEH (31-10). The ASID of PTEH indicates the ASID at the time the exception occurred. The RC bit in MMUCR is incremented by one for replacement. The PC and SR of the instruction that generated the exception are saved to the SPC and SSR, respectively. If the exception occurred during a read, H'040 is set in EXPEVT; if the exception occurred during a write, H'060 is set in EXPEVT. The BL, MD and RB bits in SR are set to 1 and a branch occurs to PC = VBR + H'0400. To speed up TLB miss processing, the offset differs from other exceptions. * TLB invalid exception Conditions: Comparison of TLB addresses shows address match but V = 0 Operations: The virtual address (32 bits) that caused the exception is set in TEA and the corresponding virtual page number (22 bits) is set in PTEH (31-10). The ASID of PTEH indicates the ASID at the time the exception occurred. The way that generated the exception is set in the RC bits in MMUCR. The PC and SR of the instruction that generated the exception are saved in the SPC and SSR, respectively. If the exception occurred during a read, H'040 is set in EXPEVT; if the exception occurred during a write, H'060 is set in EXPEVT. The BL, MD, and RB bits in SR are set to 1 and a branch occurs to PC = VBR + H'0100. * Initial page write exception Conditions: A hit occurred to the TLB for a store access, but D = 0 This occurs for initial writes to the page registered by the load. Operations: The virtual address (32 bits) that caused the exception is set in TEA and the corresponding virtual page number (22 bits) is set in PTEH (31-10). The ASID of PTEH indicates the ASID at the time the exception occurred. The way that generated the exception is set in MMUCR.RC. The PC and SR of the instruction that generated the exception are saved to the SPC and SSR, respectively. H'080 is set in EXPEVT. The BL, MD, and RB bits in SR are set to 1 and a branch occurs in PC = VBR + H'0100.
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* TLB protection exception Conditions: When a hit access violates the TLB protection information (PR bits) shown below:
PR 00 01 10 11 Privileged mode Only read enabled Read/write enabled Only read enabled Read/write enabled User mode No access No access Only read enabled Read/write enabled
Operations: The virtual address (32 bits) that caused the exception is set in TEA and the corresponding virtual page number (22 bits) is set in PTEH (31-10). The ASID of PTEH indicates the ASID at the time the exception occurred. The way that generated the exception is set in the RC bits in MMUCR. The PC and SR of the instruction that generated the exception are saved to the SPC and SSR, respectively. If the exception occurred during a read, H'0A0 is set in EXPEVT; if the exception occurred during a write, H'0C0 is set in EXPEVT. The BL, MD, and RB bits in SR are set to 1 and a branch occurs to PC = VBR + H'0100. * Address error Conditions: a. Instruction fetch from odd address (4n + 1, 4n + 3) b. Word data accessed from addresses other than word boundaries (4n + 1, 4n + 3) c. Longword accessed from addresses other than longword boundaries (4n + 1, 4n + 2, 4n + 3) d. Virtual space accessed in user mode in the area H'80000000 to H'FFFFFFFF. Operations: The virtual address (32 bits) that caused the exception is set in TEA. The PC and SR of the instruction that generated the exception are saved to the SPC and SSR, respectively. If the exception occurred during a read, H'0E0 is set in EXPEVT; if the exception occurred during a write, H'100 is set in EXPEVT. The BL, MD, and RB bits in SR are set to 1 and a branch occurs to PC = VBR + H'0100. For details see section 3.5.5, Processing Flow in Event of MMU Exception. * Unconditional trap Conditions: TRAPA instruction executed Operations: The exception is a processing-completion type, so the PC of the instruction after the TRAPA instruction is saved to the SPC. SR from the time when the TRAPA instruction was executing is saved to SSR. The 8-bit immediate value in the TRAPA instruction is quadrupled and set in TRA(9-0). H'160 is set in EXPEVT. The BL, MD, and RB bits in SR are set to 1 and a branch occurs to PC = VBR + H'0100.
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* Reserved instruction exception Conditions: a. When undefined code not in a delay slot is decoded Delay branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S, BF/S Undefined instructions: H'Fxxx(SH7708, SH7708S), H'FxxF(SH7708R) b. When a privileged instruction not in a delay slot is decoded in user mode Privileged instructions: LDC, STC, RTE, LDTLB, SLEEP; instructions that access GBR with LDC/STC are not privileged instructions Operations: The PC and SR of the instruction that generated the exception are saved to the SPC and SSR, respectively. H'180 is set in EXPEVT. The BL, MD, and RB bits in SR are set to 1 and a branch occurs to PC = VBR + H'0100. When an undefined instruction other than H'Fxxx is decoded, operation cannot be guaranteed. * Illegal slot instruction Conditions: a. When undefined code in a delay slot is decoded Delay branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S, BF/S Undefined instructions: H'Fxxx(SH7708, SH7708S), H'FxxF(SH7708R) b. When an instruction that rewrites the PC in a delay slot is decoded Instructions that rewrite the PC: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT, BF, BT/S, BF/S, TRAPA, LDC Rm, SR, LDC.L, @Rm+, SR c. When a privileged instruction in a delay slot is decoded in user mode Privileged instructions: LDC, STC, RTE, LDTLB, SLEEP; instructions that access GBR with LDC/STC are not privileged instructions Operations: The PC of the previous delay branch instruction is saved to the SPC. SR of the instruction that generated the exception is saved to SSR. H'1A0 is set in EXPEVT. The BL, MD, and RB bits in SR are set to 1 and a branch occurs to PC = VBR + H'0100. When an undefined instruction other than H'Fxxx is decoded, operation cannot be guaranteed. * User break point trap Conditions: When a break condition set in the user break point controller is satisfied Operations: When a post-execution break occurs, the PC of the instruction immediately after the instruction that set the break point is set in the SPC. If a pre-execution break occurs, the PC of the instruction that set the break point is set in the SPC. SR when the break occurs is set in SSR. H'1E0 is set in EXPEVT. The BL, MD, and RB bits in SR are set to 1 and a branch occurs to PC = VBR + H'0100. See section 7, User Break Controller, for more information.
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4.5.3
Interrupts
* NMI Conditions: NMI pin edge detection Operations: The PC and SR after the instruction that receives the interrupt are saved to the SPC and SSR, respectively. H'01C0 is set in INTEVT. The BL, MD, and RB bits in SR are set to 1 and a branch occurs to PC = VBR + H'0600. This interrupt is not masked by SR.IMASK and is accepted with top priority when the BL bit in SR is 0. When the BL bit is 1, the interrupt is masked. See section 6, Interrupt Controller, for more information. * IRL interrupts Conditions: The value of the interrupt mask bits in SR is lower than the IRL3-IRL0 level and the BL bit in SR is 0. The interrupt is accepted at an instruction boundary. Operations: The PC after the instruction that accepts the interrupt is saved to the SPC. SR at the time the interrupt is accepted is saved to SSR. The code corresponding to the IRL3-IRL0 level is set in INTEVT. The corresponding code is given as H'200 + B'(IRL3-IRL0) x H'20. The BL, MD, and RB bits in SR are set to 1 and a branch occurs to VBR + H'0600. The received level is not set in SR.IMASK. See section 6, Interrupt Controller, for more information. * On-chip module interrupts Conditions: The value of the interrupt mask bits in SR is lower than the on-chip module (TMU, RTC, SCI, CPG, REF) interrupt level and the BL bit in SR is 0. The interrupt is accepted at an instruction boundary. Operations: The PC after the instruction that accepts the interrupt is saved to the SPC. SR at the time the interrupt is accepted is saved to SSR. The code corresponding to the interrupt source is set in INTEVT. See table 6.4, Interrupt Exception Vectors and Rankings, for the corresponding codes. The BL, MD, and RB bits in SR are set to 1 and a branch occurs to VBR + H'0600. B'0000 to B'1111 are set in the interrupt priority level registers (IRPA, IRPB) within the interrupt controller. See section 6, Interrupt Controller, for more information.
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4.6
Cautions
* Return from exception handling Check the BL bit in SR with software. When the SPC and SSR have been saved to external memory, set the BL bit in SR to 1 before restoring them. Issue an RTE instruction. Set the SPC in the PC and SSR in SR with the RTE instruction, branch to the SPC address, and return from exception handling. * Operation when exception or interrupt occurs while SR.BL = 1 Interrupt: Acceptance is suppressed until the BL bit in SR is set to 0 by software. If there is a request and the reception conditions are satisfied, the interrupt is accepted after the execution of the instruction that sets the BL bit in SR to 0. During the sleep or standby mode, however, the interrupt will be accepted even when the BL bit in SR is 1. Exception: No user break point trap will occur even when the break conditions are met. When one of the other exceptions occurs, a branch is made to the fixed address of the reset (H'A0000000). In this case, the values of the EXPEVT, SPC, and SSR registers are undefined. * SPC when an Exception Occurs: The PC saved to the SPC when an exception occurs is as shown below: Re-executing-type exceptions: The PC of the instruction that caused the exception is set in the SPC and re-executed after return from exception handling. If the exception occurred in a delay slot, however, the PC of the immediately prior delayed branch instruction is set in the SPC. If the condition of the conditional delayed branch instruction is not satisfied, the delay slot PC is set in SPC. Completed-type exceptions and interrupts: The PC of the instruction after the one that caused the exception is set in the SPC. If the exception was caused by a delayed conditional instruction, however, the branch destination PC is set in SPC. If the condition of the conditional delayed branch instruction is not satisfied, the delay slot PC is set in SPC. * Initial register values after reset Undefined registers R0_BANK0/1-R7_BANK0/1, R8-R15, GBR, SPC, SSR, MACH, MACL, PR Initialized registers VBR = H'00000000 SR.MD = 1, SR.BL = 1, SR.RB = 1, SR.I3-SR.I0 = H'F. Other SR bits are undefined. PC = H'A0000000 * Ensure that an exception is not generated at an RTE instruction delay slot, as operation is not guaranteed in this case. * When the BL bit in SR is 1, ensure that a TLB-related exception or address error is not caused by an LDC instruction that updates SR and the following instruction, as these may be identified as multiple exceptions and may start reset processing.
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Section 5 Cache
5.1
5.1.1
Overview
Features
The cache specifications are listed in table 5.1. Table 5.1 Cache Specifications
Parameter Capacity Structure Line size Number of entries Write system Replacement method Specification Selectable: Normal mode: 8 kbytes RAM mode: 4 kbytes cache and 4 kbytes RAM Instruction/data mixed, 4-way set associative (2-way set associative in RAM mode) 16 bytes 128 entries/way P0, P1, P3, U0: Write-back/write-through selectable Least-recently-used (LRU) algorithm
5.1.2
Cache Structure
The cache mixes data and instructions and uses a 4-way set associative system. It is composed of four ways (banks), each of which is divided into an address section and a data section. Each of the address and data sections is divided into 128 entries. The data section of the entry is called a line. Each line consists of 16 bytes (4 bytes x 4). The data capacity per way is 2 kbytes (16 bytes x 128 entries), with a total of 8 kbytes in the cache as a whole (4 ways). Figure 5.1 shows the cache structure.
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Address array (ways 0-3) Entry 0 V U Entry 1 Address 0 1 LW0
Data array (ways 0-3) LW1 LW2 LW3
LRU section 0 1
* * * *
* * * *
* * * *
Entry 127 24 (1 + 1 + 22) bits
127 128 (32 x 4) bits LW0-LW3: Longword data 0-3
127 6 bits
Figure 5.1
Cache Structure
Address Array: The V bit indicates whether the entry data is valid. When the V bit is 1, data is valid; when 0, data is not valid. The U bit indicates whether the entry has been written to in writeback mode. When the U bit is 1, the entry has been written to; when 0, it has not. The address tag holds the physical address used in the external memory access. It is composed of 22 bits (address bits 31-10) used for comparison during cache searches. In the SH7708 Series, the top three of the 32 physical address bits are used as shadow bits (see section 10), and therefore in a normal replace operation the top three bits of the vector address are cleared to 0. The V and U bits are initialized to 0 by a power-on reset, but are not initialized by a manual reset. The tag address is not initialized by either a power-on or manual reset. Data Array: Holds a 16-byte instruction or data. Entries are registered in the cache in line units (16 bytes). The data array is not initialized by a power-on or manual reset. LRU: With the 4-way set associative system, up to four instructions or data with the same entry address (address bits 10-4) can be registered in the cache. When an entry is registered, the LRU shows which of the four ways it is recorded in. There are six LRU bits, controlled by hardware. A least-recently-used (LRU) algorithm is used to select the way. In normal mode, four ways are used as cache and six LRU bits indicate the way to be replaced (table 5.2). If a bit pattern other than those listed in table 5.2 is set in the LRU bits by software, the cache will not function correctly. When modifying the LRU bits by software, set one of the patterns listed in table 5.2.
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In RAM mode, two ways are used as cache (way 0 and way 1). Bit 5 of the LRU bits indicates which way is to be replaced. When bit 5 is 0, way 1 is to be replaced. When bit 5 is 1, way 0 is to be replaced. The LRU bits are initialized to 0 by a power-on reset, but are not initialized by a manual reset. Table 5.2 LRU and Way Replacement in Normal Mode
LRU (5-0) 000000, 000100, 010100, 100000, 110000, 110100 000001, 000011, 001011, 100001, 101001, 101011 000110, 000111, 001111, 010110, 011110, 011111 111000, 111001, 111011, 111100, 111110, 111111 Way to be Replaced 3 2 1 0
5.1.3
Register Configuration
Table 5.3 shows details of the cache control register. Table 5.3 Register Configuration
Register Cache control register Abbr. CCR R/W R/W Size Longword Initial Value* H'00000000 Address H'FFFFFFEC
Note: Initialized by a power-on reset or manual reset.
5.2
5.2.1
Register Description
Cache Control Register (CCR)
The cache is enabled or disabled using the CE bit of the cache control register (CCR). CCR also has an RA bit (which switches the cache operation mode between RAM mode and normal mode), a CF bit (which invalidates all cache entries), a WT bit and a CB bit* (which selects either writethrough mode or write-back mode). Programs that change the contents of the CCR register should be placed in address space that is not cached. When updating the contents of the CCR register, always set bit 4 to 0. Figure 5.2 shows the configuration of the CCR register. CB bit is not supported in emulator. Note:SH7708S,SH7708R only
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31 -- ... ... ... ... ... ... ... ...
6 ...
5 RA
4 0
3 CF
2 *
1 WT
0 CE
RA: RAM bit. Indicates the cache operation mode. 1 = 4 kbytes cache/4 kbytes cache (RAM mode) 0 = 8 kbytes cache (normal mode) 0: Always set to 0 when setting the register. CF: Cache flush bit. Invalidates all cache entries. 1 = flush (clears the V, U, and LRU bits of all entries to 0). Always reads 0. Write-back to external memory is not performed when the cache is flushed. --: Reserved bits. Always read 0; and the write value should always be 0. WT: Write-through bit. Indicates the cache's operating mode for areas P0, U0, and P3. 1 = write-through mode, 0 = write-back mode. CE: Cache enable bit. Indicates whether the cache function is used. 1 = cache used, 0 = cache not used. CB: P1 area write-back/write-through switching bit 1 = write-back mode, 0 = write-through mode Note:SH7708:Reserved bit SH7708S,SH7708R:CB
Figure 5.2
CCR Register Configuration
5.3
5.3.1
Cache Operation
Searching the Cache
If the cache is enabled, whenever instructions or data in memory are accessed the cache will be searched to see if the desired instruction or data is in the cache. Figure 5.3 illustrates the method by which the cache is searched. The cache is a physical cache and holds physical addresses in its address section. Entries are selected using bits 10-4 of the address (virtual) of the access to memory and the address tag of that entry is read. In parallel to reading of the address tag, the virtual address is translated to a physical address in the MMU. The physical address after translation and the physical address read from the address section are compared. The address comparison uses all four ways in normal mode. In RAM mode, two ways (way 0 and way 1) are used in the address comparison. When the comparison shows a match and the selected entry is valid (V = 1), a cache hit occurs. When the comparison does not show a match or the selected entry is not valid (V = 0), a cache miss occurs. Figure 5.3 shows a hit on way 1.
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Virtual address 31 11 10 4 3 210
Entry selection
Longword (LW) selection Ways 0-3 Ways 0-3
MMU
0 1
VU
Address
LW0
LW1
LW2
LW3
127 Physical address
CMP0 CMP1 CMP2 CMP3
Hit signal 1 CMP0: CMP1: CMP2: CMP3: Comparison circuit 0 Comparison circuit 1 Comparison circuit 2 Comparison circuit 3
Figure 5.3
Cache Search Scheme (Normal Mode)
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5.3.2
Read Access
Read Hit: In a read access, instructions and data are transferred from the cache to the CPU. The transfer unit is 32 bits. The LRU is updated. Read Miss: An external bus cycle starts and the entry is updated. The way replaced is the one least recently used. Entries are updated in 16-byte units. When the desired instruction or data that caused the miss is loaded from external memory to the cache, the instruction or data is transferred to the CPU in parallel with being loaded to the cache. When it is loaded in the cache, the U bit is cleared to 0 and the V bit is set to 1. When the U bit of a replaced entry in write-back mode is 1, the cache fill cycle starts after the entry is transferred to the write-back buffer. After the cache completes its fill cycle, the write-back buffer writes back the entry to memory. The write-back unit is 16 bytes. 5.3.3 Write Access
Write Hit: In a write access in write-back mode, data is written to the cache and the U bit of the entry written is set to 1. Writing occurs only to the cache; no external memory write cycle is issued. In write-through mode, data is written to the cache and an external memory write cycle is issued. Write Miss: In write-back mode, an external bus cycle starts when a write miss occurs and an entry with its U bit set to 1 is replaced. The way to be replaced is the one least recently used. When the U bit of the entry to be replaced is 1, the cache fill cycle starts after the entry is transferred to the write-back buffer. After the cache completes its fill cycle, the write-back buffer writes back the entry to memory. The write-back unit is 16 bytes. Data is written to the cache and the U bit is set to 1. In write-through mode, no write to cache occurs in a write miss; the write is only to external memory. 5.3.4 Write-Back Buffer
When the U bit of the entry to be replaced in write-back mode is 1, it must be written back to external memory. To increase performance, the entry to be replaced is first transferred to the writeback buffer and fetching of new entries to the cache takes priority over writing back to external memory. During the write back cycles, the cache can be accessed. The write-back buffer can hold one line of cache data (16 bytes) and its physical address. Figure 5.4 shows the configuration of the write-back buffer.
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PA (31-4) Longword 0 Longword 1 Longword 2 Longword 3
PA (31-4): Physical address written to external memory Longword 0-3: The line of cache data to be written to external memory
Figure 5.4 5.3.5
Write-Back Buffer Configuration
Coherency of Cache and External Memory
Use software to ensure coherency between the cache and the external memory. When memory shared by the SH7708 Series and another device is accessed, the latest data may be in a write-back mode cache, so invalidate the entry that includes the latest data in the cache, generate a write back, and update the data in memory before using it. When the caching area is updated by a device other than the SH7708 Series, invalidate the entry that includes the updated data in the cache. 5.3.6 RAM Mode
In RAM mode, way 0 and way 1 function as a 4-kbyte two-way set associative cache, while way 2 and way 3 function as 4-kbyte internal RAM. The internal RAM is mapped onto H'7F000000 to H'7F000FFF with 4-kbyte shadow areas from H'7F001000 to H'7FFFFFFF. In RAM mode with the MMU enabled, a virtual address from H'7F00000 to H'7FFFFFFF is not translated to an external physical address. The internal RAM can be accessed in both privileged and user mode by setting its address as source or destination address in the instructions. Before changing the RA bit in the CCR register to change the cache operation mode, all entries in the cache should be invalidated.
5.4
Memory-Mapped Cache
To allow software management of the cache, it is mapped onto virtual address space P4. The address array is mapped onto addresses H'F0000000 to H'F0FFFFFF and the data array onto addresses H'F1000000 to H'F1FFFFFF. In privileged mode, the cache contents can be read or written using the MOV instruction. With the address array and data array, the access size is fixed at longword, and instruction fetches cannot be performed. 5.4.1 Address Array
The address array is mapped onto H'F0000000 to H'F0FFFFFF. To access an address array, the 32bit address field (for read/write accesses) and 32-bit data field (for write accesses) must be specified. The address field specifies information for selecting the entry to be accessed; the data field specifies the address, V bit, U bit, and LRU bits to be written to the address array (figure 5.5(1)).
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In the address field, specify the entry address for selecting the entry (bits 10-4), W for selecting the way (bits 12-11: 00 is way 0, 01 is way 1, 10 is way 2, 11 is way 3 in normal mode (8-kbyte cache); 00 and 10 are way 0, and 01 and 11 are way 1 in RAM mode), and H'F0 to indicate address array access (bits 31-24). When writing, specify bit 3 as the A bit. The A bit indicates whether addresses are compared during writing. When the A bit is 1, the addresses of the four entries selected by the entry addresses are compared to the addresses to be written into the address array specified in the data field. Writing takes place to the way that has a hit. When a miss occurs, nothing is written to the address array and no operation occurs. The way number (W) specified in bits 12-11 is not used. When the A bit is 0, it is written to the entry selected with the entry address and way number without comparing addresses. The address specified by bits 31-10 in the data specification in figure 5.5 (1), address array access, is a virtual address. When the MMU is enabled, the address is translated into a physical address, then the physical address is used in comparing addresses when the A bit is 1. The physical address is written into the address array. When reading, the address tag, V bit, U bit, and LRU bits of the entry specified by the entry address and way number (W) are read using the data format shown in figure 5.5 without comparing addresses. To invalidate a specific entry, specify the entry by its entry address and way number, and write 0 to its V bit. To invalidate only an entry for an address to be invalidated, specify 1 for the A bit. When an entry for which 0 is written to the V bit has a U bit set to 1, if it is a valid entry it will be written back. This allows coherency to be achieved between the external memory and cache by invalidating the entry. However, when 0 is written to the V bit, 0 must also be written to the U bit of that entry. In the SH7708 Series, the top 3 bits of the 32-bit physical address are treated as a shadow (see section 10, Bus State Controller (BSC)). Therefore, in the event of a cache miss, 0 is registered in the top 3 bits of the address array address tag. When directly changing the address array using the MOV instruction, also, a value other than 0 must not be set in the top 3 bits of the address tag. 5.4.2 Data Array
The data array is mapped onto H'F1000000 to H'F1FFFFFF. To access a data array, the 32-bit address field (for read/write accesses) and 32-bit data field (for write accesses) must be specified. The address field specifies information for selecting the entry to be accessed; the data field specifies the longword data to be written to the data array (figure 5.5 (2)). In the address field, specify the entry address for selecting the entry (bits 10-4), L for indicating the longword position within the (16 byte) line (bits 3-2: 00 is longword 0, 01 is longword 1, 10 is longword 2, 11 is longword 3), W for selecting the way (bits 12-11: 00 is way 0, 01 is way 1, 10
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is way 2, 11 is way 3 in normal mode; 00 and 10 are way 0, and 01 and 11 are way 1 in RAM mode), and H'F1 to indicate data array access (bits 31-24). Both reading and writing use the longword of the data array specified by the entry address, way number and longword address. The access size of the data array is fixed at longword.
(1) Address array access Address specification Read access 31 24 23 13 12 11 10 11110000 ---- W
4 Entry
*
*
3 0
2
0
***
2 0
Write access 31 24 23 13 12 11 10 11110000 ---- W
4 Entry
*
*
3 A
***
1 U 0 V
Data specification (both read and write accesses) 31 Address tag (31-10) 10 9 LRU 4 3 2 XX
(2) Data array access (both read and write accesses) Address specification 31 24 23 13 12 11 10 11110001 ---- W 43 Entry L 21 0
*
*
**
0
Data specification 31 Longword
*
X: 0 for read, don't care bit for write : Don't care bit
Figure 5.5
Specifying Address and Data for Memory-Mapped Cache Access
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5.5
5.5.1
Usage Examples
Invalidating Specific Entries
Specific cache entries can be invalidated by writing 0 to the entry's V bit. When the A bit is 1, the address tag specified by the write data is compared to the address tag within the cache selected by the entry address, and data is written when a match is found. If no match is found, there is no operation. R0 specifies the write data in R0 and R1 specifies the address. When the V bit of an entry in the address array is set to 0, the entry is written back if the entry's U bit is 1.
; R0=H'01100010; VPN=B'0000 0001 0001 0000 0000 00, U=0, V=0 ; R1=H'F0000088; address array access, entry=B'0001000, A=1 ; MOV.L R0,@R1
5.5.2
Reading the Data of a Specific Entry
This example reads the data section of a specific cache entry. The longword indicated in the data field of the data array in figure 5.5 is read to the register. R0 specifies the address and R1 is read.
; R1=H'F100 004C; data array access, entry=B'0000100, Way = 0, longword ; address = 3 ; MOV.L @R0,R1 ; Longword 3 is read.
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Section 6 Interrupt Controller (INTC)
6.1 Overview
The interrupt controller (INTC) ascertains the priority of interrupt sources and controls interrupt requests to the CPU. The INTC registers set the order of priority of each interrupt, allowing the user to handle interrupt requests according to the user-set priority. 6.1.1 Features
INTC has the following features: * 15 levels of interrupt priority can be set: By setting the two interrupt-priority registers, the priorities of on chip supporting module interrupts can be selected from 15 levels for different request sources. * NMI noise canceller function: NMI input level bit indicates NMI pin status. By reading this bit in the interrupt exception handler, the pin status can be checked, enabling it to be used as a noise canceler. * External devices can be notified that an interrupt has been received (IRQOUT pin): For example, when the SH7708 Series has released the bus, the external bus master can be notified of the fact that an external interrupt, an on-chip supporting module interrupt, or a memory refresh request has occurred, enabling the SH7708 Series to request the bus.
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6.1.2
Block Diagram
Figure 6.1 shows a block diagram of the INTC.
IRQOUT NMI IRL3-IRL0
Input control 4 (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request/ refresh request) CPU 4 Priority identifier Comparator Interrupt request SR 3210
TMU RTC SCI WDT REF
ICR
IPR IPRA-IPRB Internal bus
Bus interface INTC TMU: RTC: SCI: WDT: REF: ICR: IPRA-IPRB: SR: Timer unit Realtime clock unit Serial communication interface Watch dog timer Memory refresh controller section of the bus state controller Interrupt control register Interrupt priority level setting registers A-B Status register
Figure 6.1
INTC Block Diagram
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6.1.3
Pin Configuration
Table 6.1 shows the INTC pin configuration. Table 6.1 Pin Configuration
Name Nonmaskable interrupt input pin Interrupt input pins Bus request output pin Abbreviation I / O NMI I I O Description Input of nonmaskable interrupt request signal Input of interrupt request signals (maskable by I3-I0 in SR) Output of signal that notifies external devices that an interrupt or memory refresh request has occurred
IRL3-IRL0
IRQOUT
6.1.4
Register Configuration
The INTC has the three registers listed in table 6.2. Table 6.2 Register Configuration
Name Interrupt control register Interrupt priority level setting register A Interrupt priority level setting register B Abbr. ICR IPRA IPRB R/W R/W R/W R/W Initial Value* 1 Address *2 H'0000 H'0000 H'FFFFFEE0 H'FFFFFEE2 H'FFFFFEE4 Access Size 16 16 16
Notes: 1. Initialized by a power-on reset or manual reset. 2. H'8000 when the NMI pin is high, H'0000 when the NMI pin is low.
6.2
Interrupt Sources
There are three types of interrupt sources: NMI, IRL, and on-chip supporting modules. Each interrupt has a priority level (0-16) with 0 the lowest and 16 the highest. Priority level 0 masks an interrupt.
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6.2.1
NMI Interrupts
The NMI interrupt has the highest priority level of 16. It is always accepted unless the BL bit in the status register in the CPU is set to 1, and is edge-detected. In sleep or standby mode, the interrupt is accepted regardless of the BL setting. The NMI edge select bit (NMIE) in the interrupt control register (ICR) is used to select either the rising or falling edge. When the NMIE bit in the ICR register is changed, the NMI interrupt is not detected for 20 cycles after changing ICR. NMI interrupt exception handling does not affect the interrupt mask level bits (I3-I0) in the status register (SR). 6.2.2 IRL Interrupts
IRL interrupts are input by level at pins IRL3-IRL0. The priority level is the level indicated by pins IRL3-IRL0. An IRL3-IRL0 value of 0 (0000) indicates the highest-level interrupt request (interrupt priority level 15). A value of 15 (1111) indicates no interrupt request (interrupt priority level 0). Figure 6.2 shows an examples of an IRL interrupt connection. Table 6.3 shows IRL pins and interrupt levels.
SH7708Series
Interrupt request
Priority encoder
4 IRL3 to IRL0
IRL3 to IRL0
Figure 6.2
Example of IRL Interrupt Connection
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Table 6.3 IRL3-IRL0 Pins and Interrupt Levels
IRL3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 IRL2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 IRL1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 IRL0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Interrupt Priority LevelInterrupt Request 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Level 15 interrupt request Level 14 interrupt request Level 13 interrupt request Level 12 interrupt request Level 11 interrupt request Level 10 interrupt request Level 9 interrupt request Level 8 interrupt request Level 7 interrupt request Level 6 interrupt request Level 5 interrupt request Level 4 interrupt request Level 3 interrupt request Level 2 interrupt request Level 1 interrupt request No interrupt request
A noise-cancellation feature is built in, and the IRL interrupt is not detected unless the levels sampled at every supporting module cycle remain unchanged for two consecutive cycles, so that no transient level on the IRL pin change is detected. In standby mode, as the peripheral clock is stopped, noise cancellation is performed using the 32.768 kHz clock for the RTC instead. Therefore when the RTC is not used, interruption by means of IRL interrupts cannot be performed in standby mode. The priority level of the IRL interrupt must not be lowered unless the interrupt is accepted and the interrupt handling starts. However, the priority level can be changed to a higher one. The interrupt mask bits (I3-I0) in the status register (SR) are not affected by IRL interrupt handling.
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6.2.3
On-Chip Supporting Module Interrupts
On-chip supporting module interrupts are generated by the following five modules: * * * * * Timer unit (TMU) Realtime clock (RTC) Serial communication interface (SCI) Bus state controller (BSC) Watchdog timer (WDT)
Not every interrupt source is assigned a different interrupt vector. Sources are reflected on the interrupt event register (INTEVT). It is easy to identify sources by using the values of the INTEVT register as branch offsets (in the exception handler routine). The priority level (from 0-15) can be set for each module by writing to interrupt priority setting registers A-B (IPRA-IPRB). The interrupt mask bits (I3-I0) in the status register are not affected by the on-chip supporting module interrupt handling. On-chip supporting module interrupt source flag and interrupt enable flag updating should only be performed when the BL bit in the status register (SR) is set to 1. To prevent acknowledgment of an erroneous interrupt from an interrupt source that should have been updated, first read the on-chip peripheral register containing the relevant flag, then clear the BL bit to 0. This will secure the necessary timing internally. When updating a number of flags, there is no problem if only the register containing the last flag updated is read. If flag updating is performed while the BL bit is cleared to 0, the program may jump to the interrupt service routine when the INTEVT register value is 0. In this case, interrupt handling is initiated due to the timing relationship between the flag update and interrupt request recognition within the chip. Processing can be continued without any problem by executing an RTE instruction. 6.2.4 Interrupt Exception Handling and Priority
Table 6.3 lists the codes for the interrupt event register (INTEVT), and the order of interrupt priority. Each interrupt source is assigned unique code. The start address of the interrupt handler is common to each interrupt source. This is why, for instance, the value of INTEVT is used as offset at the start of the interrupt handler and branched to identify the interrupt source. The order of priority of the on-chip supporting module is set within the priority levels 0-15 at will by using the interrupt priority level set in registers A and B (IPRA-IPRB). The order of priority of the on-chip supporting module is set to zero by a reset.
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When the priorities for multiple interrupt sources are set to the same level and such interrupts are generated at the same time, they are handled according to the default order listed in table 6.4. Updating of interrupt priority level setting registers A and B should only be performed when the BL bit in the status register (SR) is set to 1. To prevent erroneous interrupt acknowledgment, first read one or other of the interrupt priority level setting registers, then clear the BL bit to 0. This will secure the necessary timing internally. Table 6.4 Interrupt Exception Vectors and Rankings
Interrupt Source NMI IRL I N T E V T Interrupt IPR (Bit Code Priority (Initial Numbers) Value) H'1C0 IRL3 -IRL0 = 0000 H'200 IRL3 -IRL0 = 0001 H'220 IRL3 -IRL0 = 0010 H'240 IRL3 -IRL0 = 0011 H'260 IRL3 -IRL0 = 0100 H'280 IRL3 -IRL0 = 0101 H'2A0 IRL3 -IRL0 = 0110 H'2C0 IRL3 -IRL0 = 0111 H'2E0 IRL3 -IRL0 = 1000 H'300 IRL3 -IRL0 = 1001 H'320 IRL3 -IRL0 = 1010 H'340 IRL3 -IRL0 = 1011 H'360 IRL3 -IRL0 = 1100 H'380 IRL3 -IRL0 = 1101 H'3A0 IRL3 -IRL0 = 1110 H'3C0 TMU0 TMU1 TMU2 TMU2 TUNI0*1 TUNI1*1 TUNI2*1 TICPI2*2 H'400 H'420 H'440 H'460 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0-15 (0) 0-15 (0) 0-15 (0) 0-15 (0) -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Priority within D e f a u l t IPR Setting Priorit Unit y -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- High
IPRA (15-12) -- IPRA (11-8) -- IPRA (7-4) IPRA (7-4) High Low Low
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Table 6.4 Interrupt Exception Vectors and Rankings (cont)
I N T E V T Interrupt IPR (Bit Interrupt Source Code Priority (Initial Numbers) Value) RTC RTC RTC SCI SCI SCI SCI WDT REF REF ATI*3 PRI*4 CUI*5 ERI*6 RXI*7 TXI*8 TEI*9 ITI RCMI*10 ROVI*11 H'480 H'4A0 H'4C0 H'4E0 H'500 H'520 H'540 H'560 H'580 H'5A0 0-15 (0) 0-15 (0) 0-15 (0) 0-15 (0) 0-15 (0) 0-15 (0) 0-15 (0) 0-15 (0) 0-15 (0) 0-15 (0) IPRA (3-0) IPRA (3-0) IPRA (3-0) IPRB (7-4) IPRB (7-4) IPRB (7-4) IPRB (7-4) IPRB (15-12) IPRB (11-8) IPRB (11-8) Low -- High Low Low Priority within D efault IPR Setting Unit Priority High Low High High
Notes: 1. TUNI0-TUNI2: Underflow interrupts, see section 11. 2. TICPI2: Input capture interrupt, see section 11. 3. ATI: Alarm interrupt, see section 12. 4. PRI: Periodic interrupt, see section 12. 5. CUI: Carry-up interrupt, see section 12. 6. ERI: Receive error interrupt, see section 13. 7. RXI: Receive-data-full interrupt, see section 13. 8. TXI: Transmit-data-empty interrupt, see section 13. 9. TEI: Transmit-data-end interrupt, see section 13. 10. ITI: Interval timer interrupt, see section 9. 11. RCMI: Compare-match interrupt, see section 10. 12. ROVI: Refresh counter overflow interrupt, see section 10.
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6.3
6.3.1
INTC Registers
Interrupt Priority Registers A and B (IPRA-IPRB)
Interrupt priority registers A and B (IPRA and IPRB) are 16-bit read/write registers that set priority levels from 0 to 15 for on-chip supporting module interrupts. These registers are initialized to H'0000 by a reset. They are not initialized in standby mode.
Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 15 14 13 12 11 10 9 8
Table 6.5 lists the relationship between the interrupt sources and the IPRA and IPRB bits. Table 6.5 Interrupt Request Sources and IPRA-IPRB
Register IPRA IPRB Bits 15 to 12 TMU0 WDT Bits 11 to 8 TMU1 REF*1 Bits 7 to 4 TMU2 SCI Bits 3 to 0 RTC Reserved *2
Notes: 1. REF is the memory refresh unit in the bus state controller. See section 10, Bus State Controller, for details. 2. Reserved bits: Always read 0. Only 0 should be written.
As listed in table 6.5, four sets of on-chip supporting modules are assigned to each register. 4-bit groups (bits 15 to 12, bits 11 to 8, bits 7 to 4, and bits 3 to 0) are set with values from H'0 (0000) to H'F (1111). Setting H'0 means priority level 0 (masking is requested); H'F is priority level 15 (the highest level).
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6.3.2
Interrupt Control Register (ICR)
ICR is a 16-bit register that sets the input signal detection mode of the external interrupt input pin NMI and indicates the input signal level to the NMI pin. This register is initialized by a power-on reset or manual reset. It is not initialized in standby mode.
Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: 15 NMIL 0/1* R 7 -- 0 R 14 -- 0 R 6 -- 0 R 13 -- 0 R 5 -- 0 R 12 -- 0 R 4 -- 0 R 11 -- 0 R 3 -- 0 R 10 -- 0 R 2 -- 0 R 9 -- 0 R 1 -- 0 R 8 NMIE 0 R/W 0 -- 0 R
Note: When NMI input is high: 1; when NMI input is low: 0.
Bit 15--NMI Input Level (NMIL): Sets the level of the signal input at the NMI pin. This bit can be read to determine the NMI pin level. It cannot be modified.
Bit 15: NMIL 0 1 Description NMI input level is low NMI input level is high
Bit 8--NMI Edge Select (NMIE): Selects whether the falling or rising edge of the interrupt request signal to the NMI is detected.
Bit 8: NMIE 0 1 Description Interrupt request is detected on the falling edge of NMI input (Initial value) Interrupt request is detected on rising edge of NMI input
Bits 14-9 and 7-0--Reserved: These bits always read 0. The write value should always be 0.
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6.4
6.4.1
INTC Operation
Interrupt Sequence
The sequence of interrupt operations is explained below. Figure 6.3 is a flowchart of the operations. 1. The interrupt request sources send interrupt request signals to the interrupt controller. 2. The interrupt controller selects the highest priority interrupt from the interrupt requests sent, following the priority levels set in interrupt priority registers A and B (IPRA and IPRB). Lower priority interrupts are held pending. If two of these interrupts have the same priority level or if multiple interrupts occur within a single module, the interrupt with the highest default priority or the highest priority within its IPR setting unit (as indicated in table 6.4) is selected. 3. The priority level of the interrupt selected by the interrupt controller is compared with the interrupt mask bits (I3-I0) in the status register (SR) of the CPU. If the request priority level is higher than the level in bits I3-I0, the interrupt controller accepts the interrupt and sends an interrupt request signal to the CPU. When the interrupt controller receives an interrupt, a low level is output from the IRQOUT pin. 4. The CPU receives an interrupt at a break in instructions. 5. The interrupt source code is set in the interrupt event register (INTEVT). 6. The status register (SR) and program counter (PC) are saved to SSR and SPC, respectively. 7. The block bit (BL), mode bit (MD), and register bank bit (RB) in SR are set to 1. 8. The CPU jumps to the start address of the interrupt handler (the sum of the value set in the vector base register (VBR) and H'00000600). The interrupt handler may branch with the INTEVT register value as its offset in order to identify the interrupt source. This enables it to branch to the handling routine for the individual interrupt source. Notes: 1. The interrupt mask bits (I3-I0) in the status register (SR) are not changed by acceptance of an interrupt in the SH7708 Series. 2. IRQOUT outputs a low level until the interrupt request is cleared. However, if the interrupt source is masked by an interrupt mask bit, the IRQOUT pin returns to the high level. The level is output without regard to the BL bit. 3. The interrupt source flag should be cleared in the interrupt handler. To ensure that an interrupt request that should have been cleared is not inadvertently accepted again, read the interrupt source flag after it has been cleared, then wait for the interval shown in table 6.6 (Time for priority decision and SR mask bit comparison) before clearing the BL bit or executing an RTE instruction.
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Program execution state
Interrupt generated? Yes (SR. BL = 0) or (sleep or standby mode)? Yes NMI? Yes
No
No
No
Level 15 interrupt? Yes Yes I3-I0 level 14 or lower? No Yes
No
Level 14 interrupt? Yes I3-I0 level 13 or lower? No Yes
No
Level 1 interrupt? Yes I3-I0 level 0? No
No
IRQOUT = low Set interrupt cause in INTEVT Save SR to SSR; save PC to SPC Set BL/MD/RB bits in SR to 1 Branch to exception handler I3-I0:
Interrupt mask bits in status register (SR)
Figure 6.3
118
Interrupt Operation Flowchart
6.4.2
Multiple Interrupts
When handling multiple interrupts, an interrupt handler should include the following procedures: 1. Branch to a specific interrupt handler corresponding to a code set in INTEVT. The code in INTEVT can be used as a branch-offset for branching to the specific handler. 2. Clear the cause of the interrupt in each specific handler. 3. Save SSR and SPC to memory. 4. Clear the BL bit in SR, and set the accepted interrupt level in the interrupt mask bits in SR. 5. Handle the interrupt. 6. Execute the RTE instruction. When these procedures are followed in order, an interrupt of higher priority than the one being handled can be accepted after clearing BL in step 4. Figure 6.3 shows a sample interrupt operation flowchart.
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6.5
Interrupt Response Time
The time from generation of an interrupt request until interrupt exception handling is performed and fetching of the first instruction of the exception handler is started (the interrupt response time) is shown in table 6.6. Figure 6.4 shows an example of pipeline operation when an IRL interrupt is accepted. When SR.BL is 1, interrupt exception handling is masked, and is kept waiting until completion of an instruction that clears BL to 0. Table 6.6 Interrupt Response Time
Number of States Item Time for priority decision and SR mask bit comparison Wait time until end of sequence being executed by CPU NMI 0.5 x Icyc + 0.5 x Bcyc + 0.5 x Pcyc X ( 0) x Icyc IRL 0.5 x Icyc + 0.5 x Bcyc + 2 x Pcyc X ( 0) x Icyc Supporting Modules 0.5 x Icyc + 1.5 x Pcyc X ( 0) x Icyc Interrupt exception handling is kept waiting until the executing instruction ends. If the number of instruction execution states is S*1, the maximum wait time is: X = S - 1. However, if BL is set to 1 by instruction execution or by an exception, interrupt exception handling is deferred until completion of an instruction that clears BL to 0. If the following instruction masks interrupt exception handling, the handling may be further deferred. Notes
Time from interrupt exception handling (save of SR and PC) until fetch of first instruction of exception handler is started
5 x Icyc
5 x Icyc
5 x Icyc
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Table 6.6 Interrupt Response Time (cont)
Number of States Item Response time Total NMI RL Peripheral Modules Notes
(5.5 + X) x Icyc (5.5 + X) x Icyc (5.5 + X) x Icyc + 0.5 x Bcyc + 0.5 x Bcyc + 1.5 x Pcyc + 0.5 x Pcyc + 2 x Pcyc 6.5 7+S 8 13 + S 7 10.5 + S At 60 MHz operation: 0.10-0.14 s At 60 MHz operation: 0.23-0.34 s (in case of operand cache-hit) At 60 MHz operation: 0.27-0.37 s (when external memory access is performed with wait = 0)
Minimum case* 2 Maximum case* 3
Icyc: Duration of one cycle of internal clock supplied to CPU, etc. Bcyc: Duration of one CKIO cycle Pcyc: Duration of one cycle of peripheral clock supplied to supporting modules Notes: 1. S also includes the memory access wait time. The processing requiring the maximum execution time is LDC.L @Rm+, SR. When the memory access is a cache-hit, this requires 7 instruction execution cycles. When external access is performed, the corresponding number of cycles must be added. There are also instructions that perform two external memory accesses; if external memory access is slow, the number of instruction execution cycles will increase accordingly. 2. The internal clock : CKIO : peripheral clock ratio is 1 : 1 : 1. 3. The internal clock : CKIO : peripheral clock ratio is 1 : 1 : 1/4.
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Interrupt acceptance 0.5 x Icyc + 0.5 x Bcyc + 2 x Pcyc IRL Instruction (instruction replaced by interrupt exception handling) Overrun fetch First instruction of interrupt handler
Start of interrupt handling
5 x Icyc
IF
ID
EX
EX
EX
EX
IF
IF
ID
EX
IF: Instruction fetch ... Instruction is fetched from memory in which program is stored. ID: Instruction decode ... Fetched instruction is decoded. EX: Instruction execution ... Data operation and address calculation are performed in accordance with result of decoding.
Figure 6.4
Example of Pipeline Operations when IRL Interrupt is Accepted
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Section 7 User Break Controller (UBC)
7.1 Overview
The user break controller (UBC) provides functions that simplify program debugging. These functions make it easy to design an effective self-monitoring debugger, enabling programs to be debugged in the chip alone, without using an in-circuit emulator. Break conditions that can be set in the UBC are instruction fetch or data read/write, data size, data content, address value, and stop timing during instruction fetches. 7.1.1 Features
The features of the user break controller are listed below. * Two break channels (channel A and channel B). User break interrupts can be requested using either independent or sequential condition for the two channels (sequential breaks are channel A, then channel B). * Selection and setting of the following as break compare conditions: Address Selection of 32-bit logical address and ASID to be compared Address: Compare all bits, mask bottom 10 bits, mask bottom 12 bits. mask all bits ASID: Compare all bits/mask all bits Data (channel B only, 32-bit maskable) Bus cycle: Instruction fetch/data access Read/write Operand size: byte/word/longword * The instruction fetch cycle break can be performed before or after the instruction is executed. * User break trap generated when break conditions are satisfied. A user-designed user break trap routine can be run. 7.1.2 Block Diagram
Figure 7.1 shows the logical block diagram of the user break controller.
123
Access control
Address bus
Channel A Access comparator BBRA
Data bus
BARA Address comparator BASRA BAMRA
Channel B Access comparator BBRB
BARB Address comparator BASRB BAMRB
Data comparator
BDRB BDMRB
BBRA: BARA: BASRA: BAMRA: BBRB: BARB: BASRB: BAMRB: BDRB: BDMRB: BRCR:
Break bus cycle register A Break address register A Break ASID register A Break address mask register A Break bus cycle register B Break address register B Break ASID register B Break address mask register B Break data register B Break data mask register B Break control register
Control
BRCR
User break trap request
Figure 7.1
Logical Block Diagram of User Break Controller
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7.1.3
Register Configuration
Table 7.1 shows the user break controller registers. Table 7.1 UBC Registers
Channel A Register BARA BASRA BAMRA BBRA B BARB BAMRB BASRB BBRB BDRB BDMRB Common BRCR Initial Value* 1 Access Size Access Address R / W Undefined Undefined Undefined H'0000*2 Undefined Undefined Undefined H'0000*2 Undefined Undefined H'0000*2 Longword Byte Byte Word Longword Byte Byte Word Longword Longword Word H'FFFFFFB0 H'FFFFFFE4 H'FFFFFFB4 H'FFFFFFB8 H'FFFFFFA0 H'FFFFFFA4 H'FFFFFFE8 H'FFFFFFA8 H'FFFFFF90 H'FFFFFF94 H'FFFFFF98
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Notes: 1. Value is retained in standby mode. 2. Initialized by power-on reset or manual reset.
7.1.4
Break Conditions and Register Settings
The relationship between break conditions and register settings is as follows: 1. Break conditions for channel A or B are set in the respective registers. 2. The address is set in the BARA or BARB register. ASID is set in the BASRA or BASRB register. Whether the address is included in the break conditions, or whether or not masking is to be performed, is set in the BAMA or BAMB bit of the BAMRA or BAMRB register. If ASID is included in the conditions, this is set in the BASMA or BASMB bit of the BAMRA or BAMRB register. 3. Bus cycle break conditions are set in the BBRA or BBRB register. Settings are instruction fetch or data access, read or write, and data access size. In the case of an instruction fetch, whether the break is to be made before or after instruction execution is set in the PCBA or PCBB bit of the BRCR register. 4. For channel B, data can be included in the break conditions. Data is set in the BDRB register. If data is to be masked, it is set in the BDMRB register. Data inclusion in or exclusion from break conditions is set in the DBEB bit of the BRCR register.
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5. Sequential use of channels A and B is set in the SEQ bit of the BRCR. When sequential use is designated, a user break occurs when the channel B conditions are matched after matching of channel A conditions. 6. When a user break occurs, the CMFA and CMFB bits in the BRCR register are set to 1. If a break is to be generated again, the CMFA and CMFB bits should be cleared to 0.
7.2
7.2.1
UBC Register Functions
Break Address Register A (BARA)
Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: 31 BAA31 -- R/W 23 BAA23 -- R/W 15 BAA15 -- R/W 7 BAA7 -- R/W 30 BAA30 -- R/W 22 BAA22 -- R/W 14 BAA14 -- R/W 6 BAA6 -- R/W 29 BAA29 -- R/W 21 BAA21 -- R/W 13 BAA13 -- R/W 5 BAA5 -- R/W 28 BAA28 -- R/W 20 BAA20 -- R/W 12 BAA12 -- R/W 4 BAA4 -- R/W 27 BAA27 -- R/W 19 BAA19 -- R/W 11 BAA11 -- R/W 3 BAA3 -- R/W 26 BAA26 -- R/W 18 BAA18 -- R/W 10 BA10 -- R/W 2 BAA2 -- R/W 25 BAA25 -- R/W 17 BAA17 -- R/W 9 BAA9 -- R/W 1 BAA1 -- R/W 24 BAA24 -- R/W 16 BAA16 -- R/W 8 BAA8 -- R/W 0 BAA0 -- R/W
Break address register A (BARA) is a 32-bit read/write register that stores the virtual address of the channel A break condition. It is not initialized by a reset. Bits 31 to 0--Break Address A31 to 0 (BAA31 to BAA0): These bits store the virtual address of the channel A break condition. 7.2.2 Break Address Register B (BARB)
BARB is the break address register for channel B. The bit configuration is the same as for BARA.
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7.2.3
Break ASID Register A (BASRA)
Bit: Bit name: Initial value: R/W: 7 BASA7 -- R/W 6 BASA6 -- R/W 5 BASA5 -- R/W 4 BASA4 -- R/W 3 BASA3 -- R/W 2 BASA2 -- R/W 1 BASA1 -- R/W 0 BASA0 -- R/W
Break ASID register A (BASRA) specifies the ASID that serves as the break condition for channel A. It is compared to the ASID field of the MMU's PTEH register. BASRA is an 8-bit read/write register. It is not initialized by a reset. Bits 7 to 0--Break ASID A7 to 0 (BASA7 to BASA0): These bits store the ASID (bits 7 to 0) that is the channel A break condition. 7.2.4 Break ASID Register B (BASRB)
BASRB is the break ASID register for channel B. The bit configuration is the same as for BASRA. 7.2.5 Break Address Mask Register A (BAMRA)
Bit: Bit name: Initial value: R/W: 7 -- 0 R/W 6 -- 0 R/W 5 -- 0 R/W 4 -- 0 R/W 3 -- 0 R/W 2 BASMA -- R/W 1 BAMA1 -- R/W 0 BAMA0 -- R/W
Break address mask register A (BAMRA) is an 8-bit read/write register that specifies which bits in the break ASID specified in BASRA and which bits in the break address specified in BARA are masked. It is not initialized by a reset. Bits 7 to 3--Reserved: These bits always read 0. The write value should always be 0. Bit 2--Break ASID Mask A (BASMA): Indicates whether the bits of the channel A breakpoint ASID7 to ASID0 (BASA7 to BASA0) set in BASRA are masked.
Bit 2: BASMA 0 1 Description BASRA not masked; all bits included in break condition. All BASRA bits masked; ASID not included in break condition.
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Bits 1 and 0--Break Address Mask A1 and A0 (BAMA1 and BAMA0): These bits indicate which of the channel A break address bits 31-0 (BAA31-BAA0) set in BARA are masked.
Bit 1: BAMA1 0 0 1 1 Bit 0: BAMA0 0 1 0 1 Description BARA not masked; all bits included in break condition. Lowest 10 bits masked and excluded from break condition. Lowest 12 bits masked and excluded from break condition. All BARA bits masked; address not included in break condition.
7.2.6
Break Address Mask Register B (BAMRB)
BAMRB is the break address mask register for channel B. The bit configuration is the same as for BAMRA. 7.2.7 Break Bus Cycle Register A (BBRA)
Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: 15 -- 0 R 7 -- 0 R 14 -- 0 R 6 -- 0 R 13 -- 0 R 5 IDA1 0 R/W 12 -- 0 R 4 IDA0 0 R/W 11 -- 0 R 3 RWA1 0 R/W 10 -- 0 R 2 RWA0 0 R/W 9 -- 0 R 1 SZA1 0 R/W 8 -- 0 R 0 SZA0 0 R/W
The break bus cycle register A (BBRA) is a 16-bit read/write register that sets the following three channel A break conditions for channel A: (1) instruction fetch/data access, (2) read/write, and (3) operand size. A reset initializes BBRA to H'0000. Bits 15 to 6--Reserved: These bits always read 0. The write value should always be 0.
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Bits 5 and 4--Instruction Fetch/Data Access Select A (IDA1 and IDA0): These bits select whether to break channel A on instruction fetch and/or data access cycles.
Bit 5: IDA1 0 Bit 4: IDA0 0 1 1 0 1 Description No conditions compared value) Break on instruction fetch cycle Break on data access cycle Break on either instruction fetch or data access cycle (Initial
Bits 3 and 2--Read/Write Select A (RWA1 and RWA0): These bits select whether to break channel A on read and/or write cycles.
Bit 3: RWA1 0 Bit 2: RWA0 0 1 1 0 1 Description No conditions compared value) Break on read cycles Break on write cycles Break on both read and write cycles (Initial
Bits 1 and 0--Operand Size Select A (SZA1 and SZA0): These bits select the bus cycle operand size as a channel A break condition.
Bit 1: SZA1 0 Bit 0: SZA0 0 1 1 0 1 Description Operand size is not a break condition value) Break on byte access Break on word access Break on longword access (Initial
7.2.8
Break Bus Cycle Register B (BBRB)
BBRB is the break bus cycle register for channel B. The bit configuration is the same as for BBRA.
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7.2.9
Break Data Register B (BDRB)
Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: 31 BDB31 -- R/W 23 BDB23 -- R/W 15 BDB15 -- R/W 7 BDB7 -- R/W 30 BDB30 -- R/W 22 BDB22 -- R/W 14 BDB14 -- R/W 6 BDB6 -- R/W 29 BDB29 -- R/W 21 BDB21 -- R/W 13 BDB13 -- R/W 5 BDB5 -- R/W 28 BDB28 -- R/W 20 BDB20 -- R/W 12 BDB12 -- R/W 4 BDB4 -- R/W 27 BDB27 -- R/W 19 BDB19 -- R/W 11 BDB11 -- R/W 3 BDB3 -- R/W 26 BDB26 -- R/W 18 BDB18 -- R/W 10 BDB10 -- R/W 2 BDB2 -- R/W 25 BDB25 -- R/W 17 BDB17 -- R/W 9 BDB9 -- R/W 1 BDB1 -- R/W 24 BDB24 -- R/W 16 BDB16 -- R/W 8 BDB8 -- R/W 0 BDB0 -- R/W
Break data register B (BDRB) is a 32-bit read/write register that specifies the data that is the break condition for channel B data breaks. BDRB is not initialized by a reset. BDRB Bits 31 to 0--Break Data B31 to B0 (BDB31 to BDB0): These bits store the data that is the break condition for break channel B. When byte access has been specified by the SZB bit in the BBRB register, set the same byte data in bits BDB15-BDB8 as has been set in bits BDB7-BDB0. Bits BDB31-BDB16 are ignored when either byte or word access is specified. When the instruction fetch cycle is specified as a channel B break condition, or when the data bus is not included in the conditions according to the DBEB bit specification in BRCR (0), the BDRB value is ignored.
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7 . 2 . 1 0 Break Data Mask Register B (BDMRB)
Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: 31 BDM31 -- R/W 23 BDM23 -- R/W 15 BDM15 -- R/W 7 BDM7 -- R/W 30 BDM30 -- R/W 22 BDM22 -- R/W 14 BDM14 -- R/W 6 BDM6 -- R/W 29 BDM29 -- R/W 21 BDM21 -- R/W 13 BDM13 -- R/W 5 BDM5 -- R/W 28 BDM28 -- R/W 20 BDM20 -- R/W 12 BDM12 -- R/W 4 BDM4 -- R/W 27 BDM27 -- R/W 19 BDM19 -- R/W 11 BDM11 -- R/W 3 BDM3 -- R/W 26 BDM26 -- R/W 18 BDM18 -- R/W 10 BDM10 -- R/W 2 BDM2 -- R/W 25 BDM25 -- R/W 17 BDM17 -- R/W 9 BDM9 -- R/W 1 BDM1 -- R/W 24 BDM24 -- R/W 16 BDM16 -- R/W 8 BDM8 -- R/W 0 BDM0 -- R/W
Break data mask register B (BDMRB) is a 32-bit read/write register that determines which of the bits in the break address set in BDRB are masked. BDMRB is not initialized by a reset. BDMRB Bits 31 to 0--Break Data Mask B31 to B0 (BDMB31 to BDMB0): These bits specify whether bits B31-B0 (BDB31 to BDB0) of the channel B break data set in BDRB are masked. Set the same values in BDMB15-BDMB8 as are set in BDMB7-BDMB 0.
Bits 31-0: BDMBn 0 1 Description Channel B break data bit BDBn is included in the break condition. Channel B break data bit BDBn is masked and therefore not included in the break condition.
n = 31 to 0 Notes: 1. When the data bus value is contained in the break conditions, specify the operand size. 2. For byte data, set the same data in bits 0-7 and bits 8-15 of BDRB and BDMRB. 3. Bits 31-16 of BDRB and BDMRB are ignored for byte and word sizes.
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7 . 2 . 1 1 Break Control Register (BRCR)
Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: 15 CMFA 0 R/W 7 DBEB 0 R/W 14 CMFB 0 R/W 6 PCBB 0 R/W 13 -- 0 R 5 -- 0 R 12 -- 0 R 4 -- 0 R 11 -- 0 R 3 SEQ 0 R/W 10 PCBA 0 R/W 2 -- 0 R 9 -- 0 R 1 -- 0 R 8 -- 0 R 0 -- 0 R
The break control register (BRCR) is a 16-bit read/write register that controls user breaks. BRCR: 1. Determines whether to use channels A and B as two independent channels or as sequential conditions. 2. Selects whether to break before or after instruction execution during the instruction fetch cycle. 3. Determines whether to include the BDRB register in the channel B comparison conditions. It also has a condition-match flag. A power-on or manual reset initializes BRCR to H'0000. Bit 15--Condition Match Flag A (CMFA): Set to 1 when the break conditions set in channel A are met. Not cleared to 0. To check a flag setting after it has been set, clear it by writing 0.
Bit 15: CMFA 0 1 Description Channel A break conditions do not match. value) Channel A break conditions match. (Initial
Bit 14--Condition Match Flag B (CMFB): Set to 1 when the break conditions set in channel B are met. Not cleared to 0. To check a flag setting after it has been set, clear it by writing 0.
Bit 14: CMFB 0 1 Description Channel B break conditions do not match. value) Channel B break conditions match. (Initial
Bits 13 to 11--Reserved: These bits always read 0. The write value should always be 0.
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Bit 10--PC Break Select A (PCBA): Selects whether to place the channel A instruction fetch cycle break before or after instruction execution.
Bit 10: PCBA 0 Description Places the channel A PC break before instruction execution. (Initial value) Places the channel A PC break after instruction execution.
1
Bits 9 and 8--Reserved: These bits always read 0. The write value should always be 0. Bit 7--Data Break Enable B (DBEB): Selects whether to include data bus conditions in the channel B break conditions.
Bit 7: DBEB 0 Description Do not include data bus conditions in the channel B conditions. (Initial value) Include data bus conditions in the channel B conditions.
1
Note: When the data bus is not included in the break conditions, the IDB1 and IDB0 bits of break bus cycle register B (BBRB) should be 10 or 11.
Bit 6--PC Break Select B (PCBB): Selects whether to place the channel B instruction fetch cycle break before or after instruction execution
Bit 6: PCBB 0 Description Places the channel B PC break before instruction execution. (Initial value) Places the channel B PC break after instruction execution.
1
Bits 5 and 4--Reserved: These bits always read 0. The write value should always be 0. Bit 3--Sequence Condition Select (SEQ): Selects whether to handle the channel A and B conditions independently or sequentially. When set for sequential, the CMFB flag is set when the channel B condition is matched after the channel A condition has already been matched.
Bit 3: SEQ 0 1 Description Compare channel A and B conditions independently. value) (Initial
Compare channel A and B conditions sequentially (channel A, then channel B). 133
Bits 2 to 0--Reserved: These bits always read 0. The write value should always be 0.
7.3
7.3.1
UBC Operation
User Break Operation Flow
The flow from break condition setting to user break trap processing is as follows: 1. In the break conditions, set the break address in the break address register for the relevant channel (BARA or BARB), the ASID corresponding to the break space in the break ASID register (BASRA or BASRB), and the address and ASID masking method in the break address masking register (BAMRA or BAMRB). If the data bus value is included in the break conditions, set the break data in the break data register (BDRB) and the data mask in the break data mask register (BDMRB). 2. Set the break bus conditions in the break bus cycle register (BBRA or BBRB). If 00 is set for even one set out of BBRA/BBRB register instruction fetch/data access select and read/write select, a user trap break will not be generated in the corresponding channel. Set such specifications as pre- or post-execution in the case of instruction fetch, whether the data bus value is to be included in the conditions in the case of data access, and independent or sequential conditions for channels A and B, in the break control register (BRCR). Set the BBRA and BBRB registers only after all other break-related register settings have been completed. If break enabling is set with the BBRA and BBRB registers while the break address, data, mask, and other registers are still in their initial post-reset state, a break may occur inadvertently. 3. When a condition is matched, the condition match flag for the relevant channel (CMFA or CMFB) is set. This flag is set by a condition match but is not reset. To confirm setting of the same flag again, therefore, it should first be cleared to 0. 4. When sequential conditions are set, a break is made at the instruction matched by channel B when the channel B condition is matched after matching of the channel A condition. No break is made if the channel B set condition is matched before or at the same time as the channel A condition. With sequential conditions, the condition match flag is set only for channel B, and not for channel A.
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7.3.2
Instruction Fetch Cycle Break
1. Making an instruction fetch/read/word setting made in the break bus cycle register (BBRA/BBRB) enables an instruction fetch cycle to be set as a break condition. In this case, pre- or post-execution of the instruction can be selected by means of bit PCBA/PCBB in the break control register (BRCR). 2. When instructions are fetched consecutively, 32 bits (two instructions) are fetched in one bus cycle. In this case, although only one bus cycle is generated, breaks can be set for both instructions by setting the start addresses of the respective instructions in the break address registers (BARA and BARB). 3. With an instruction subject to a pre-execution break, the break is executed when it has been confirmed that the instruction has been fetched and is to be executed. Consequently, an overrunfetched instruction (an instruction fetched but not executed in the event of a branch or exception) cannot be subject to a break. If an exception when an instruction subject to a break is fetched, exception processing is performed first, and the break is executed only when the instruction is re-executed. Since a delayed branch instruction and delay slot instruction are executed as a single instruction, if a pre-execution condition is specified for the delay slot instruction, a break is made before execution of the delayed branch instruction. However, a pre-execution break condition cannot be specified for an RTE instruction delay slot instruction. 4. With a post-execution condition, the instruction set as the break condition is executed and a break trap is generated before the next instruction is executed. In the same way, a break cannot be specified for an overrun-fetch instruction. When a post-execution condition is set for a delayed branch instruction, similarly, the break is made after executing the delay slot and before executing the instruction at the branch destination. 5. When an instruction fetch cycle is set for channel B, break data register B (BDRB) is ignored. Therefore, break data need not be set for an instruction fetch cycle break. 6. Instruction fetch cycle breaks cannot be specified consecutively for a delayed branch instruction and its delay slot.
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7.3.3
Data Access Cycle Break
1. In the case of a data access cycle break, the bits used for comparison with the address bus depend on the break bus cycle register (BBRA/BBRB) operand size specification, as follows: Operand size Compared address Not included in conditions (00): For byte address, comparison with address bits A31-A0 For word address, comparison with address bits A31-A1 For longword address, comparison with address bits A31-A2 Byte (01): Comparison with address bits A31-A0 Word (10): Comparison with address bits A31-A1 Longword (11): Comparison with address bits A31-A2 2. When data value is included in break condition in channel B When the data value is included in the break conditions, set the DBEB bit in the break control register (BRCR) to 1. In this case, break data register B (BDRB) and break data mask register B (BDMRB) settings are needed in addition to the address condition. A user break trap is generated on a match of the address condition and the data condition. Bits IDB1 and IDB0 of break bus cycle register B (BBRB) should be set to 00 or 01. When byte data is specified, set the same data in the two bytes comprising bits 15-8 and bits 7-0 in break data register B (BDRB) and break mask register B (BDMRB). If word or byte is designated, bits 31-16 of BDRB and BDMRB are ignored.
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7.3.4
Saved Program Counter (PC) Value
1. When instruction fetch (pre-execution) is set as break condition The program counter (PC) value saved in the SPC in user break interrupt handling is the address of the instruction for which the break condition matched. In this case, the fetched instruction is not executed, due to the user break interrupt generated prior to its execution. In the fetch cycle of an instruction located in the delay slot of a delayed branch instruction, a break is generated before the branch, so that the SPC value indicates the delayed branch instruction. 2. When instruction fetch (post-execution) is set as break condition The program counter (PC) value saved in the SPC in user break interrupt processing is the address of the next instruction to be executed after the instruction for which the break condition matched. In this case, the fetched instruction is executed, and a user break trap occurs before execution of the next instruction. When a delayed branch instruction is designated, the delay slot instruction is executed and a user break occurs before execution of the instruction at the branch destination. In this case, the PC value saved in the SPC is the address of the branch destination instruction. 3. When data access (address only) is set as break condition The value saved is the address of the next instruction to be executed after the instruction for which the condition matched. The condition-matching instruction is executed, and a user break trap occurs before execution of the next instruction. 4. When data access (address + data ) is set as break condition The value saved is the start address of the next instruction after the instruction for which execution has been completed when user break trap processing is initiated. When a data value is set as a break condition, the point at which the break is to be made cannot be specified. A break is executed before execution of the instruction fetched around the time of the break data access. 7.3.5 Examples of Use
Register settings, set conditions, and states in which the set conditions are matched, are as follows: 1. Instruction fetch cycle break condition setting (independent channel A and B conditions) BRCR = H'0400: Independent channel A and B conditions, post-execution for channel A, preexecution for channel B Channel A: BASRA = H'80: BARA = H'00000404: BAMRA = H'00: BBRA = H'0014: ASID H'80 Address H'00000404 Address mask H'00 Bus cycle, instruction fetch (post-execution), read (operand size not included in conditions) ASID H'70 Address H'00008010
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Channel B:
BASRB = H'70: BARB = H'00008010:
Address mask H'02 Bus cycle, instruction fetch (pre-execution), read (operand size not included in conditions) BDRB = H'00000000: Data H'00000000 BDMRB = H'00000000: Data mask H'00000000 A user break is generated after execution of the instruction at address H'00000404 with ASID= H'80, or before execution of instructions at addresses H'00008000 to H'000083FE with ASID = H'70. 2. Instruction fetch cycle break condition setting (independent channel A and B conditions) BRCR = H'0080: Channel A channel B sequential conditions, pre-execution for channel A, pre-execution for channel B Channel A: BASRA = H'80: BARA = H'00037226: BAMRA = H'00: BBRA = H'0016: ASID H'80 Address H'00037226 Address mask H'00 Bus cycle, instruction fetch (pre-execution), read, word
BAMRB = H'02: BBRB = H'0014:
Channel B:
ASID H'70 Address H'0003722E Address mask H'00 Bus cycle, instruction fetch (pre-execution), read, word BDRB = H'00000000: Data H'00000000 BDMRB = H'00000000: Data mask H'00000000
BASRB = H'70: BARB = H'0003722E: BAMRB = H'00: BBRB = H'0016:
A user break is generated before execution of the instruction at address H'0003722E with ASID = H'70, after execution of the instruction at address H'00037226 with ASID = H'80. 3. Data access cycle break condition setting BRCR = H'0080: Independent channel A and B conditions, data break enable Channel A: BASRA = H'80: BARA = H'00123456: BAMRA = H'00: BBRA = H'0024: ASID H'80 Address H'00123456 Address mask H'00 Bus cycle, data access, read (operand size not included in conditions) ASID H'70 Address H'000ABCDE Address mask H'02 Bus cycle, data access, write, word Data H'0000A512, (data break enable) Data mask H'00000000
Channel B:
BASRB = H'70: BARB = H'000ABCDE: BAMRB = H'02: BBRB = H'002A: BDRB = H'0000A512: BDMRB = H'00000000:
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For channel A, a user break trap occurs when ASID = H'80 and a longword read is performed at address H'00123454, a word read is performed at address H'00123456, or a byte read is performed at address H'00123456. For channel B, a user break trap occurs when ASID = H'70 and H'A512 is written anywhere in addresses H'000AB000 to H'000ABFFE. 4. Instruction fetch cycle break condition setting (example of setting error) BRCR = H'0000: Independent channel A and B conditions, pre-execution for channel A, preexecution for channel B Channel A: BASRA = H'80: BARA = H'00027128 BAMRA = H'00: BBRA = H'001A: ASID H'80 Address H'00027128 Address mask H'00 Bus cycle, instruction fetch (pre-execution), write, word
Channel B:
BASRB = H'70: BARB = H'00031415 BAMRB = H'00: BBRB = H'0014:
ASID H'70 Address H'00031415 Address mask H'00 Bus cycle, instruction fetch (pre-execution), read, (operand size not included in conditions) BDRB = H'00000000: Data H'00000000 BDMRB = H'00000000: Data mask H'00000000
For channel A, a user break trap does not occur since an instruction fetch is not a write cycle. For channel B, a user break trap does not occur since an instruction fetch is performed on an even address. 7.3.6 Cautions
1. If pre-execution is specified for one channel and post-execution for the other for the same address, a pre-execution break will be generated but the condition match flag will be set for both channels. 2. Do not set consecutive PC breaks for a delayed branch instruction and a delay slot instruction. 3. If a PC break (post-execution condition) is set for the TRAPA instruction, the condition match flag will be set but a break will not be executed. The TRAP instruction will be processed correctly. 4. If data access (address + data) is set as a break condition, and an exception is generated by the instruction (including the delay slot for a delayed branch instruction) following that at which that break condition was matched, the condition match flag will be set but a break will not be executed. The exception generated after the break will be processed correctly.
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5. If data access (address + data) is set as a break condition, and the instruction following that at which that break condition was matched is a SLEEP instruction, the condition match flag will be set but a break will not be executed. The SLEEP instruction will be processed correctly. 6. If an instruction fetch (halt after execution) is set as a break condition, and a nonmaskable interrupt is detected at the instruction following that at which that break condition was matched, the condition match flag will be set but a break will not be executed. The nonmaskable interrupt will be processed correctly. 7. When a sequential break setting is made, a condition match occurs on a channel B match in a bus cycle after that in which a channel A match occurred. Therefore, a condition match will not be recognized if bus cycles occurring simultaneously in channel A and B are designated. Also, since the CPU has a pipeline structure, the order of instruction fetch and data access cycles is determined by the pipeline. With sequential conditions, therefore, the sequential conditions will be taken as being matched as long as the respective channel conditions match in the order in which the bus cycles occur. 8. With an emulator, the UBC is used on the emulator system side in order to implement the emulator's break functions. Consequently, no UBC functions can be used when an emulator is used.
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Section 8 Power-Down Modes
8.1 Overview
In the power-down modes, all CPU and some on-chip supporting module functions are halted. This lowers power consumption. 8.1.1 Power-Down Modes
The SH7708 Series have the following power-down modes: 1. 2. 3. 4. Sleep mode Standby mode Module standby function (TMU, RTC, and SCI on-chip supporting modules) Hardware standby mode (SH7708S, SH7708R only)
Table 8.1 shows the transition conditions for entering the modes from the program execution state, as well as the CPU and supporting module states in each mode and the procedures for canceling each mode.
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Table 8.1 Power-Down Modes
State Transition Conditions CPU On-Chip R e g - On-Chip Periphera E x t e r n a lCanceling C P G C P U i s t e r Memory l Modules P i n s Memory Procedure Halts Held Held (Register held) Halts Held Held (Register held) Run Held Refresh 1. Interrupt 2. Reset
Mode Sleep mode
Execute SLEEP Runs instruction with STBY bit cleared to 0 in STBCR
Standby Execute SLEEP Halts mode instruction with STBY bit set to 1 in STBCR Hardware Drive CA pin standby low mode
Halts*1
Held Selfrefresh
1. Interrupt 2. Reset
Halts Halts Held Held (Register held)
Halts*3
Held Selfrefresh
Power-on reset
Module Set MSTP bit of Runs Runs Held Held standby STBCR to 1
Specified module halts
*2
Refresh
1. Clear MSTP bit to 0 2. Reset
Notes: 1. The RTC still runs if the START bit in RCR2 is set to 1 (see section 12, Realtime Clock (RTC)). TMU still runs when output of the RTC is used as input to its counter (see section 11, Timer (TMU)). 2. Depends on the on-chip supporting module. TMU external pin: Held SCI external pin: Reset 3. The RTC still runs if the START bit in RCR2 is set to 1 (see section 12, Realtime Clock (RTC)). The TMU does not run.
8.1.2
Register Configuration
Table 8.2 shows the configuration of the control register for the power-down modes. Table 8.2 Register Configuration
Name Standby control register Abbreviation R / W STBCR R/W Initial ValueAddress H'00* Access Size
H'FFFFFF82 Byte
Note: Initialized by a power-on reset. In a manual reset, the register contents are retained.
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8.1.3
Pin Configuration
Table 8.3 lists the pins used for the power-down modes. Table 8.3 Pin Configuration
Processing Status 1 Pin (STATUS1) High Processing Status 0 Pin (STATUS0) I / O High Low Low High Low O Processor Operating Status Reset Sleep mode Standby mode Normal operation
Note: The "normal operation" status applies during refresh cycles even in sleep mode.
8.2
8.2.1
Register Description
Standby Control Register (STBCR)
The standby control register (STBCR) is an 8-bit read/write register that sets the power-down mode. STBCR is initialized to H'00 by a power-on reset. Always set bits 6-3 to 0 when writing to the STBCR register.
Bit: Bit name: Initial value: R/W: 7 STBY 0 R/W 6 -- 0 R 5 -- 0 R 4 -- 0 R 3 -- 0 R 2 MSTP2 0 R/W 1 MSTP1 0 R/W 0 MSTP0 0 R/W
Bit 7--Standby (STBY): Specifies transition to standby mode.
Bit 7: STBY 0 1 Description Executing SLEEP instruction puts the chip into sleep mode. value) Executing SLEEP instruction puts the chip into standby mode. (Initial
Bits 6 to 3--Reserved: These bits always read 0. The write value should always as 0.
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Bit 2--Module Standby 2 (MSTP2): Specifies halting the clock supply to the timer unit TMU (an on-chip supporting module). When the MSTP2 bit is set to 1, the supply of the clock to the TMU is halted.
Bit 2: MSTP2 0 1 Description TMU runs. value) Clock supply to TMU is halted. (Initial
Bit 1--Module Standby 1 (MSTP1): Specifies halting the clock supply to the realtime clock RTC (an on-chip supporting module). When the MSTP1 bit is set to 1, the supply of the clock to RTC is halted. When the clock halts, all RTC registers become inaccessible, but the counter keeps running.
Bit 1: MSTP1 0 1 Description RTC runs. value) Clock supply to RTC is halted. (Initial
Bit 0--Module Standby 0 (MSTP0): Specifies halting the clock supply to the serial communication interface SCI (an on-chip supporting module). When the MSTP0 bit is set to 1, the supply of the clock to the SCI is halted.
Bit 0: MSTP0 0 1 Description SCI operates. value) Clock supply to SCI is halted. (Initial
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8.3
8.3.1
Sleep Mode
Transition to Sleep Mode
Executing the SLEEP instruction when the STBY bit in STBCR is 0 causes a transition from the program execution state to sleep mode. Although the CPU halts immediately after executing the SLEEP instruction, the contents of its internal registers remain unchanged. The on-chip supporting modules continue to run during sleep mode and the clock continues to be output to the CKIO pin. In sleep mode, the STATUS1 pin is set high and the STATUS0 pin low. However, during a refresh cycle, the STATUS1 pin and STATUS0 pin are both set low. 8.3.2 Canceling Sleep Mode
Sleep mode is canceled by an interrupt (NMI, IRL, on-chip supporting module) or reset. Interrupts are accepted during sleep mode even when the BL bit in the SR register is 1. Canceling with an Interrupt: When an NMI, IRL or on-chip supporting module interrupt occurs, sleep mode is canceled and interrupt exception handling is executed. A code indicating the interrupt source is set in the INTEVT register. Canceling with a Reset: Sleep mode is canceled by a power-on reset or a manual reset.
8.4
8.4.1
Standby Mode
Transition to Standby Mode
To enter standby mode, set the STBY bit to 1 in STBCR, then execute the SLEEP instruction. The chip moves from the program execution state to standby mode. In standby mode, power consumption is greatly reduced by halting not only the CPU, but the clock and on-chip supporting modules as well. The clock output from the CKIO pin also halts. CPU and cache register contents are held, but some on-chip supporting modules are initialized. Table 8.4 lists the states of registers in standby mode.
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Table 8.4 Register States in Standby Mode
Module Interrupt controller Break controller Bus state controller On-chip clock pulse generator Timer unit Realtime clock Registers -- -- -- -- TSTR register -- Initialized Registers Retaining Data All registers All registers All registers All registers Registers other than TSTR All registers
The procedure for moving to standby mode is as follows: 1. Clear the TME bit in the WDT's timer control register (WTCSR) to 0 to stop the WDT. Set the WDT's timer counter (WTCNT) and the CKS2-CKS0 bits of the WTCSR register to appropriate values to secure the specified oscillation settling time. 2. When PLL circuit 1 is running in clock modes 3-6, clear the PSTBY and PLLEN bits in the frequency control register (FRQCR) to 0 to stop PLL circuit 1. 3. After the STBY bit in the STBCR register is set to 1, a SLEEP instruction is executed. 4. Standby mode is entered and the clocks within the chip are halted. The STATUS1 pin output goes low and the STATUS0 pin output goes high. 8.4.2 Canceling Standby Mode
Standby mode is canceled by an interrupt (NMI, IRL, or on-chip supporting module) or a reset. Canceling with an Interrupt: The on-chip WDT can be used for hot starts. When the chip detects an NMI, IRL,*1 or on-chip supporting module (except the interval timer)*2 interrupt, the clock will be supplied to the entire chip and standby mode canceled after the time set in the WDT's timer control/status register has elapsed. The STATUS1 and STATUS0 pins both go low. Interrupt handling then begins and a code indicating the interrupt source is set in the INTEVT register. Interrupts are accepted during standby mode even when the BL bit in the SR register is 1. Immediately after an interrupt is detected, the phase of the clock output of the CKIO pin may be unstable, until the processor starts interrupt handling. (The canceling condition is that the IRL3-IRL0 level is higher than the mask level in the I3-I0 bits in the SR register.) Notes: 1. When the RTC is being used, standby mode can be canceled using IRL3-IRL0. 2. Standby mode can be canceled with an RTC or TMU (only when running on the RTC clock) interrupt.
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Canceling with a Reset: Standby mode can be canceled with a reset (power-on or manual). Keep the RESET pin low until the clock oscillation settles. The internal clock will continue to be output to the CKIO pin. 8.4.3 Clock Pause Function
In standby mode, the clock input from the EXTAL pin or CKIO pin can be halted and the frequency can be changed. This function is used as follows: 1. Enter standby mode using the appropriate procedures. 2. Once standby mode is entered and the clock stopped within the chip, the STATUS1 pin output is low and the STATUS0 pin output is high. 3. Once the STATUS1 pin goes low and the STATUS0 pin goes high, the input clock is stopped or the frequency is changed. 4. When the frequency is changed, an NMI or IRL interrupt is input after the change. When the clock is stopped, the same interrupts are input after the clock is applied. 5. After the time set in the WDT has elapsed, the clock starts being applied internally within the chip, the STATUS1-STATUS0 pins both go low, interrupts are handled, and operation resumes.
8.5
8.5.1
Module Standby Function
Transition to Module Standby Function
Setting the standby control register MSTP2-MSTP0 bits to 1 halts the supply of clocks to the corresponding on-chip supporting modules. This function can be used to reduce the power consumption in sleep mode. The module standby function holds the status prior to halt of the external pins of the on-chip supporting modules. TMU external pins hold their status prior to the halt. SCI external pins go to the reset state. With a few exceptions, all registers hold their values.
Bit MSTP2 Value 0 1 MSTP1 0 1 MSTP0 0 1 Description TMU runs. Supply of clock to TMU is halted. Registers are initialized.*1 RTC runs. Supply of clock to RTC is halted. Register access is prohibited.*2 SCI operates. Supply of clock to SCI is halted.
Notes: 1. The registers initialized are the same as in standby mode (table 8.4). 2. The counter runs.
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8.5.2
Clearing the Module Standby Function
The module standby function can be cleared by clearing the MSTP2-MSTP0 bits to 0, or by a power-on reset or manual reset.
8.6
Timing of STATUS Pin Changes
The timing of STATUS1 and STATUS0 pin changes is shown in figures 8.1 through 8.9. The meaning of the STATUS descriptions is as follows: Reset: Sleep: Standby: Normal: HH (STATUS1 high, STATUS0 high) HL (STATUS1 high, STATUS0 low) LH (STATUS1 low, STATUS0 high) LL (STATUS1 low, STATUS0 low)
The meaning of the clock units is as follows: Bcyc: Pcyc: 8.6.1 Bus clock cycle Peripheral clock cycle
Timing for Resets
Power-On Reset (Clock Modes 0, 1, 2, and 7):
CKIO PLL settling time
RESET
STATUS
Normal 0 to 5 Bcyc
Reset 0 to 30 Bcyc
Normal
Figure 8.1
Power-On Reset (Clock Mode 0, 1, 2, and 7) STATUS Output
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Power-On Reset (Clock Modes 3 and 4):
CKIO RESET
STATUS
Normal 0 to 5 Bcyc
Reset 0 to 30 Bcyc
Normal
Figure 8.2 Manual Reset:
Power-On Reset (Clock Mode 3 and 4) STATUS Output
CKIO RESET
STATUS
Normal 0 Bcyc or more*
Reset 0 to 30 Bcyc
Normal
Note: During manual reset, STATUS becomes HH (reset) and the internal reset begins after waiting for the executing bus cycle to end.
Figure 8.3
Manual Reset STATUS Output
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8.6.2
Timing for Canceling Standbys
Standby to Interrupt:
Oscillation stops Interrupt request WDT overflow
CKIO WDT count STATUS Normal Standby Normal
Figure 8.4
Standby to Interrupt STATUS Output
Standby to Power-On Reset:
Oscillation stops Reset
CKIO RESET*
STATUS
Normal
Standby
*
Reset 0 to 30 Bcyc
Normal
0 to 10 Bcyc
Note: When standby mode is cleared with a power-on reset, the WDT does not count. Keep RESET low during the PLL's oscillation settling time. *: Undefined
Figure 8.5
Standby to Power-On Reset STATUS Output
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Standby to Manual Reset:
Oscillation stops Reset
CKIO RESET*
STATUS
Normal
Standby
Reset 0 to 20 Bcyc
Normal
Note: When standby mode is cleared with a manual reset, the WDT does not count. Keep RESET low during the PLL's oscillation settling time.
Figure 8.6 8.6.3
Standby to Manual Reset STATUS Output
Timing for Canceling Sleep Mode
Sleep to Interrupt:
Interrupt request
CKIO
STATUS
Normal
Sleep
Normal
Figure 8.7
Sleep to Interrupt STATUS Output
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Sleep to Power-On Reset:
Reset
CKIO RESET*
STATUS
Normal
Sleep
*
Reset 0 to 30 Bcyc
Normal
0 to 10 Bcyc
Note: When the PLL1's multiplication ratio is changed by a power-on reset, keep RESET low during the PLL's oscillation settling time. *: Undefined
Figure 8.8 Sleep to Manual Reset:
Sleep to Power-On Reset STATUS Output
Reset CKIO RESET*
STATUS
Normal
Sleep 0 to 30 Bcyc
Reset 0 to 30 Bcyc
Normal
Note: Keep RESET low until the STATUS becomes reset.
Figure 8.9
Sleep to Manual Reset STATUS Output
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8.7
Hardware Standby Mode
The hardware standby mode is provided only in the SH7708S and SH7708R. This mode is not supported in emulator. 8.7.1 Transition to Hardware Standby Mode
Driving the CA pin low causes a transition to hardware standby mode. In hardware standby mode, all modules except those operating on an RTC clock are halted, as in the standby mode entered on execution of a SLEEP instruction. Hardware standby mode differs from standby mode as follows. 1. 2. 3. 4. Interrupts and manual resets are not accepted. The TCLK clock output is fixed low. The TMU does not operate. The RTC continues to operate even if power is not supplied to power supply pins other than those for RTC power. In this case, all output pins go to the non-drive state.
Operation when a low-level signal is input at the CA pin depends on the CPG state, as follows. 1. In standby mode The clock remains stopped and the chip enters the hardware standby state. Acceptance of interrupts and manual resets is disabled, TCLK output is fixed low, and the TMU halts. 2. During WDT operation when standby mode is canceled by an interrupt The chip enters hardware standby mode after standby mode is canceled and the CPU resumes operation. 3. In sleep mode The chip enters hardware standby mode after sleep mode is canceled and the CPU resumes operation. 4. During PLL standby (see section 9.6 for the PLL standby function) The chip enters hardware standby mode after forced implementation of the PLL OFF state. Hold the CA pin low in hardware standby mode.
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8.7.2
Canceling Hardware Standby Mode
Hardware standby mode can only be canceled by a power-on reset. When the CA pin is driven high while the RESET pin is low and the BREQ pin is high, clock oscillation is started. Hold the RESET pin low until clock oscillation stabilizes. When the RESET pin is driven high, the CPU begins power-on reset processing. Hardware standby mode cannot be canceled by an interrupt or manual reset. 8.7.3 Hardware Standby Mode Timing
Figures 8.10 and 8.11 show examples of pin timing in hardware standby mode. The CA pin is sampled using EXTAL2 (32.768 kHz), and a hardware standby request is only recognized when the pin is low for two consecutive clock cycles. The CA pin must be held low while the chip is in hardware standby mode. Clock oscillation starts when the CA pin is driven high after the RESET pin is driven low.
CKIO
CA RESET
STATUS
Normal 2 Rcyc or more
Standby
Undefined
Reset
0 to 10 Bcyc
Rcyc: EXTAL2 (32.768 kHz) cycle
Figure 8.10
Hardware Standby Mode Timing (When CA Goes Low in Normal Operation)
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CKIO
CA RESET
STATUS
Standby
Normal
Standby
Undefined
Reset
WDT operation 2 Rcyc or more
0 to 10 Bcyc
Figure 8.11
Hardware Standby Mode Timing (When CA Goes Low during WDT Operation on Standby Mode Cancellation)
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Section 9 On-Chip Oscillation Circuits
9.1 Overview
The clock pulse generator (CPG) supplies all clocks to the processor and controls the power-down modes. The watchdog timer (WDT) is a single-channel timer that counts the clock settling time and is used when clearing standby mode and temporary standbys, such as frequency changes. It can also be used as an ordinary watchdog timer or interval timer. 9.1.1 Features
The CPG has the following features: * Six clock modes: Selection of six clock modes for different frequency ranges, power consumption, direct crystal input, and external clock input. * Three clocks generated independently: An internal clock for the CPU, cache, and TLB (I); a peripheral clock (P) for the on-chip supporting modules; and a bus clock (CKI0) for the external bus interface. * Frequency change function: Internal and peripheral clock frequencies can be changed independently using the PLL circuit and divider circuit within the CPG. Frequencies are changed by software using frequency control register (FRQCR) settings. * PLL on/off function: Power consumption can be decreased by stopping the PLL circuit when operating at low frequencies. * Power-down mode control: The clock can be stopped for sleep mode and standby mode and specific modules can be stopped using the module standby function. The WDT has the following features: * Can be used to ensure the clock settling time: Use the WDT to cancel standby mode and the temporary standbys which occur when the clock frequency is changed. * Can switch between watchdog timer mode and interval timer mode. * Generates internal resets in watchdog timer mode: Internal resets occur after counter overflow. Selection of power-on reset or manual reset. * Generates interrupts in interval timer mode: Internal timer interrupts occur after counter overflow. * Selection of eight counter input clocks. Eight clocks (x1 to x1/4096) can be obtained by dividing the peripheral clock.
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9.2
9.2.1
Overview of the CPG
CPG Block Diagram
A block diagram of the on-chip clock pulse generator is shown in figure 9.1(SH7708, SH7708S) and figure 9.2(SH7708R).
Clock pulse generator CAP1 PLL circuit 1 (x 1, 2, 4) CKIO Cycle = Bcyc CAP2 XTAL EXTAL Crystal oscillator Divider 2 x1 x 1/2 x 1/4 Divider 1 x1 x 1/2 x 1/4
Internal clock (I) Cycle = Icyc
PLL circuit 2 (x 1, 4)
Peripheral clock (P) Cycle = Pcyc
CPG control unit Clock frequency control circuit Standby control circuit Standby control
MD2 MD1 MD0
FRQCR
STBCR
Bus interface
Internal bus FRQCR: Frequency control register STBCR: Standby control register
Figure 9.1
Block Diagram of Clock Pulse Generator(SH7708, SH7708S)
158
Clock pulse generator CAP1 PLL circuit 1 (x 1, 2, 3,4) CKIO Cycle = Bcyc CAP2 XTAL EXTAL Crystal oscillator Divider 2 x1 x 1/2 x 1/3 x 1/4 Divider 1 x1 x 1/2 x 1/3 x 1/4
Internal clock (I) Cycle = Icyc
PLL circuit 2 (x 1, 4)
Peripheral clock (P) Cycle = Pcyc
CPG control unit Clock frequency control circuit Standby control circuit Standby control
MD2 MD1 MD0
FRQCR
STBCR
Bus interface
Internal bus FRQCR: Frequency control register
Figure 9.2
Block Diagram of Clock Pulse Generator(SH7708R)
The clock pulse generator blocks function as follows: 1. PLL Circuit 1: PLL circuit 1 doubles, triples*, quadruples, or leaves unchanged the input clock frequency from the CKIO terminal. The multiplication rate is set by the frequency control register. When this is done, the phase of the leading edge of the internal clock is controlled so that it will agree with the phase of the leading edge of the CKIO pin. Note: SH7708R only 2. PLL Circuit 2: PLL circuit 2 leaves unchanged or quadruples the frequency of the crystal oscillator or the input clock frequency coming from the EXTAL pin. The multiplication ratio
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is fixed by the clock operation mode. The clock operation mode is set by pins MD0, MD1, and MD2. See table 9.3 for more information on clock operation modes. 3. Crystal Oscillator: This oscillator is used when a crystal oscillator element is connected to the XTAL and EXTAL pins. It operates according to the clock operating mode setting. 4. Divider 1: Divider 1 generates a clock at the operating frequency used by the internal clock. The operating frequency can be 1, 1/2, 1/3*, or 1/4 times the output frequency of PLL circuit 1, as long as it stays at or above the clock frequency of the CKIO pin. The division ratio is set in the frequency control register. Note: SH7708R only 5. Divider 2: Divider 2 generates a clock at the operating frequency used by the peripheral clock. The operating frequencies can be 1, 1/2, 1/3*, or 1/4 times the output frequency of PLL Circuit 1 or the clock frequency of the CKIO pin, as long as it stays at or below the clock frequency of the CKIO pin. The division ratio is set in the frequency control register. Note: SH7708R only 6. Clock Frequency Control Circuit: The clock frequency control circuit controls the clock frequency using the MD pin and the frequency control register. 7. Standby Control Circuit: The standby control circuit controls the status of the clock pulse generator and other modules during clock switching and sleep/standby modes. 8. Frequency Control Register: The frequency control register has control bits assigned for the following functions: clock output/non-output from the CKIO pin, on/off control of PLL circuit 1, PLL standby, the frequency multiplication ratio of PLL 1, and the frequency division ratio of the internal clock and the peripheral clock. 9. Standby Control Register: The standby control register has bits for controlling the power-down modes. See section 8, Power-Down Modes, for more information.
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9.2.2
CPG
Pin Configuration
Table 9.1 lists the CPG pins and their functions. Table 9.1 Clock Pulse Generator Pins and Functions
Pin Name Mode control pins Symbol MD0 MD1 MD2 Crystal I/O pins (clock input pins) XTAL EXTAL CKIO CAP1 CAP2 I / O Description I I I O I I/O I I Connects a crystal oscillator. Connects a crystal oscillator. Also used to input an external clock. Inputs or outputs an external clock. Level can be fixed during output. Connects capacitor for PLL circuit 1 operation (recommended value 470 pF). Connects capacitor for PLL circuit 2 operation (recommended value 470 pF). Set the clock operating mode.
Clock I/O pin Capacitor connection pins for PLL
9.2.3
CPG
Register Configuration
Table 9.2 shows the CPG register configuration. Table 9.2 Register Configuration
Register Name Frequency control register Abbreviatio n FRQCR R/W R/W Initial Value* H'0102 Address H'FFFFFF80 Access Size 16
Note: Initialized by a power-on reset via the RESET pin. Register contents are retained in a poweron reset initiated by the WDT.
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9.3
Clock Operating Modes
Table 9.3 shows the relationship between the mode control pin (MD2-MD0) combinations and the clock operating modes. Table 9.4 shows the usable frequency ranges in the clock operating modes. Table 9.3 Clock Operating Modes
Pin Values Mod M D M D M D e 2 1 0 0 0 0 0 Divider Divider C K I O 1 2 S o u r c e Ou tp ut O n / O f f ider 3 O n / O f f I n p u t Input Frequenc y EXTAL CKIO Off On multiplication ratio: 1 Off On multiplication ratio: 4 Off On multiplication ratio: 4 Off On multiplication ratio: 1 ON PLL1 output PLL1 (EXTAL) Clock I/O PLL2 DivPLL1
1
0
0
1
EXTAL CKIO
ON
PLL1 output
PLL1
(EXTAL) x4
2
0
1
0
Crystal CKIO oscillato r EXTAL CKIO
On
PLL1 output
PLL1
(Crystal) x4
3
0
1
1
Off (initial value) On
PLL2 output
PLL2
(EXTAL) x1
PLL1 output PLL2 output PLL2 (Crystal) x1
4
1
0
0
Crystal CKIO oscillato r
Off On multiplication ratio: 1
Off (initial value) On
PLL1 output PLL1 output PLL1 (CKIO)
7
1
1
1
CKIO
--
Off
Off
On
Mode 0: An external clock is input from the EXTAL pin and undergoes waveform shaping by PLL circuit 2 before being supplied inside the SH7708 Series. PLL circuit 1 is constantly on, and there are no frequency range restrictions compared to mode 3. An input clock frequency of 8 MHz to 60 MHz(SH7708, SH7708S) or 16 MHz to 60 MHz(SH7708R) can be used, and the CKIO frequency range is 8 MHz to 60 MHz(SH7708, SH7708S) or 16 MHz to 60 MHz(SH7708R).
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As PLL circuit 1 compensates for fluctuations in the CKIO pin load, this mode is suitable for connection of synchronous DRAM. Mode 1: An external clock is input from the EXTAL pin and its frequency is multiplied by 4 by PLL circuit 2 before being supplied inside the SH7708 Series, allowing a low-frequency external clock to be used. An input clock frequency of 5 MHz to 15 MHz can be used, and the CKIO frequency range is 20 MHz to 60 MHz. As PLL circuit 1 compensates for fluctuations in the CKIO pin load, this mode is suitable for connection of synchronous DRAM. Mode 2: The on-chip crystal oscillator operates, with the oscillation frequency being multiplied by 4 by PLL circuit 2 before being supplied inside the SH7708 Series, allowing a low crystal frequency to be used. A crystal oscillation frequency of 5 MHz to 15 MHz can be used, and the CKIO frequency range is 20 MHz to 60 MHz. As PLL circuit 1 compensates for fluctuations in the CKIO pin load, this mode is suitable for connection of synchronous DRAM. Mode 3: An external clock is input from the EXTAL pin and undergoes waveform shaping by PLL circuit 2 before being supplied inside the SH7708 Series. PLL circuit 1 is off in the default state at power-on reset, and PLL circuit 1 can be selected as on or off, enabling power consumption to be kept lower than in mode 0. An input clock frequency of 8 MHz to 15 MHz(SH7708, SH7708S) or 16 MHz to 25 MHz(SH7708R) can be used, and the CKIO frequency range is of 8 MHz to 15 MHz(SH7708, SH7708S) or 16 MHz to 25 MHz(SH7708R). Mode 4: The on-chip crystal oscillator operates, with its output supplied inside the SH7708 Series as a square waveform by PLL circuit 2. PLL circuit 1 is off in the default state at power-on reset, and PLL circuit 1 can be selected as on or off, enabling power consumption to be reduced accordingly. A crystal oscillation frequency of of 8 MHz to 15 MHz(SH7708, SH7708S) or 16 MHz to 25 MHz(SH7708R) can be used, and the CKIO frequency range is of 8 MHz to 15 MHz(SH7708, SH7708S) or 16 MHz to 25 MHz(SH7708R). Mode 7: In this mode, the CKIO pin is an input, an external clock is input to this pin, and undergoes waveform shaping, and also frequency multiplication according to the setting, by PLL circuit 1 before being supplied to the SH7708 Series. In modes 0 to 6, the system clock is generated from the output of the SH7708 Series' CKIO pin. Consequently, if a large number of ICs are operating on the clock cycle, the CKIO pin load will be large. This mode, however, assumes a comparatively large-scale system. If a large number of ICs are operating on the clock cycle, a clock generator with a number of low-skew clock outputs can be provided, so that the ICs can operate synchronously by distributing the clocks to each one. As PLL circuit 1 compensates for fluctuations in the CKIO pin load, this mode is suitable for connection of synchronous DRAM.
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Table 9.4 Range of Usable Frequencies for Each Clock Operating Mode(SH7708, SH7708S)
FRQCR Register Mode V a l u e PLL1 0 H'0102 H'0101 H'0100 H'0112 H'0111 H'0115 H'0116 H'0122 H'0126 H'012a 1, 2 H'0102 H'0101 H'0100 H'0112 H'0111 H'0115 H'0116 3, 4 H'0102 H'0101 H'0100 H'01d1 H'01d0 H'01d4 H'01d5 H'01d6 H'01e0 H'01e4 H'01e5 H'01e8 H'01e9 H'01ea ON (x 1) ON (x 1) ON (x 1) ON (x 2) ON (x 2) ON (x 2) ON (x 2) ON (x 4) ON (x 4) ON (x 4) ON (x 1) ON (x 1) ON (x 1) ON (x 2) ON (x 2) ON (x 2) ON (x 2) OFF OFF OFF ON (x 2) ON (x 2) ON (x 2) ON (x 2) ON (x 2) ON (x 4) ON (x 4) ON (x 4) ON (x 4) ON (x 4) ON (x 4) Clock Ratio* 1 (I:B:P) 1:1:1/4 1:1:1/2 1:1:1 2:1:1/2 2:1:1 1:1:1 1:1:1/2 4:1:1 2:1:1 1:1:1 4:4:1 4:4:2 4:4:4 8:4:2 8:4:4 4:4:4 4:4:2 1:1:1/4 1:1:1/2 1:1:1 2:1:1/2 2:1:1 1:1:1 1:1:1/2 1:1:1/4 4:1:4 2:1:1 2:1:1/2 1:1:1 1:1:1/2 1:1:1/4 Input Clock/ Crystal Oscillator CKIO Pin Frequency Range Frequency Range 8 MHz to 60 MHz 8 MHz to 60 MHz 8 MHz to 30 MHz 8 MHz to 30 MHz 8 MHz to 30 MHz 8 MHz to 30 MHz 8 MHz to 30 MHz 8 MHz to 15 MHz 8 MHz to 15 MHz 8 MHz to 15 MHz 5 MHz to 15 MHz 5 MHz to 15 MHz 5 MHz to 7.5 MHz 5 MHz to 7.5 MHz 5 MHz to 7.5 MHz 5 MHz to 7.5 MHz 5 MHz to 7.5 MHz 8 MHz to 15 MHz 8 MHz to 15 MHz 8 MHz to 15 MHz 8 MHz to 15 MHz 8 MHz to 15 MHz 8 MHz to 15 MHz 8 MHz to 15 MHz 8 MHz to 15 MHz 8 MHz to 15 MHz 8 MHz to 15 MHz 8 MHz to 15 MHz 8 MHz to 15 MHz 8 MHz to 15 MHz 8 MHz to 15 MHz 8 MHz to 60 MHz 8 MHz to 60 MHz 8 MHz to 30 MHz 8 MHz to 30 MHz 8 MHz to 30 MHz 8 MHz to 30 MHz 8 MHz to 30 MHz 8 MHz to 15 MHz 8 MHz to 15 MHz 8 MHz to 15 MHz 20 MHz to 60 MHz 20 MHz to 60 MHz 20 MHz to 30 MHz 20 MHz to 30 MHz 20 MHz to 30 MHz 20 MHz to 30 MHz 20 MHz to 30 MHz 8 MHz to 15 MHz 8 MHz to 15 MHz 8 MHz to 15 MHz 8 MHz to 15 MHz 8 MHz to 15 MHz 8 MHz to 15 MHz 8 MHz to 15 MHz 8 MHz to 15 MHz 8 MHz to 15 MHz 8 MHz to 15 MHz 8 MHz to 15 MHz 8 MHz to 15 MHz 8 MHz to 15 MHz 8 MHz to 15 MHz
PLL2 ON (x 1) ON (x 1) ON (x 1) ON (x 1) ON (x 1) ON (x 1) ON (x 1) ON (x 1) ON (x 1) ON (x 1) ON (x 4) ON (x 4) ON (x 4) ON (x 4) ON (x 4) ON (x 4) ON (x 4) ON (x 1) ON (x 1) ON (x 1) ON (x 1) ON (x 1) ON (x 1) ON (x 1) ON (x 1) ON (x 1) ON (x 1) ON (x 1) ON (x 1) ON (x 1) ON (x 1)
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Table 9.4 Range of Usable Frequencies for Each Clock Operating Mode(SH7708, SH7708S) (cont)
FRQCR Register Mode V a l u e PLL1 5*
2
PLL2 OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF
Clock Ratio* 1 (I:B:P) 1/2:1/2:1/8 1/2:1/2:1/4 1/2:1/2:1/2 1:1/2:1/4 1:1/2:1/2 1/2:1/2:1/2 1/2:1/2:1/4 1/2:1/2:1/8 2:1/2:1/2 1:1/2:1/2 1/2:1/2:1/2 1/2:1/2:1/8 1/2:1/2:1/4 1/2:1/2:1/2 1:1/2:1/4 1:1/2:1/2 1/2:1/2:1/2 1/2:1/2:1/4 1/2:1/2:1/8 2:1/2:1/2 1:1/2:1/2 1/2:1/2:1/2 1:1:1/4 1:1:1/2 1:1:1 2:1:1/2 2:1:1 1:1:1 1:1:1/2 4:1:1 2:1:1 1:1:1
Input Clock/ Crystal Oscillator CKIO Pin Frequency Range Frequency Range 2 MHz to 30 MHz 2 MHz to 30 MHz 2 MHz to 30 MHz 16 MHz to 30 MHz 16 MHz to 30 MHz 16 MHz to 30 MHz 16 MHz to 30 Mhz 16 MHz to 30 MHz 16 MHz to 30 MHz 16 MHz to 30 MHz 16 MHz to 30 MHz 2 MHz to 20 MHz 2 MHz to 20 MHz 2 MHz to 20 MHz 16 MHz to 20 MHz 16 MHz to 20 MHz 16 MHz to 20 MHz 16 MHz to 20 MHz 16 MHz to 20 MHz 16 MHz to 20 MHz 16 MHz to 20 MHz 16 MHz to 20 MHz 8 MHz to 60 MHz 8 MHz to 60 MHz 8 MHz to 30 MHz 8 MHz to 30 MHz 8 MHz to 30 MHz 8 MHz to 30 MHz 8 MHz to 30 MHz 8 MHz to 15 MHz 8 MHz to 15 MHz 8 MHz to 15 MHz 1 MHz to 15 MHz 1 MHz to 15 MHz 1 MHz to 15 MHz 8 MHz to 15 MHz 8 MHz to 15 MHz 8 MHz to 15 MHz 8 MHz to 15 Mhz 8 MHz to 15 MHz 8 MHz to 15 MHz 8 MHz to 15 MHz 8 MHz to 15 MHz 1 MHz to 10 MHz 1 MHz to 10 MHz 1 MHz to 10 MHz 8 MHz to 10 MHz 8 MHz to 10 MHz 8 MHz to 10 MHz 8 MHz to 10 Mhz 8 MHz to 10 MHz 8 MHz to 10 MHz 8 MHz to 10 MHz 8 MHz to 10 MHz 8 MHz to 60 MHz 8 MHz to 60 MHz 8 MHz to 30 MHz 8 MHz to 30 MHz 8 MHz to 30 MHz 8 MHz to 30 MHz 8 MHz to 30 MHz 8 MHz to 15 MHz 8 MHz to 15 MHz 8 MHz to 15 MHz
H'0102 H'0101 H'0100 H'01d1 H'01d0 H'01d4 H'01d5 H'01d6 H'01e2 H'01e6 H'01ea
OFF OFF OFF ON (x 2) ON (x 2) ON (x 2) ON (x 2) ON (x 2) ON (x 4) ON (x 4) ON (x 4) OFF OFF OFF ON (x 2) ON (x 2) ON (x 2) ON (x 2) ON (x 2) ON (x 4) ON (x 4) ON (x 4) ON (x 1) ON (x 1) ON (x 1) ON (x 2) ON (x 2) ON (x 2) ON (x 2) ON (x 4) ON (x 4) ON (x 4)
6*
2
H'0102 H'0101 H'0100 H'01d1 H'01d0 H'01d4 H'01d5 H'01d6 H'01e2 H'01e6 H'01ea
7
H'0102 H'0101 H'0100 H'0112 H'0111 H'0115 H'0116 H'0122 H'0126 H'012a
Notes: 1. Taking input clock as 1. Maximum frequencies: Io = 60 MHz, Bo = 60 MHz, Po = 30 MHz. 2. Modes 5 and 6 are available only in the SH7708. 165
Table 9.5 Range of Usable Frequencies for Each Clock Operating Mode(SH7708R)
Clock Mode FRQCR 0 H'0100 H'0101 H'0102 H'0111 H'0112 H'0115 H'0116 H'0122 H'0126 H'012A H'A100 H'E100 H'E101 1, 2 H'0100 H'0101 H'0102 H'0111 H'0112 H'0115 H'0116 H'A100 H'E100 H'E101 3 H'0100 H'0101 H'0102 H'01D0 H'01D1 H'01D2 H'01D4 H'01D5 H'01D6 Clock Rate*1 (I:B:P) 1:1:1 1:1:1/2 1:1:1/4 2:1:1 2:1:1/2 1:1:1 1:1:1/2 4:1:1 2:1:1 1:1:1 3:1:1 1:1:1 1:1:1/2 4:4:4 4:4:2 4:4:1 8:4:4 8:4:2 4:4:4 4:4:2 12:4:4 4:4:4 4:4:2 1:1:1 1:1:1/2 1:1:1/4 2:1:1 2:1:1/2 2:1:1/4 1:1:1 1:1:1/2 1:1:1/4 Input Frequency CKIO Frequency Range Range 16 MHz to 33.3 MHz 16 MHz to 33.3 MHz 16 MHz to 60 MHz 16 MHz to 60 MHz 16 MHz to 60 Mhz 16 MHz to 60 Mhz 16 MHz to 33.3 MHz 16 MHz to 50 MHz 16 MHz to 33.3 MHz 16 MHz to 50 MHz 16 MHz to 25 MHz 16 MHz to 25 MHz 16 MHz to 25 MHz 16 MHz to 33.3 MHz 16 MHz to 50 MHz 16 MHz to 33.3 MHz 16 MHz to 50 MHz 16 MHz to 25 MHz 16 MHz to 25 MHz 16 MHz to 25 MHz
PLL1 ON (x 1) ON (x 1) ON (x 1) ON (x 2) ON (x 2) ON (x 2) ON (x 2) ON (x 4) ON (x 4) ON (x 4) ON (x 3) ON (x 3) ON (x 3) ON (x 1) ON (x 1) ON (x 1) ON (x 2) ON (x 2) ON (x 2) ON (x 2) ON (x 3) ON (x 3) ON (x 3) OFF OFF OFF ON (x 2) ON (x 2) ON (x 2) ON (x 2) ON (x 2) ON (x 2)
PLL2 ON (x 1) ON (x 1) ON (x 1) ON (x 1) ON (x 1) ON (x 1) ON (x 1) ON (x 1) ON (x 1) ON (x 1) ON (x 1) ON (x 1) ON (x 1) ON (x 4) ON (x 4) ON (x 4) ON (x 4) ON (x 4) ON (x 4) ON (x 4) ON (x 4) ON (x 4) ON (x 4) ON (x 1) ON (x 1) ON (x 1) ON (x 1) ON (x 1) ON (x 1) ON (x 1) ON (x 1) ON (x 1)
25 MHz to 33.3 MHz 25 MHz to 33.3 MHz 25 MHz to 33.3 MHz 25 MHz to 33.3 MHz 25 MHz to 33.3 MHz 25 MHz to 33.3 MHz 5 MHz to 8.3 MHz 5 MHz to 15 MHz 5 MHz to 15 MHz 5 MHz to 8.3 MHz 5 MHz to 12.5 MHz 5 MHz to 8.3 MHz 5 MHz to 12.5 MHz 5 MHz to 8.3 MHz 5 MHz to 8.3 MHz 5 MHz to 8.3 MHz 16 MHz to 25 MHz 16 MHz to 25 MHz 16 MHz to 25 MHz 16 MHz to 25 MHz 16 MHz to 25 MHz 16 MHz to 25 MHz 16 MHz to 25 MHz 16 MHz to 25 MHz 16 MHz to 25 MHz 20 MHz to 33.3 MHz 20 MHz to 60 MHz 20 MHz to 60 MHz 20 MHz to 33.3 MHz 20 MHz to 50 MHz 20 MHz to 33.3 MHz 20 MHz to 50 MHz 20 MHz to 33.3 MHz 20 MHz to 33.3 MHz 20 MHz to 33.3 MHz 16 MHz to 25 MHz 16 MHz to 25 MHz 16 MHz to 25 MHz 16 MHz to 25 MHz 16 MHz to 25 MHz 16 MHz to 25 MHz 16 MHz to 25 MHz 16 MHz to 25 MHz 16 MHz to 25 MHz
166
Table 9.5 Range of Usable Frequencies for Each Clock Operating Mode(SH7708R) (cont)
Clock Mode FRQCR 3 H'81C0 H'81C1 H'C1C0 H'C1C1 H'01E0 H'01E1 H'01E4 H'01E5 H'01E6 H'01E8 H'01E9 H'01EA 4 H'0100 H'0101 H'0102 H'01D0 H'01D1 H'01D2 H'01D4 H'01D5 H'01D6 H'81C0 H'81C1 H'C1C0 H'C1C1 H'01E0 H'01E1 H'01E4 H'01E5 H'01E6 H'01E8 H'01E9 H'01EA Clock Rate*1 (I:B:P) 3:1:1 3:1:1/2 1:1:1 1:1:1/2 4:1:1 4:1:1/2 2:1:1 2:1:1/2 2:1:1/4 1:1:1 1:1:1/2 1:1:1/4 1:1:1 1:1:1/2 1:1:1/4 2:1:1 2:1:1/2 2:1:1/4 1:1:1 1:1:1/2 1:1:1/4 3:1:1 3:1:1/2 1:1:1 1:1:1/2 4:1:1 4:1:1/2 2:1:1 2:1:1/2 2:1:1/4 1:1:1 1:1:1/2 1:1:1/4 Input Frequency CKIO Frequency Range Range 16 MHz to 25 MHz 16 MHz to 25 MHz 16 MHz to 25 MHz 16 MHz to 25 MHz 16 MHz to 25 MHz 16 MHz to 25 MHz 16 MHz to 25 MHz 16 MHz to 25 MHz 16 MHz to 25 MHz 16 MHz to 25 MHz 16 MHz to 25 MHz 16 MHz to 25 MHz 16 MHz to 20 MHz 16 MHz to 20 MHz 16 MHz to 20 MHz 16 MHz to 20 MHz 16 MHz to 20 MHz 16 MHz to 20 MHz 16 MHz to 20 MHz 16 MHz to 20 MHz 16 MHz to 20 MHz 16 MHz to 20 MHz 16 MHz to 20 MHz 16 MHz to 20 MHz 16 MHz to 20 MHz 16 MHz to 20 MHz 16 MHz to 20 MHz 16 MHz to 20 MHz 16 MHz to 20 MHz 16 MHz to 20 MHz 16 MHz to 20 MHz 16 MHz to 20 MHz 16 MHz to 20 MHz 16 MHz to 25 MHz 16 MHz to 25 MHz 16 MHz to 25 MHz 16 MHz to 25 MHz 16 MHz to 25 MHz 16 MHz to 25 MHz 16 MHz to 25 MHz 16 MHz to 25 MHz 16 MHz to 25 MHz 16 MHz to 25 MHz 16 MHz to 25 MHz 16 MHz to 25 MHz 16 MHz to 20 MHz 16 MHz to 20 MHz 16 MHz to 20MHz 16 MHz to 20 MHz 16 MHz to 20 MHz 16 MHz to 20 MHz 16 MHz to 20 MHz 16 MHz to 20 MHz 16 MHz to 20 MHz 16 MHz to 20 MHz 16 MHz to 20 MHz 16 MHz to 20 MHz 16 MHz to 20 MHz 16 MHz to 20 MHz 16 MHz to 20 MHz 16 MHz to 20 MHz 16 MHz to 20 MHz 16 MHz to 20 MHz 16 MHz to 20 MHz 16 MHz to 20 MHz 16 MHz to 20 MHz
PLL1 ON (x 3) ON (x 3) ON (x 3) ON (x 3) ON (x 4) ON (x 4) ON (x 4) ON (x 4) ON (x 4) ON (x 4) ON (x 4) ON (x 4) OFF OFF OFF ON (x 2) ON (x 2) ON (x 2) ON (x 2) ON (x 2) ON (x 2) ON (x 3) ON (x 3) ON (x 3) ON (x 3) ON (x 4) ON (x 4) ON (x 4) ON (x 4) ON (x 4) ON (x 4) ON (x 4) ON (x 4)
PLL2 ON (x 1) ON (x 1) ON (x 1) ON (x 1) ON (x 1) ON (x 1) ON (x 1) ON (x 1) ON (x 1) ON (x 1) ON (x 1) ON (x 1) ON (x 1) ON (x 1) ON (x 1) ON (x 1) ON (x 1) ON (x 1) ON (x 1) ON (x 1) ON (x 1) ON (x 1) ON (x 1) ON (x 1) ON (x 1) ON (x 1) ON (x 1) ON (x 1) ON (x 1) ON (x 1) ON (x 1) ON (x 1) ON (x 1)
167
Table 9.4 Range of Usable Frequencies for Each Clock Operating Mode(SH7708R) (cont)
Clock Mode FRQCR 7 H'0100 H'0101 H'0102 H'0111 H'0112 H'0115 H'0116 H'0122 H'0126 H'012A H'A100 H'E100 H'E101 Clock Rate*1 (I:B:P) 1:1:1 1:1:1/2 1:1:1/4 2:1:1 2:1:1/2 1:1:1 1:1:1/2 4:1:1 2:1:1 1:1:1 3:1:1 1:1:1 1:1:1/2 Input Frequency CKIO Frequency Range Range 16 MHz to 33.3 MHz 16 MHz to 33.3 MHz 16 MHz to 60 MHz 16 MHz to 60 MHz 16 MHz to 60 MHz 16 MHz to 60 MHz
PLL1 ON (x 1) ON (x 1) ON (x 1) ON (x 2) ON (x 2) ON (x 2) ON (x 2) ON (x 4) ON (x 4) ON (x 4) ON (x 3)) ON (x 3) ON (x 3)
PLL2 OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF
16 MHz to 33.3 MHz 16 MHz to 33.3 MHz 16 MHz to 50 MHz 16 MHz to 50 MHz 16 MHz to 25 MHz 16 MHz to 25 MHz 16 MHz to 25 MHz 16 MHz to 50 MHz 16 MHz to 50 MHz 16 MHz to 25 MHz 16 MHz to 25 MHz 16 MHz to 25 MHz 16 MHz to 33.3 MHz 16 MHz to 33.3 MHz
25 MHz to 33.3 MHz 25 MHz to 33.3 MHz 25 MHz to 33.3 MHz 25 MHz to 33.3 MHz 25 MHz to 33.3 MHz 25 MHz to 33.3 MHz
Notes: 1. Input clock frequency is 1 2. Max frequency : I = 100 MHz, B = (CKIO) = 60 MHz, P = 30 MHz
Cautions: 1. When clock operating modes 3 and 4 are used: * The on/off state of PLL circuit 1 is set by the frequency control register. * PLL circuit 1 is initialized to the off state by a power-on reset. * Always turn PLL circuit 1 off before going into standby mode. 2. The input to divider 1 becomes the output of: * PLL circuit 1 when PLL circuit 1 is on. * PLL circuit 2 when PLL circuit 1 is off and PLL circuit 2 is on. * Divider 3 when PLL circuit 1 is off and PLL circuit 2 is off. 3. The input of divider 2 becomes the output of: * PLL circuit 1 when the clock operating mode is 0-2 or 7. * PLL circuit 2 when the clock operating mode is 3 and 4 and PLL circuit 2 is on. * Divider 3 when the clock operating mode is 3 and 4 and PLL circuit 2 is off. 4. The frequency of the internal clock (I) becomes: * The product of the frequency of the CKIO pin, the frequency multiplication ratio of PLL circuit 1, and the division ratio of divider 1 when PLL circuit 1 is on.
168
* Equal to the frequency of CKIO pin when PLL circuit 1 is off. * Do not set the internal clock frequency lower than the CKIO pin frequency. 5. The frequency of the peripheral clock (P) becomes: * The product of the frequency of the CKIO pin, the frequency multiplication ratio of PLL circuit 1, and the division ratio of divider 2 when the clock operating mode is 0-2 or 7. * The product of the frequency of the CKIO pin and the division ratio of divider 2 when the clock operating mode is 3 and 4. * The peripheral clock frequency should not be set higher than the frequency of the CKIO pin, higher than 30 MHz(SH7708, SH7708S) / 33.3 MHz(SH7708R), or lower than 1/4 (SH7708, SH7708S) / 1/8(SH7708R) the internal clock (I). 6. The output frequency of PLL circuit 1 is the product of the CKIO frequency and the multiplication ratio of PLL circuit 1. This frequency should be equal to or lower than 60 MHz(SH7708, SH7708S) / 100 MHz(SH7708R). 7. x 1, x 2, x 3* or x 4 can be used as the multiplication ratio of PLL circuit 1. x 1, x 1/2, x 1/3*, and x 1/4 can be selected as the division ratios of dividers 1 and 2. Set the rate in the frequency control register. The on/off state of PLL circuit 2 is determined by the mode. x 3 multiplication of PLL circuit 1 and x 1/3 of dividers 1 and 2 are not supported in emulator. Note: SH7708R only 8. For more in formation about the range of usable freguencies for each clock operating mode,see table 9.4.
169
9.4
9.4.1
Register Descriptions
Frequency Control Register (FRQCR)
The frequency control register (FRQCR) is a 16-bit read/write register used to specify whether a clock is output from the CKIO pin, the on/off state of PLL circuit 1, PLL standby, the frequency multiplication ratio of PLL circuit 1, and the frequency division ratio of the internal clock and the peripheral clock. Only word access can be used on the FRQCR register. FRQCR is initialized to H'0102 by a power-on reset, but retains its value in a manual reset and in standby mode. SH7708, SH7708S:
Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: 15 -- 0 R 7 PLLEN 0 R/W 14 -- 0 R 6 PSTBY 0 R/W 13 -- 0 R 5 STC1 0 R/W 12 -- 0 R 4 STC0 0 R/W 11 -- 0 R 3 IFC1 0 R/W 10 -- 0 R 2 IFC0 0 R/W 9 -- 0 R 1 PFC1 1 R/W 8 CKOEN 1 R/W 0 PFC0 0 R/W
Bit 8--Clock Enable (CKOEN): Used to output a clock from the CKIO pin or to fix the level of the CKIO pin. Even when the level is fixed, the SH7708 Series will operate internally at the frequency before the level was fixed. In case of clock operating mode 7, the CKIO pin becomes an input pin irrespective of the value of this bit.
Bit 8: CKOEN 0 1 Description Fixes the level of CKIO terminal. Outputs a clock from the CKIO pin.(Initial value)
Bit 7--PLL Circuit Enable (PLLEN): Specifies the on/off state of PLL circuit 1. This bit is valid in clock operating modes 3-6. PLL circuit 1 goes on when the clock operating mode is 0-2 or 7 irrespective of the value of PLLEN.
170
Bit 7: PLLEN 0 1
Description PLL circuit 1 is not used.(Initial value) PLL circuit 1 is used.
Bit 6--PLL Standby (PSTBY): Specifies PLL standby. When PLL standby is active, PLL circuit 1 will be in standby mode at the frequency specified by the STC bit. This function is valid in clock operating modes 3-6.
Bit 6: PSTBY 0 1 Description PLL is not in standby mode. (Initial value) PLL is in standby mode.
Bits 5 and 4--Frequency Multiplication Ratio (STC1, STC0): These bits specify the frequency multiplication ratio of PLL circuit 1.
Bit 5: STC1 0 0 1 1 Bit 4: STC0 0 1 0 1 Description x 1 (Initial value) x2 x4 Setting prohibited (do not set)
Note: Do not set the output frequency of PLL circuit 1 higher than 60 MHz.
Bits 3 and 2--Internal Clock Frequency Division Ratio (IFC1, IFC0): These bits specify the frequency division ratio of the internal clock with respect to the output frequency of PLL circuit 1. When PLL circuit 1 is off or in standby mode, set x 1.
Bit 3: IFC1 0 0 1 1 Bit 2: IFC0 0 1 0 1 Description x 1 (Initial value) x 1/2 x 1/4 Setting prohibited (do not set)
Note: Do not set the internal clock frequency lower than the CKIO frequency.
Bits 1 and 0--Peripheral Clock Frequency Division Ratio (PFC1, PFC0): These bits specify the division ratio of the peripheral clock frequency with respect to the frequency of the output frequency of PLL circuit 1 or the frequency of the CKIO pin.
171
Bit 1: PFC1 0 0 1 1
Bit 0: PFC0 0 1 0 1
Description x1 x 1/2 x 1/4 (Initial value) Setting prohibited (do not set)
Note: Do not set the peripheral clock frequency higher than the frequency of the CKIO pin.
SH7708R:
Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: 15 STC2 0 R/W 7 PLLEN 0 R/W 14 IFC2 0 R/W 6 PSTBY 0 R/W 13 PFC2 0 R/W 5 STC1 0 R/W 12 -- 0 R 4 STC0 0 R/W 11 -- 0 R 3 IFC1 0 R/W 10 -- 0 R 2 IFC0 0 R/W 9 -- 0 R 1 PFC1 1 R/W 8 CKOEN 1 R/W 0 PFC0 0 R/W
Bits 15, 5 and 4--Frequency Multiplication Ratio (STC): These bits specify the frequency multiplication ratio of PLL circuit 1.
Bit 15: STC2 0 0 1 1 Bit 5: STC1 0 0 0 1 Bit 4: STC0 0 1 0 0 Description x1 x2 x3 x4 (Initial value)
Note: Do not set the output frequency of PLL circuit 1 higher than 100MHz.
Bits 14, 3 and 2--Internal Clock Frequency Division Ratio (IFC): These bits specify the frequency division ratio of the internal clock with respect to the output frequency of PLL circuit 1. When PLL circuit 1 is off or in standby mode, set x 1.
Bit 14: IFC2 0 0 1 1 Bit 2: IFC1 0 0 0 1 Bit 1: IFC0 0 1 0 0 Description x1 x 1/2 x 1/3 x 1/4 (Initial value)
Note: Do not set the interunal clock frequency lower then the CKIO frequency.
172
Bits 13, 1 and 0--Peripheral Clock Frequency Division Ratio (PFC): These bits specify the division ratio of the peripheral clock frequency with respect to the frequency of the output frequency of PLL circuit 1 or the frequency of the CKIO pin.
Bit 13: PFC2 0 0 1 1 Bit 1: PFC1 0 0 0 1 Bit 0: PFC0 0 1 0 0 Description x1 x 1/2 x 1/3 x 1/4
Note: Do not set the peripheral clock frequency higher then the frequency of the CKIO pin.
Bit 8--Clock Enable (CKOEN): Used to output a clock in operating mode 3-6 from the CKIO pin or to fix the level of the CKIO pin in clock operation modes 3 and 4. Even when the level is fixed, the SH7708R will operate internally at the frequency before the level was fixed. In case of clock operating mode 0-2, set this bit to 1. In case of clock operating mode 7, the CKIO pin becomes an input pin irrespective of the value of this bit.
Bit 8: CKOEN 0 1 Description Fixes the level of CKIO terminal. Outputs a clock from the CKIO pin.(Initial value)
Bit 7--PLL Circuit Enable (PLLEN): Specifies the on/off state of PLL circuit 1. This bit is valid in clock operating modes 3 and 4. PLL circuit 1 goes on when the clock operating mode is 0-2 or 7 irrespective of the value of PLLEN.
Bit 7: PLLEN 0 1 Description PLL circuit 1 is not used.(Initial value) PLL circuit 1 is used.
Bit 6--PLL Standby (PSTBY): Specifies PLL standby. When PLL standby is active, PLL circuit 1 will be in standby mode at the frequency specified by the STC bit. This function is valid in clock operating modes 3 and 4.
Bit 6: PSTBY 0 1 Description PLL is not in standby mode. (Initial value) PLL is in standby mode.
173
9.5
Changing the Frequency
The frequency of the internal clock and peripheral clock can be changed either by changing the multiplication rate of PLL circuit 1 or by changing the division rates of dividers 1 and 2. All of these are controlled by software through the frequency control register. The methods are described below. In modes 3-6, the frequency can also be changed by turning PLL circuit 1 on and off, as described in section 9.6, PLL Standby Function. 9.5.1 Changing the Multiplication Rate
A PLL settling time is required when the multiplication rate of PLL circuit 1 is changed. The onchip WDT counts the settling time. 1. In the initial state, the multiplication rate of PLL circuit 1 is 1. 2. Set a value that will become the specified oscillation settling time in the WDT and stop the WDT. The following must be set: WTCSR register TME bit = 0: WDT stops WTCSR register CKS2-CKS0 bits: Division ratio of WDT count clock WTCNT counter: Initial counter value 3. Set the desired value in the STC1 and STC0 bits. The division ratio can also be set in the IFC1-IFC0 bits and PFC1-PFC0 bits. 4. The processor pauses internally and the WDT starts incrementing. In clock modes 0-2 and 7, the internal and peripheral clocks both stop. In clock modes 3 and 4, only the internal clock stops. The clock will continue to be output at the CKIO pin as long as the CKOEN bit in the FRQCR register is set to 1. 5. Supply of the clock that has been set begins at WDT count overflow, and the processor begins operating again. The WDT stops after it overflows. 9.5.2 Changing the Division Ratio
The WDT will not count unless the multiplication rate is changed simultaneously. 1. In the initial state, IFC1-IFC0 = 00 and PFC1-PFC0 = 10. 2. Set the IFC1, IFC0, PFC1, and PFC0 bits to the new division ratio. The values that can be set are limited by the clock mode and the multiplication rate of PLL circuit 1. Note that if the wrong value is set, the processor will malfunction. 3. The clock is immediately supplied at the new division ratio.
174
9.6
9.6.1
PLL Standby Function
Overview of the PLL Standby Function
When operating in clock modes 3 and 4, the internal clock can be controlled by turning the PLL1 circuit on and off. A long oscillation settling time is required, however, when the PLL circuit is started up from a complete halt. During this time, processor operation halts. To enable fast on/off switching of the PLL1 circuit, the PLL standby function is provided. This function is controlled by software using the frequency control register. The use of the PLL standby function is described below. 9.6.2 Usage
From Off to On: 1. Initially, PSTBY = 0, PLLEN = 0, and PLL circuit 1 is stopped. The output of PLL circuit 2 is used for divider 1 input. 2. When the multiplication rate of PLL circuit 1 is set in the STC1-STC0 bits and PSTBY is set to 1, PLL circuit 1 begins oscillating at the specified multiplication rate. The input to divider 1 is still the output of PLL circuit 2 at this point. 3. After PLL circuit 1 oscillation has stabilized, the input of divider 1 switches when PLLEN is set to 1 and the oscillation output of PLL circuit 1 is divided and becomes the internal clock. At this time, the division ratio can be changed by changing the settings of IFC1-IFC0 and PFC1-PFC0. For several cycles before and after the clock switches, the internal clock will be stopped, but the peripheral clock and CKIO output do not stop. From On to Off: 1. When PLLEN is set to 0, the input of divider 1 switches to the output of PLL circuit 2. At this time, the division ratio can be changed by changing the settings of IFC1-IFC0 and PFC1- PFC0. 2. When PSTBY is set to 0, PLL circuit 1 stops. This setting can be performed simultaneously (and with the same instruction as) the setting in 1 above. Notes: 1. There are some restrictions on the PLL standby state (PSTBY = 1, PLLEN = 0) as follows: The settings of the frequency control register's CKOEN, STC2-STC0, IFC2-IFC0 and PFC2-PFC0 bits generally cannot be changed. In some cases, however, they can be changed if the PSTBY and PLLEN bit settings are also changed simultaneously (figure 9.3). The SLEEP instruction cannot be executed. 2. It is the responsibility of software to ensure the oscillation settling time. If PLLEN is set to 1 before the oscillation has settled, malfunctions may be caused by an unstable clock.
175
3. In clock modes 3 and 4, the SH7708 Series cannot go to standby mode while PLL circuit 1 is on. Always set PSTBY and PLLEN to 0 to stop PLL circuit 1 before going to standby mode. 4. When PSTBY and PLLEN are both changed from 0 to 1 together, the WDT will automatically start counting and the clock will switch when the WDT overflows. See section 9.5, Changing the Frequency, for setting the WDT.
PSTBY = 1 and PLLEN = 0 PSTBY = 1 (STC) PLL1 off PSTBY = 0 and PLLEN = 0 PSTBY = 0 (STC) PLL1 standby PLLEN = 1 (IFC, PFC) PLLEN = 0 (STC, IFC, PFC) PLL1 on PSTBY = 1 and PLLEN = 1
PSTBY = 0, PLLEN = 0 (STC, IFC, PFC)
Note: Bits in parentheses can be changed simultaneously.
Figure 9.3
State Transitions for the PLL Standby Function
9.7
Controlling Clock Output
The CKOEN bit in the FRQCR register can be used to switch between outputting a clock to the CKIO pin or having the level fixed. 9.7.1 Clock Modes 0-2
The CKIO pin level cannot be fixed. Always set the CKOEN bit in FRQCR to 1 (clock output). 9.7.2 Clock Modes 3 and 4
The CKIO output changes as soon as the CKOEN bit is changed. When the WDT is started by simultaneously changing the multiplication rate of PLL circuit 1 or switching PLL circuit 1 on or off, the WDT starts running after the CKIO output is switched, and then the internal clock changes.
176
9.8
9.8.1
Overview of the Watchdog Timer (WDT)
Block Diagram of the WDT
Figure 9.4 shows a block diagram of the WDT.
WDT Standby cancellation Internal reset request Interrupt request Standby control Standby mode Peripheral clock Divider Clock selection Clock selector Interrupt control WTCSR Bus interface Overflow Clock WTCNT
Reset control
Internal bus WTCSR: WTCNT: Watchdog timer control/status register Watchdog timer counter
Figure 9.4 9.8.2 Register Configurations
Block Diagram of the WDT
The WDT has two registers that select the clock, switch the timer mode, and perform other functions. Table 9.5 shows the WDT register.
177
Table 9.5 Register Configuration
Name Watchdog timer counter Watchdog timer control/status register Abbreviatio n WTCNT WTCSR R/W R/W* R/W* Size R: byte; W: word* R: byte; W: word* Initial Value H'00 H'00 Address H'FFFFFF84 H'FFFFFF86
Note: Write with a word access. Write H'5A and H'A5, respectively, in the upper bytes. Byte or longword writes are not possible. Read with a byte access.
9.9
9.9.1
WDT Registers
Watchdog Timer Counter (WTCNT)
The watchdog timer counter (WTCNT) is an 8-bit read/write counter that increments on the selected clock. When an overflow occurs, it generates a reset in watchdog timer mode and an interrupt in interval time mode. Its address is H'FFFFFF84. The WTCNT counter is initialized to H'00 only by a power-on reset through the RESET pin. Use a word access to write to the WTCNT counter, with H'5A in the upper byte. Use a byte access to read WTCNT.
Bit: 7 6 5 4 3 2 1 0
Initial value: R/W:
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
9.9.2
Watchdog Timer Control/Status Register (WTCSR)
The watchdog timer control/status register (WTCSR) is an 8-bit read/write register composed of bits to select the clock used for the count, bits to select the timer mode, and overflow flags. Its address is H'FFFFFF86. The WTCSR register is initialized to H'00 only by a power-on reset through the RESET pin. When a WDT overflow causes an internal reset, the WTCSR retains its value. When used to count the clock settling time for canceling a standby, it retains its value after counter overflow. Use a word access to write to the WTCSR counter, with H'A5 in the upper byte. Use a byte access to read WTCSR.
Bit: 7 TME Initial value: R/W: 0 R/W 6 WT/IT 0 R/W 5 RSTS 0 R/W 4 WOVF 0 R/W 3 IOVF 0 R/W 2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W
178
Bit 7--Timer Enable (TME): Starts and stops timer operation. Clear this bit to 0 when using the WDT in standby mode or when changing the clock frequency.
Bit 7: TME 0 1 Description Timer disabled: Count-up stops and WTCNT value is retained (Initial value) Timer enabled
Bit 6--Timer Mode Select (WT/IT): Selects whether to use the WDT as a watchdog timer or an interval timer.
Bit 6: WT/I T 0 1 Description Use as interval timer(Initial value) Use as watchdog timer
Note: If WT/IT is modified when the WDT is running, the up-count may not be performed correctly.
Bit 5--Reset Select (RSTS): Selects the type of reset when the WTCNT overflows in watchdog timer mode. In interval timer mode, this setting is ignored.
Bit 5: RSTS 0 1 Description Power-on reset(Initial value) Manual reset
Bit 4--Watchdog Timer Overflow (WOVF): Indicates that the WTCNT has overflowed in watchdog timer mode. This bit is not set in interval timer mode.
Bit 4: WOVF 0 1 Description No overflow(Initial value) WTCNT has overflowed in watchdog timer mode
Bit 3--Interval Timer Overflow (IOVF): Indicates that the WTCNT has overflowed in interval timer mode. This bit is not set in watchdog timer mode.
Bit 3: IOVF 0 1 Description No overflow(Initial value) WTCNT has overflowed in interval timer mode
Bits 2 to 0--Clock Select 2-0 (CKS2-CKS0): These bits select the clock to be used for the WTCNT count from the eight types obtainable by dividing the peripheral clock. The overflow period in the table is the value when the peripheral clock (P) is 15 MHz.
179
Bit 2: CKS2 Bit 1: CKS1 Bit 0: CKS0 Clock Division Ratio 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 1/4 1/16 1/32 1/64 1/256 1/1024 1/4096 (Initial value)
Overflow Period (when P = 15 MHz) 17 s 68 s 273 s 546 s 1.09 ms 4.36 ms 17.46 ms 69.84 ms
Note: If bits CKS2-CKS0 are modified when the WDT is running, the up-count may not be performed correctly. Ensure that these bits are modified only when the WDT is not running.
9.9.3
Notes on Register Access
The watchdog timer counter (WTCNT) and watchdog timer control/status register (WTCSR) are more difficult to write to than other registers. The procedure for writing to these registers are given below. Writing to WTCNT and WTCSR: These registers must be written by a word transfer instruction. They cannot be written by a byte or longword transfer instruction. When writing to WTCNT, set the upper byte to H'5A and transfer the lower byte as the write data, as shown in figure 9.5. When writing to WTCSR, set the upper byte to H'A5 and transfer the lower byte as the write data. This transfer procedure writes the lower byte data to WTCNT or WTCSR.
WTCNT write 15 Address: H'FFFFFE84 H'5A 8 7 Write data 0
WTCSR write 15 Address: H'FFFFFE86 H'A5 8 7 Write data 0
Figure 9.5
Writing to WTCNT and WTCSR
180
9.10
Using the WDT
9 . 1 0 . 1 Canceling Standbys The WDT can be used to cancel standby mode with an NMI or other interrupts. The procedure is described below. (The WDT does not run when resets are used for canceling, so keep the RESET pin low until the clock stabilizes.) 1. Before transitioning to standby mode, always clear the TME bit in WTCSR to 0. When the TME bit is 1, an erroneous reset or interval timer interrupt may be generated when the count overflows. 2. Set the type of count clock used in the CKS2-CKS0 bits in WTCSR and the initial values for the counter in the WTCNT counter. These values should ensure that the time till count overflow is longer than the clock oscillation settling time. 3. Move to standby mode by executing a SLEEP instruction to stop the clock. 4. The WDT starts counting by detecting the edge change of the NMI signal or detecting interrupts. 5. When the WDT count overflows, the CPG starts supplying the clock and the processor resumes operation. The WOVF flag in WTCSR is not set when this happens. 6. The counter stops at the values H'00-H'01. The stop value depends on the clock ratio. 9 . 1 0 . 2 Changing the Frequency To change the frequency used by the PLL, use the WDT. When changing the frequency only by switching the divider, do not use the WDT. 1. Before changing the frequency, always clear the TME bit in WTCSR to 0. When the TME bit is 1, an erroneous reset or interval timer interrupt may be generated when the count overflows. 2. Set the type of count clock used in the CKS2-CKS0 bits of WTCSR and the initial values for the counter in the WTCNT counter. These values should ensure that the time till count overflow is longer than the clock oscillation settling time. 3. When the frequency control register (FRQCR) is written, the clock stops and the processor enters standby mode temporarily. The WDT starts counting. 4. When the WDT count overflows, the CPG resumes supplying the clock and the processor resumes operation. The WOVF flag in WTCSR is not set when this happens. 5. The counter stops at the values H'00-H'01. The stop value depends on the clock ratio.
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9 . 1 0 . 3 Using Watchdog Timer Mode 1. Set the WT/IT bit in the WTCSR register to 1, set the reset type in the RSTS bit, set the type of count clock in the CKS2-CKS0 bits, and set the initial value of the counter in the WTCNT counter. 2. Set the TME bit in WTCSR to 1 to start the count in watchdog timer mode. 3. While operating in watchdog timer mode, rewrite the counter periodically to H'00 to prevent the counter from overflowing. 4. When the counter overflows, the WDT sets the WOVF flag in WTCSR to 1 and generates the type of reset specified by the RSTS bit. The counter then resumes counting. 9 . 1 0 . 4 Using Interval Timer Mode When operating in interval timer mode, interval timer interrupts are generated at every overflow of the counter. This enables interrupts to be generated at set periods. 1. Clear the WT/IT bit in the WTCSR register to 0, set the type of count clock in the CKS2- CKS0 bits, and set the initial value of the counter in the WTCNT counter. 2. Set the TME bit in WTCSR to 1 to start the count in interval timer mode. 3. When the counter overflows, the WDT sets the IOVF flag in WTCSR to 1 and an interval timer interrupt request is sent to INTC. The counter then resumes counting.
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9 . 1 0 . 5 Usage Notes WTCNT should be set as shown below when using the SH7708 WDT in watchdog timer mode or interval timer mode.
(a) (b) Perform either processing (a) or processing (b). No processing is required when the WDT is not used (WTCSR.TME = 0). If this processing is not performed, the WDT count will stop in sleep mode. (a) Read WTCNT and confirm that it has been incremented, then execute a SLEEP instruction. (b) Wait for two WDT count clock cycles after WTCNT is set, then execute a SLEEP instruction.
WTCNT setting
WTCNT setting
WTCNT = set value + 1? Yes SLEEP instruction
No
Wait for 2 WDT count clock cycles
SLEEP instruction
Figure 9.6
To Operate the WDT in Sleep Mode
(a)
(b)
WTCNT setting
WTCNT setting
Perform either processing (a) or processing (b). No processing is required when the WDT is not used (WTCSR.TME = 0). If this processing is not performed, the second WTCNT setting may not be carried out. (a) After the first WTCNT setting, read WTCNT and confirm that it has been incremented, then perform the next WTCNT setting. (b) After the first WTCNT setting, wait for two WDT count clock
WTCNT = set value + 1? Yes WTNCT instruction
No
Wait for 2 WDT count clock cycles
WTCNT instruction
Figure 9.7
To Perform Repeated WTCNT Settings
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9.11
Notes on Board Design
When Using an External Crystal Resonator: Place the crystal resonator, capacitors CL1 and CL2, and damping resistor R close to the EXTAL and XTAL pins. To prevent induction from interfering with correct oscillation, use a common grounding point for the capacitors connected to the resonator, and do not locate a wiring pattern near these components.
Avoid crossing signal lines CL1 CL2
R EXTAL XTAL
SH7708R
Note:The values for CL1, CL2, and the damping resistance should be determined after consultation with the crystal manufacturer.
Figure 9.8
Points for Attention when Using Crystal Resonator
Decoupling Capacitors: As far as possible, insert a laminated ceramic capacitor of 0.01 to 0.1 F as a passive capacitor for each VSS/VCC pair. Mount the passive capacitors as close as possible to the LSI power supply pins, and use components with a frequency characteristic suitable for the LSI operating frequency, as well as a suitable capacitance value. Digital system VSS/VCC pairs: 6-7, 17-18, 19-20, 30-31, 41-42, 49-50, 54-55, 59-60, 68-69, 82-81,83, 100-102, 115-116, 121-122, 127-128, 144-139 On-chip oscillator VSS/VCC pairs: 73-75, 76-78, 138-135 When Using a PLL Oscillator Circuit: Keep the wiring from the PLL VCC and VSS connection pattern to the power supply pins short, and make the pattern width large, to minimize the inductance component. Ground the oscillation stabilization capacitors C1 and C2 to VSS (PLL1) and VSS (PLL2), respectively. Place C1 and C2 close to the CAP1 and CAP2 pins and do not locate a wiring pattern in the vicinity. In clock mode 7, connect the EXTAL pin to VCC or VSS and leave the XTAL pin open.
184
Avoid crossing signal lines VCC (PLL2) Power supply CAP2 VSS (PLL2) VCC (PLL1) VSS CAP1 C1 VSS (PLL1) C2 VCC Reference values C1 = 470 pF C2 = 470 pF
Figure 9.9
Points for Attention when Using PLL Oscillator Circuit
185
186
Section 10 Bus State Controller (BSC)
10.1 Overview
The bus state controller (BSC) divides physical address space and outputs control signals for various types of memory and bus interface specifications. BSC functions enable the SH7708 Series to link directly with DRAM, synchronous DRAM, pseudo-SRAM, SRAM, ROM, and other memory storage devices without an external circuit. The BSC also allows direct connection to PCMCIA interfaces, simplifying system design and allowing high-speed data transfers in a compact system. 1 0 . 1 . 1 Features The BSC has the following features: * Physical address space is divided into seven areas A maximum 64 Mbytes for each of the seven areas, 0-6 Area bus width can be selected by register (area 0 is set by external pin) Wait states can be inserted using the WAIT pin Wait state insertion can be controlled through software. Register settings can be used to specify the insertion of 1-10 cycles independently for each area (areas 1 and 2 have a common setting) The type of memory connected can be specified for each area, and control signals are output for direct memory connection Wait cycles are automatically inserted to avoid data bus conflict for continuous memory accesses to different areas or writes directly following reads of the same area * Direct interface to DRAM Multiplexes row/column addresses according to DRAM capacity Supports burst operation (high-speed page mode, hyper page mode) Supports CAS-before-RAS refresh and self-refresh Performs low power 4-CAS-system byte control Controls timing of DRAM direct-connection control signals according to register settings * Direct interface to synchronous DRAM Multiplexes row/column addresses according to synchronous DRAM capacity Supports burst operation Has both auto-refresh and self-refresh functions Controls timing of synchronous DRAM direct-connection control signals according to register setting
187
* Direct interface to pseudo-SRAM Supports burst operation (static column mode) Auto-refresh and self-refresh * ROM burst interface Insertion of wait states controllable through software Register setting control of burst transfers * PCMCIA direct-connection interface Insertion of wait states controllable through software Burst operation (page mode) Bus sizing function for I/O bus width (little-endian mode only) * Fine refreshing control Supports refresh operation immediately after self-refresh operation in low-power DRAM by means of refresh counter overflow interrupt function * Refresh counter can be used as an interval timer Interrupt request generated at compare-match Interrupt request generated at refresh counter overflow 1 0 . 1 . 2 Block Diagram Figure 10.1 shows a block diagram of the bus state controller.
188
Bus interface
WAIT
Wait controller
WCR1 WCR2
CS6-CS0, CE2A, CE2B BS RD RD/WR WE3-WE0 RAS CAS, CASxx CKE ICIORD, ICIOWR IOIS16 Peripheral bus
Area controller
BCR1 BCR2 MCR DCR PCR RFCR RTCNT Module bus
Memory controller
Interrupt controller
Refresh controller
Comparator RTCOR RTCSR BSC
WCR: BCR: MCR: DCR: PCR:
Wait state control register Bus control register Memory control register DRAM control register PCMCIA control register
RFCR: RTCNT: RTCOR: RTCSR:
Refresh count register Refresh timer count register Refresh time constant register Refresh timer control/status register
Figure 10.1
BSC Block Diagram
Internal bus 189
1 0 . 1 . 3 Pin Configuration Table 10.1 lists the BSC pins. Table 10.1Pin Configuration
Pin Name Address bus Data bus Signal A25-A0 D31-D24, D15-D0 I/O O I/O Description Address output Data I/O When port function is used, D31-D24 cannot be used. Leave these pins open. When port function is not used, data I/O; when port function is used, port (I/O is set by register for each bit) Shows start of bus cycle. During burst transfers, asserts every data cycle. Chip select signal to indicate area being accessed. CS5 and CS6 can also be used as CE1A and CE1B of PCMCIA. Data bus direction indicator signal. DRAM/synchronous DRAM/PCMCIA write indicator signal. When DRAM/synchronous DRAM is used, RAS signal. When pseudo-SRAM is used, CE signal. When synchronous DRAM is used, CAS signal. When DRAM is used, CAS signal for D7-D0. When pseudo-SRAM is used, OE/RFSH signal. When DRAM is used, CAS signal for D15-D8 When DRAM is used, CAS signal for D23-D16. When the area 2 DRAM is being used, CAS signal for D7- D0. When DRAM is used, CAS signal for D31-D24. When the area 2 DRAM is being used, CAS signal for D15- D8.
Data bus/port
D23-D16/ I/O PORT7-PORT0 BS CS6-CS0 O O
Bus cycle start Chip select 6-0
Read/write
RD/WR
O
Row address strobe Column address strobe Column address strobe LH Column address strobe HL Column address strobe HH
RAS/CE CAS/CASLL/ OE CASLH
O O
O
CASHL , CAS2L O
CASHH, CAS2H O
190
Table 10.1Pin Configuration (Preliminary) (cont)
Pin Name Data enable 0 Data enable 1 Signal DQMLL/WE0 DQMLU/WE1 I/O O O Description When synchronous DRAM is used, selects D7-D0. For other memory, D7-D0 write strobe signal. When synchronous DRAM is used, selects D15-D8. When PCMCIA is used, strobe signal that indicates the write cycle. For other memory, D15-D8 write strobe signal. When synchronous DRAM is used, selects D23- D16. For other memory, D23-D16 write strobe signal. For PCMCIA, strobe signal indicating I/O read. When synchronous DRAM is used, selects D31- D24. For other memory, D31-D24 write strobe signal. For PCMCIA, strobe signal indicating I/O write. Strobe signal indicating read cycle Wait state request signal (synchronous signal) Signal indicating PCMCIA 16-bit I/O. Valid only in little-endian mode. (Fix low in big-endian mode.) Connected to clock enable control signal of synchronous DRAM Bus release request signal Bus release acknowledge signal Signal controlling bus width of physical space area 0. When PCMCIA is used, CE2A and CE2B. Signal setting endian for all spaces on reset. When area 2 DRAM is connected, area 2 DRAM RAS signal
Data enable 2
DQMUL/WE2 / ICIORD DQMUU/WE3 / ICIOWR RD WAIT IOIS16 CKE BREQ BACK MD3/CE2A* , 2 MD4/CE2B*
3 1
O
Data enable 3
O
Read Wait 16-bit I/O Clock enable Bus release request Bus release acknowledgment Area 0 bus width, PCMCIA card select
O I I O I O I/O
Endian switching/ MD5/RAS2* low address strobe
I/O
Notes: 1. MD3/CE2A input/output switching is performed by BCR1.A5PCM. Output is selected when BCR1.A5PCM = 1. 2. MD4/CE2B input/output switching is performed by BCR1.A6PCM. Output is selected when BCR1.A6PCM = 1. 3. MD5/RAS2 input/output switching is performed by BCR1.DRAMTP. Output is selected when BCR1.DRAMTP (2-0) = 101.
191
1 0 . 1 . 4 Register Configuration The BSC has 11 registers (table 10.2). The synchronous DRAM also has a built-in synchronous DRAM mode register. These registers control direct connection interfaces to memory, wait states, refreshes, and PCMCIA devices. Table 10.2Register Configuration
Name Bus control register 1 Bus control register 2 Wait state control register 1 Wait state control register 2 Individual memory control register DRAM control register PCMCIA control register Abbr. BCR1 BCR2 WCR1 WCR2 MCR DCR PCR R / W Initial Value* 2 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W W H'0000 H'3FFC H'3FFF H'FFFF H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 -- -- Address H'FFFFFF60 H'FFFFFF62 H'FFFFFF64 H'FFFFFF66 H'FFFFFF68 H'FFFFFF6A H'FFFFFF6C H'FFFFFF6E H'FFFFFF70 H'FFFFFF72 H'FFFFFF74 H'FFFFD000- H'FFFFDFFF H'FFFFE000- H'FFFFEFFF Bus 16 16 16 16 16 16 16 16 16 16 16 8 Width
Refresh timer control/status register RTCSR Refresh timer counter Refresh time constant register Refresh count register SDRAM mode register, area 2 SDRAM mode register, area 3 RTCNT RTCOR RFCR SDMR
Notes: 1. For details see section 10.2.8, Synchronous DRAM Mode Register. 2. Initialized during a power-on reset.
192
1 0 . 1 . 5 Area Overview Space Allocation: The SH7708 Series architecture provides for a 32-bit virtual address space. The virtual space is divided into five areas by the value of the upper bits of the address. The physical space is divided into eight areas with a 29-bit address space. Virtual space can be allocated at will to physical spaces using a memory management unit (MMU). For details, refer to section 3, Memory Management Unit, which describes area allocation for physical spaces. As shown in table 10.4, the SH7708 Series can be connected directly to seven areas of memory/PC card, and it outputs chip select signals (CS0-CS6, CE2A, CE2B ) for each of them. CS0 is asserted during area 0 access; CS6 is asserted during area 6 access. When DRAM, synchronous DRAM, or pseudo-SRAM is connected to area 2 or 3, signals such as RAS, CAS, RD/WR, and DQM are also asserted. When PCMCIA interface is selected in area 5 or 6, in addition to CS5/CS6, CE2A/CE2B are asserted for the corresponding bytes accessed. For virtual address spaces P0 and P3, when the memory management unit (MMU) is on, any physical address can be generated by the MMU for a virtual address. Consequently, figure 10.2 can be applied when the MMU is off, and when the MMU is on and the physical addresses corresponding to virtual addresses are identical except for the top 3 bits. When virtual addresses are translated to arbitrary physical addresses, refer to table 10.3, Physical Address Space Map.
H'00000000 H'20000000 H'40000000 H'60000000 H'80000000 P1 H'A0000000 P2 H'C0000000 P3 H'E0000000 P4 P0, U0
Area 0 (CS0) Area 1 (CS1) Area 2 (CS2) Area 3 (CS3) Area 4 (CS4) Area 5 (CS5) Area 6 (CS6) Reserved area
H'00000000 H'04000000 H'08000000 H'0C000000 H'10000000 H'14000000 H'18000000
Physical address space
Virtual address space
Figure 10.2
Correspondence between Virtual Address Space and Physical Address Space
193
Table 10.3 Physical Address Space Map
A r e a Physical Address 0 H'00000000 to H'03FFFFFF Connectable Memory Capacity Access Size 64 Mbytes 8, 16, 32*2 Shadow n: 1-6
Normal memory*1, burst H'00000000 + H'20000000 x n to ROM H'03FFFFFF + H'20000000 x n H'04000000 to H'07FFFFFF H'04000000 + H'20000000 x n to H'07FFFFFF + H'20000000 x n Normal memory
1
64 Mbytes 8, 16, 32*3 Shadow n: 1-6
2
Normal memory, synchronous DRAM, DRAM H'08000000 + H'20000000 x n to H'0BFFFFFF + H'20000000 x n H'0C000000 to H'0FFFFFFF Normal memory, H'0C000000 + H'20000000 x n to synchronous DRAM, DRAM, pseudo-SRAM H'0FFFFFFF + H'20000000 x n H'10000000 to H'13FFFFFF H'10000000 + H'20000000 x n to H'13FFFFFF + H'20000000 x n Normal memory
H'08000000 to H'0BFFFFFF
64 Mbytes 8, 16, 32*3, *4 Shadow n: 1-6
3
64 Mbytes 8, 16, 32*3, *5 Shadow n: 1-6
4
64 Mbytes 8, 16, 32*3 Shadow n: 1-6
5*5
H'14000000 to H'15FFFFFF H'16000000 to H'17FFFFFF H'14000000 + H'20000000 x n to H'17FFFFFF + H'20000000 x n
Normal memory, PCMCIA, burst ROM
32 Mbytes 8, 16, 32 *3, *6 32 Mbytes Shadow n: 1-6
6
H'18000000 to H'19FFFFFF H'1A000000 to H'1BFFFFFF H'18000000 + H'20000000 x n to H'1BFFFFFF + H'20000000 x n
Normal memory, PCMCIA, burst ROM
32 Mbytes 8, 16, 32 *3, *6
Shadow
n: 1-6 n: 0-7
7*7
H'1C000000 + H'20000000 x n Reserved area to H'1FFFFFFF + H'20000000 x n
Notes: 1. 2. 3. 4.
Memory with an SRAM, ROM, or similar interface Memory bus width specified by external pin Memory bus width specified by register With synchronous DRAM interface, bus width is 32 bits only. With DRAM interface, bus width is 16 bits only. 5. With synchronous DRAM interface, bus width is 32 bits only. With DRAM and pseudo-SRAM interface, bus width is either 16 or 32 bits only. When areas 2 and 3 are both DRAM interface areas, bus width is 16 bits only. 6. With PCMCIA interface, bus width is either 8 or 16 bits only. 7. Do not access a reserved area, as operation cannot be guaranteed in this case.
194
Area 0: H'00000000 Area 1: H'04000000 Area 2: H'08000000
Normal memory/ burst ROM Normal memory Normal memory/ synchronous DRAM, DRAM Only DRAM with a 16-bit bus can be connected to area 2
Area 3: H'0C000000 Normal memory/synchronous DRAM, DRAM, pseudo-SRAM Area 4: H'10000000 Normal memory Area 5: H'14000000 Area 6: H'18000000 Normal memory/ burst ROM/PCMCIA Normal memory/ burst ROM/PCMCIA The PCMCIA interface is for the memory card only The PCMCIA interface is shared by the memory and I/O card
Figure 10.3
Physical Space Allocation
Memory Size: The memory size in the SH7708Series can be set for each area. In area 0, an external pin can be used to select byte (8 bits), word (16 bits), or longword (32 bits). The relationship between the external pins (MD4 and MD3) and the bus width after a power-on reset is as follows.
MD4 0 MD3 0 1 1 0 1 Bus Width Reserved (do not set) 8 bits 16 bits 32 bits
For areas 1-6, byte, word, and longword may be chosen for the bus width using bus control register 2 (BCR2) whenever normal memory, ROM, burst ROM, or the PCMCIA interface is used. When the DRAM or pseudo-SRAM interfaces are used, word or longword can be chosen as the bus width using the individual memory control register (MCR). Set the bus width to longword with MCR for synchronous DRAM interfaces. When area 2 is used as a DRAM area, set the bus widths of areas 2 and 3 to word. When areas 5 and 6 are used as PCMCIA interfaces, set the bus width to byte or word. When using the port function, set each of the bus widths to byte or word for all areas. For more information, see section 10.2.2, Bus Control Register 2 (BCR2), and section 10.2.5, Individual Memory Control Register (MCR).
195
Shadow Space: Areas 0-6 are decoded by physical address bits A28-A26, which correspond to areas 000 to 110. Address bits 31-29 are ignored. This means that the range of area 0 addresses, for example, is H'00000000 to H'03FFFFFF, and its corresponding shadow space is the address space obtained by adding to it H'20000000 x n (n = 1-6). The address range for area 7, which is on-chip I/O space, is H'FC000000 to H'FFFFFFF. The address space H'1C000000 + H'20000000 x n- H'1FFFFFFF + H'20000000 x n (n = 0-6) corresponding to the area 7 shadow space is reserved, so should not be used. 1 0 . 1 . 6 PCMCIA Support The SH7708 Series supports PCMCIA standard interface specifications in physical space areas 5 and 6. The interface supported is basically the IC memory card interface and I/O card interface defined by PCMCIA Specifications Version 4.2. In addition, burst access is supported to enable high-speed access. Physical space area 5 supports the IC memory card interface only; area 6 supports both the IC memory card interface and the I/O card interface. Table 10.4PCMCIA Interface Characteristics
Item Access Data bus Memory type Memory capacity I/O section capacity Other Characteristics Random access + burst access (ROM page mode correspondence added) 8/16 bits Mask ROM, OTPROM, EPROM, EEPROM, flash memory, SRAM Maximum 32 Mbytes Maximum 32 Mbytes Supports dynamic I/O bus sizing* and access to PCMCIA interface from both the address translation area and non-address translation area
Note: Dynamic I/O bus sizing is supported only in little-endian mode.
Area 5: H'14000000 Area 5: H'16000000 Area 6: H'18000000 Area 6: H'1A000000
Common memory/Attribute memory
Common memory/Attribute memory I/O space
Figure 10.4
196
PCMCIA Space Allocation
Table 10.5 PCMCIA Support Interface
IC Memory Card Interface P i n Signal 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 GND D3 D4 D5 D6 D7 CE1 A10 OE A11 A9 A8 A13 A14 WE /PGM RDY/BSY VCC VPP1 A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 D0 I I I I I I I I I I I I / O Function -- Ground Signal GND D3 D4 D5 D6 D7 CE1 A10 OE A11 A9 A8 A13 A14 WE /PGM IREQ VCC VPP1 A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 D0 I I I I I I I I I I I I/O Card Interface I / O Function -- Ground SH7708 Series Pin -- D3 D4 D5 D6 D7 CS5 or CS6 A10 RD A11 A9 A8 A13 A14 WE1 Sensed at port -- -- A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 D0 197
I/O Data I/O Data I/O Data I/O Data I/O Data I I I I I I I I I O Card enable Address Output enable Address Address Address Address Address Write enable Ready/Busy Operation power Program power Address Address Address Address Address Address Address Address Address Address Address
I/O Data I/O Data I/O Data I/O Data I/O Data I I I I I I I I I O Card enable Address Output enable Address Address Address Address Address Write enable Interrupt request Operation power Program/ peripheral power Address Address Address Address Address Address Address Address Address Address Address
I/O Data
I/O Data
198
Table 10.5 PCMCIA Support Interface (cont)
IC Memory Card Interface P i n Signal 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 D1 D2 WP* GND GND CD1 D11 D12 D13 D14 D15 CE2 RFSH RFU RFU A17 A18 A19 A20 A21 VCC VPP2 A22 A23 A24 A25 RFU RESET I I I I I I I I I I O I / O Function I/O Data I/O Data O Write protect Ground Ground Card detection Signal D1 D2 IOIS16 GND GND CD1 D11 D12 D13 D14 D15 CE2 RFSH IORD IOWR A17 A18 A19 A20 A21 VCC VPP2 A22 A23 A24 A25 RFU RESET I I I I I O I/O Card Interface I / O Function I/O Data I/O Data O 16 bit I/O port Ground Ground Card detection SH7708 Series Pin D1 D2 IOIS16 -- -- Sensed at port D11 D12 D13 D14 D15 CE2A or CE2B Output from port ICIORD ICIOWR A17 A18 A19 A20 A21 -- -- A22 A23 A24 Output from port -- Output from port 199
I/O Data I/O Data I/O Data I/O Data I/O Data I I Card enable Refresh request Reserved Reserved Address Address Address Address Address Power supply Program power Address Address Address Address Reserved Reset
I/O Data I/O Data I/O Data I/O Data I/O Data I I I I I I I I I Card enable Refresh request I/O read I/O write Address Address Address Address Address Power supply Program/ peripheral power Address Address Address Address Reserved Reset
Table 10.5 PCMCIA Support Interface (cont)
IC Memory Card Interface P i n Signal 59 60 61 62 63 64 65 66 67 68 WAIT RFU REG BVD2 BVD1 D8 D9 D10 CD2 GND I O O I / O Function O Wait request Reserved Attribute memory space select Battery voltage detection Battery voltage detection Signal WAIT INPACK REG SPKR STSCHG D8 D9 D10 CD2 GND I/O Card Interface I / O Function O O I O O Wait request SH7708 Series Pin WAIT
Input acknowledge -- Attribute memory space select Digital voice signal Card status change Output from port Sensed at port Sensed at port D8 D9 D10 Sensed at port --
I/O Data I/O Data I/O Data O Card detection Ground
I/O Data I/O Data I/O Data O Card detection Ground
Note: The SH7708 Series does not provide WP support.
200
10.2
BSC Registers
Control Register 1 (BCR1)
1 0 . 2 . 1 Bus
The bus control register 1 (BCR1) is a 16-bit read/write register that sets the functions and bus cycle status for each area. It is initialized to H'0000 by a power-on reset, but is not initialized by a manual reset or in standby mode. Do not access external memory outside area 0 until BCR1 register initialization is complete.
Bit: Bit name: Initial value: R/W: Bit: 15 -- 0 R 7 14 -- 0 R 6 13
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12
11
10
9
8
HIZMEM* HIZCNT ENDIAN A0BST1 A0BST0 A5BST1
0 R/W 5
0 R/W 4 DRAM TP2 0 R/W
0/1*1 R 3 DRAM TP1 0 R/W
0 R/W 2 DRAM TP0 0 R/W
0 R/W 1
0 R/W 0
Bit name: A5BST0 A6BST1 A6BST0 Initial value: R/W: 0 R/W 0 R/W 0 R/W
A5PCM A6PCM 0 R/W 0 R/W
Notes: 1. Samples the value of the external pin designating endian upon a power-on reset. 2. Reserved bit in the SH7708.
Bits 15 and 14--Reserved: These bits always read 0. The write value should always be 0. Bits 13 (SH7708)--Reserved: These bits always read 0. The write value should always be 0. This bit is not supported in emulator. Bit 13 (SH7708S, SH7708R) --High-Z Memory Control (HIZMEM): Specifies the state of A25 to A0, BS, CS, RD/WR, WE/DQM, RD, MD3/CE2A, and MD4/CE2B in standby mode.
Bit 13: HIZMEM 0 1 Description High-impedance (high-Z) in standby mode value) Drive state in standby mode (Initial
Bit 12--High-Z Control (HIZCNT): Specifies the state of the RAS and CAS signals in the standby and bus-released states.
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Bit 12: HIZCNT 0
Description RAS and CAS signals become high-impedance (High-Z) in standby mode and in bus-released state. (Initial value) RAS and CAS signals drive in standby mode and in bus-released state.
1
Bit 11--Endian Flag (ENDIAN): Samples the value of the external pin designating endian upon a power-on reset. Endian for all physical spaces is decided by this bit, which is read-only.
Bit 11: ENDIAN 0 1 Description (On reset) Endian setting external pin (MD5) is low. Indicates the SH7708 Series is set as big-endian. (On reset) Endian setting external pin (MD5) is high. Indicates the SH7708 Series is set as little-endian.
Bits 10 and 9--Area 0 Burst ROM Control (A0BST1-A0BST0): These bits specify whether to use burst ROM in physical space area 0. When burst ROM is used, they set the number of burst transfers.
Bit 10: A0BST1 0 Bit 9: A0BST0 0 1 1 0 1 Description Access area 0 as normal memory. (Initial value)
Access area 0 as burst ROM (4 consecutive accesses). Can be used when bus width is 8, 16, or 32. Access area 0 as burst ROM (8 consecutive accesses). Can be used only when bus width is 8 or 16. Access area 0 as burst ROM (16 consecutive accesses). Can be used only when bus width is 8.
Bits 8 and 7--Area 5 Burst Enable (A5BST1-A5BST0): These bits specify whether to use burst ROM and PCMCIA burst mode in physical space area 5. When burst ROM and PCMCIA burst mode are used, they set the number of burst transfers.
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Bit 8: A5BST1 0
Bit 7: A5BST0 0 1
Description Access area 5 as normal memory. value) (Initial
Burst access of area 5 (4 consecutive accesses). Can be used when bus width is 8, 16, or 32. Burst access of area 5 (8 consecutive accesses). Can be used only when bus width is 8 or 16. Burst access of area 5 (16 consecutive accesses). Can be used only when bus width is 8.
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0 1
Bits 6 and 5--Area 6 Burst Enable (A6BST1-A6BST0): These bits specify whether to use burst ROM and PCMCIA burst mode in physical space area 6. When burst ROM and PCMCIA burst mode are used, they set the number of burst transfers.
Bit 6: A6BST1 0 Bit 5: A6BST0 0 1 1 0 1 Description Access area 6 as normal memory. value) (Initial
Burst access of area 6 (4 consecutive accesses). Can be used when bus width is 8, 16, or 32. Burst access of area 6 (8 consecutive accesses). Can be used only when bus width is 8 or 16. Burst access of area 6 (16 consecutive accesses). Can be used only when bus width is 8.
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Bits 4 to 2--Area 2, Area 3 Memory Type (DRAMTP2, DRAMTP1, DRAMTP0): These bits designate the types of memory connected to physical space areas 2 and 3. Normal memory, such as ROM, SRAM, or flash RAM, can be directly connected. Pseudo-SRAM, DRAM, and synchronous DRAM can also be directly connected.
Bit 4: DRAMTP2 0 Bit 3: DRAMTP1 0 Bit 2: DRAMTP0 0 Description Areas 2 and 3 are normal memory (Initial value) Area 2: normal memory; area 3: PSRAM Area 2: normal memory; area 3: SDRAM Areas 2 and 3 are SDRAM Area 2: normal memory; area 3: DRAM Areas 2 and 3 are DRAM * Reserved (cannot be set) Reserved (cannot be set)
1 1 0 1 1 0 0 1 1 0 1
Note: When selecting these bits, set the area 2 and 3 bus widths as word. The MD5 pin output is the RAS2 signal.
Bit 1--Area 5 Bus Type (A5PCM): Designates whether to access physical space area 5 as PCMCIA space.
Bit 1: A5PCM 0 1 Description Access physical space area 5 as normal memory. Access physical space area 5 as PCMCIA space.* (Initial value)
Note: MD3 pin output is CE2A.
Bit 0--Area 6 Bus Type (A6PCM): Designates whether to access physical space area 6 as PCMCIA space.
Bit 0: A6PCM 0 1 Description Access physical space area 6 as normal memory. Access physical space area 6 as PCMCIA space.* (Initial value)
Note: MD4 pin output is CE2B.
1 0 . 2 . 2 Bus
Control Register 2 (BCR2)
Bus control register 2 (BCR2) is a 16-bit read/write register that selects the bus size of each area, and whether to use the 8-bit port. It is initialized to H'3FFC by a power-on reset, but is not
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initialized by a manual reset or in standby mode. Do not access external memory outside area 0 until BCR2 register initialization is complete.
Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: 15 -- 0 R 7 A3SZ1 1 R/W 14 -- 0 R 6 A3SZ0 1 R/W 13 A6SZ1 1 R/W 5 A2SZ1 1 R/W 12 A6SZ0 1 R/W 4 A2SZ0 1 R/W 11 A5SZ1 1 R/W 3 A1SZ1 1 R/W 10 A5SZ0 1 R/W 2 A1SZ0 1 R/W 9 A4SZ1 1 R/W 1 -- 0 -- 8 A4SZ0 1 R/W 0 PORTEN 0 R/W
Bits 15, 14, 1--Reserved: These bits always read 0. The write value should always be 0. Bits 2n + 1, 2n--Area n (1-6) Bus Size Specification (AnSZ1, AnSZ0): These bits specify the bus sizes of physical space area n (n = 1 to 6).
Bit 2n + 1: AnSZ1 0 Bit 2n: AnSZ0 0 1 1 0 1 Bit 0: PORTEN 0 Description Reserved (not settable) Byte (8-bit) size Word (16-bit) size Longword (32-bit) size (Initial value) 0 0 1 1 0 1 1 Reserved (not settable) Byte (8-bit) size Word (16-bit) size Reserved (not settable)
Bit 0--Port Function Enable (PORTEN): Designates whether to use the D23-D16 pins as an 8-bit port. When using this function set the bus widths to word or byte in all areas.
Bit 0: PORTEN 0 1 Description D23-D16 are not used as a port. D23-D16 are used as a port. (Initial value)
1 0 . 2 . 3 Wait State Control Register 1 (WCR1)
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Wait state control register 1 (WCR1) is a 16-bit read/write register that specifies the number of idle (wait) state cycles inserted for each area. For some memories, the drive of the data bus may not be turned off quickly even when the read signal from the external device is turned off. This can result in conflicts between data buses when consecutive memory accesses are to different memories or when a write immediately follows a memory read. The SH7708 Series automatically inserts idle states equal to the number set in WCR1 in those cases. WCR1 is initialized to H'3FFF by a power-on reset. It is not initialized by a manual reset or in standby mode, but retains its contents.
Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: 15 -- 0 R 7 A3IW1 1 R/W 14 -- 0 R 6 A3IW0 1 R/W 13 A6IW1 1 R/W 5 A2IW1 1 R/W 12 A6IW0 1 R/W 4 A2IW0 1 R/W 11 A5IW1 1 R/W 3 A1IW1 1 R/W 10 A5IW0 1 R/W 2 A1IW0 1 R/W 9 A4IW1 1 R/W 1 A0IW1 1 R/W 8 A4IW0 1 R/W 0 A0IW0 1 R/W
Bits 15, 14 --Reserved: These bits always read 0. The write value should always be 0. Bits 2n + 1, 2n--Area n (6-0) Intercycle Idle Specification (AnIW1, AnIW0): These bits specify the number of idles inserted between bus cycles when switching between physical space area n (6- 0) to another space or between a read access to a write access in the same physical space.
Bit 2n + 1: AnIW1 0 Bit 2n: AnIW0 0 1 1 0 1 Description No idle cycles 1 idle cycle inserted 2 idle cycles inserted 3 idle cycles inserted value) (Initial
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1 0 . 2 . 4 Wait State Control Register 2 (WCR2) Wait state control register 2 (WCR2) is a 16-bit read/write register that specifies the number of wait state cycles inserted for each area. It also specifies the pitch of data access for burst memory accesses. This allows direct connection of even low-speed memories without an external circuit. WCR2 is initialized to H'FFFF by a power-on reset. It is not initialized by a manual reset or in standby mode, but retains its contents.
Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: 15 A6W2 1 R/W 7 A4W0 1 R/W 14 A6W1 1 R/W 6 A3W1 1 R/W 13 A6W0 1 R/W 5 A3W0 1 R/W 12 A5W2 1 R/W 4 11 A5W1 1 R/W 3 10 A5W0 1 R/W 2 A0W2 1 R/W 9 A4W2 1 R/W 1 A0W1 1 R/W 8 A4W1 1 R/W 0 A0W0 1 R/W
A1-2W1 A1-2W0 1 R/W 1 R/W
Bits 15 to 13--Area 6 Wait Control (A6W2, A6W1, A6W0): These bits specify the number of wait states inserted in physical space area 6. They also specify the burst pitch for burst transfer.
Description First Cycle Bit 15: Bit 14: Bit 13: A6W2 A6W1 A6W0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Inserted Wait States WAIT Pin 0 1 2 3 4 6 8 Ignored Enabled Enabled Enabled Enabled Enabled Enabled Burst Cycle (Excluding First Cycle) Number of States Per Data Transfer WAIT Pin 2 2 3 4 4 6 8 10 Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled
10 (Initial value) Enabled
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Bits 12 to 10--Area 5 Wait Control (A5W2, A5W1, A5W0): These bits specify the number of wait states inserted in physical space area 5. They also specify the burst pitch for burst transfer.
Description First Cycle Bit 12: Bit 11: Bit 10: A5W2 A5W1 A5W0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Inserted Wait States WAIT Pin 0 1 2 3 4 6 8 Ignored Enabled Enabled Enabled Enabled Enabled Enabled Burst Cycle (Excluding First Cycle) Number of States Per Data Transfer WAIT Pin 2 2 3 4 4 6 8 10 Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled
10 (Initial value) Enabled
Bits 9 to 7--Area 4 Wait Control (A4W2, A4W1, A4W0): These bits specify the number of wait states inserted in physical space area 4.
Description Bit 9: A4W2 0 Bit 8: A4W1 0 Bit 7: A4W0 0 1 1 0 1 1 0 0 1 1 0 1 Inserted Wait States 0 1 2 3 4 6 8 10 WAIT Pin Ignored Enabled Enabled Enabled Enabled Enabled Enabled Enabled (Initial value)
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Bits 6 and 5--Area 3 Wait Control (A3W1, A3W0): These bits specify the number of wait states inserted in physical space area 3. External wait input is enabled only when normal memory is used, and is ignored when DRAM, synchronous DRAM, or pseudo-SRAM is used. * For Normal Memory
Description Bit 6: A3W0 0 Bit 5: A3W0 0 1 1 0 1 Inserted Wait States WAIT Pin 0 1 2 3 Ignored Enabled Enabled Enabled (Initial value)
* For DRAM, SDRAM, Pseudo-SRAM
Description Bit 6: A3W1 0 Bit 5: A3N0 0 1 1 0 1 DRAM: CAS Assert Period 1 1 2 3 SDRAM: CAS Latency 1 1 2 3 PSRAM: OE, W E Assert Period 1 1 2 3 (Initial value)
Bits 4 and 3--Areas 1 and 2 Wait Control (A1-2W1, A1-2W0): These bits specify the number of wait states inserted in physical space areas 1 and 2. External wait input is enabled only when normal memory is used, and is ignored when DRAM or synchronous DRAM is used.
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* For Normal Memory
Description Bit 4: A1-2W0 0 Bit 3: A1-2W0 0 1 1 0 1 Inserted Wait States WAIT Pin 0 1 2 3 Ignored Enabled Enabled Enabled (Initial value)
* For DRAM, Synchronous DRAM
Description Bit 4: A1-2W0 Bit 3: A1-2W0 0 0 1 1 0 1 DRAM: CAS Assert Period SDRAM: CAS Latency 1 1 2 3 1 1 2 3 (Initial value)
Bits 2 to 0--Area 0 Wait Control (A0W2, A0W1, A0W0): These bits specify the number of wait states inserted in physical space area 0. They also specify the burst pitch for burst transfer.
Description First Cycle Bit 2: A0W2 0 Bit 1: A0W1 0 Bit 0: A0W0 0 1 1 0 1 1 0 0 1 1 0 1 Inserted Wait States 0 1 2 3 4 6 8 WAIT Pin Ignored Enabled Enabled Enabled Enabled Enabled Enabled Burst Cycle (Excluding First Cycle) Number of States Per Data Transfer WAIT Pin 2 2 3 4 4 6 8 10 Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled
10 (Initial value) Enabled
1 0 . 2 . 5 Individual Memory Control Register (MCR) The individual memory control register (MCR) is a 16-bit read/write register that specifies RAS and CAS timing and burst control for DRAM (area 3 only), synchronous DRAM (areas 2 and 3),
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and pseudo-SRAM, specifies address multiplexing, and controls refresh. This enables direct connection of DRAM, synchronous DRAM and pseudo-SRAM without external circuits. MCR is initialized to H'0000 by a power-on reset, but is not initialized by a manual reset or in standby mode. Bits TPC1-TPC0, RCD1-RCD0, TRWL1-TRWL0, TRAS1-TRAS0, BE, SZ, AMX1-AMX0, and EDOMODE are written to in the initialization after a power-on reset and are not then modified again. When RFSH and RMODE are written to, write the same values to the other bits. When using DRAM, pseudo-SRAM, and synchronous DRAM, do not access areas 2 and 3 until this register is initialized.
Bit: Bit name: 15 TPC1 0 R/W: Bit: Bit name: Initial value: R/W: R/W 7 -- 0 R 14 TPC0 0 R/W 6 BE 0 R/W 13 RCD1 0 R/W 5 SZ 0 R/W 12 RCD0 0 R/W 4 AMX1 0 R/W 11 TRWL1 0 R/W 3 AMX0 0 R/W 10 TRWL0 0 R/W 2 RFSH 0 R/W 9 TRAS1 0 R/W 1 RMODE 0 R/W 8 TRAS0 0 R/W 0 EDO MODE 0 R/W
Bits 15 and 14--RAS Precharge Time (TPC1, TPC0): When DRAM interface is selected as connected memory, the TPC bits set the minimum number of cycles until the next RAS assertion after RAS negation. When synchronous DRAM interface is selected, they set the minimum number of cycles until output of the next bank-active command after precharge. When pseudoSRAM interface is selected, they set the minimum number of cycles until the next CE assertion after CE negation.
Description Bit 15: TPC1 0 Bit 14: TPC0 0 1 1 0 1 Normally 1 cycle (Initial value) 2 cycles 3 cycles 4 cycles Immediately after SelfRefresh 2 cycles (Initial value) 5 cycles 8 cycles 11 cycles
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Bits 11 and 10--Write-Precharge Delay (TRWL1, TRWL0): These bits set the synchronous DRAM write-precharge delay time. This designates the time between the end of a write cycle and the next bank-active command. This is valid only when synchronous DRAM is connected. After the write cycle, the next bank-active command is not issued for the period TPC + TRWL.
Bit 11: TRWL1 Bit 10: TRWL0 Description 0 0 1 1 0 1 1 cycle value) 2 cycles 3 cycles Reserved (cannot be set) (Initial
Bits 9 and 8--CAS-Before-RAS Refresh RAS Assert Time (TRAS1, TRAS0): When DRAM interface is selected as connected memory, the TRAS bits set the RAS assertion period for CASbefore-RAS refreshes. When pseudo-SRAM interface is selected, they set the OE/RFSH assertion period for auto-refreshes. When synchronous DRAM interface is selected, no bank-active command is issued during the period TPC + TRAS after an auto-refresh command. In the SH7708, set the same values in the TRAS bits in MCR and DCR.
Bit 9: TRAS1 0 Bit 8: TRAS0 0 1 1 0 1 Description 2 cycles value) 3 cycles 4 cycles 5 cycles (Initial
Bit 7--Reserved: This bit always reads 0. The write value should always be 0. Bit 6--Burst Enable (BE): Specifies whether to conduct a burst access of DRAM or pseudoSRAM. When accessing synchronous DRAM, burst access is always carried out, regardless of this bit's designation.
Bit 6: BE 0 1 Description Burst disabled value) (Initial
With DRAM interface, high-speed page mode access With pseudo-SRAM interface, continuous data transfer in static column mode
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Bit 5--Memory Data Size (SZ): Specifies the memory data bus size for DRAM, synchronous DRAM, and pseudo-SRAM. Always set this bit to 1 when synchronous DRAM is used. Takes precedence over the BCR2 register designation.
Bit 5: SZ 0 1 Description Word (16-bit) value) Longword (32-bit) (Initial
Bits 4 and 3--Address Multiplex (AMX1, AMX0): These bits specify address multiplexing for DRAM and synchronous DRAM. The actual address shift value differs between DRAM interface and synchronous DRAM interface. For DRAM Interface:
Bit 4: AMX1 0 Bit 3: AMX0 0 1 1 0 1 Description 8-bit column address product value) 9-bit column address product 10-bit column address product 11-bit column address product (Initial
For Synchronous DRAM Interface:
Bit 4: AMX1 0 Bit 3: AMX0 0 1 1 0 1 Description 16-Mbit product (1M x 16 bits) value) 16-Mbit product (2M x 8 bits) 16-Mbit product (4M x 4 bits) 4-Mbit product (256k x 16 bits) (Initial
Bit 2--Refresh Control (RFSH): Determines whether or not refreshing of DRAM, synchronous DRAM, and pseudo-SRAM is performed. The timer for generation of the refresh request frequency can also be used as an interval timer.
Bit 2: RFSH 0 1 Description No refresh value) Refresh (Initial
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Bit 1--Refresh Mode (RMODE): Selects whether to perform an ordinary refresh or a self-refresh when the RFSH bit is 1. When the RFSH bit is 1 and this bit is 0, a CAS-before-RAS refresh or an auto-refresh is performed on DRAM, synchronous DRAM or pseudo-SRAM at the period set by the refresh-related registers RTCNT, RTCOR and RTCSR. When a refresh request occurs during an external bus cycle, the bus cycle will be ended and the refresh cycle performed. When the RFSH bit is 1 and this bit is also 1, the DRAM, synchronous DRAM or pseudo-SRAM will wait for the end of any executing external bus cycle before going into a self-refresh. All refresh requests to memory that is in the self-refresh state are ignored.
Bit 1: RMODE 0 1 Description CAS-before-RAS refresh (RFSH must be 1) value) Self-refresh (RFSH must be 1) (Initial
Bit 0-- Extended Data Out (EDOMODE): Specifies the timing of data sampling during data reads when using DRAM in EDO mode. Operating timing of memory other than DRAM does not change even if this bit is set. This bit is valid only for DRAM connected to area 3. Do not set this bit to 1 when using synchronous DRAM or pseudo-SRAM.
Bit 0: EDOMODE Description 0 Set when using normal DRAM. Data is sampled during read cycle on the falling edge of CKIO. (Initial value) Set when using EDO mode DRAM. Data is sampled during read cycle on the rising edge of CKIO. Also, RAS signal negation is delayed 1/2 a CKIO machine cycle.
1
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1 0 . 2 . 6 DRAM Control Register (DCR) The DRAM area control register (DCR) is a 16-bit read/write register that specifies RAS and CAS timing and burst control for DRAM connected to area 2. It also specifies address multiplexing and controls refreshing. When DRAM is connected to area 2, the bus width is fixed at 16 bits. In such cases, set the area 3 bus width to 16 bits as well. Other areas should be 8 bits or 16 bits. DCR is initialized to H'0000 by a power-on reset, but is not initialized by a manual resets or in standby mode. Do not access external memory outside area 2 until initialization of this register is complete.
Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: 15 TPC1 0 R/W 7 -- 0 R 14 TPC0 0 R/W 6 BE 0 R/W 13 RCD1 0 R/W 5 -- 0 R 12 RCD0 0 R/W 4 AMX1 0 R/W 11 -- 0 R 3 AMX0 0 R/W 10 -- 0 R 2 RFSH 0 R/W 9 TRAS1 0 R/W 1 RMODE 0 R/W 8 TRAS0 0 R/W 0 -- 0 R
Bits 15 and 14--RAS Precharge Time (TPC1, TPC0): These bits set the RAS precharge time for the DRAM connected to area 2.
Description Bit 15: TPC1 0 Bit 14: TPC0 0 1 1 0 1 Normally 1 cycle (Initial value) 2 cycles 3 cycles 4 cycles Immediately after SelfRefresh 2 cycles (Initial value) 5 cycles 8 cycles 11 cycles
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Bits 13 and 12--RAS-CAS Delay (RCD1, RCD0): These bits set the RAS-CAS delay time for the DRAM connected to area 2.
Bit 13: RCD1 0 Bit 12: RCD0 0 1 1 0 1 Description 1 cycle value) 2 cycles 3 cycles 4 cycles (Initial
Bits 9 and 8--CAS-Before-RAS Refresh RAS Assert Time (TRAS1, TRAS0): These bits set the RAS assert period for CAS-before-RAS refreshing of the DRAM connected to area 2. In the SH7708, set the same values in the TRAS bits in MCR and DCR.
Bit 9: TRAS1 0 Bit 8: TRAS0 0 1 1 0 1 Description 2 cycles value) 3 cycles 4 cycles 5 cycles (Initial
Bit 6--Burst Enable (BE): Specifies whether to conduct a burst access of the DRAM connected to area 2.
Bit 6: BE 0 1 Description Burst disabled value) High-speed page mode access (Initial
Bits 4 and 3--Address Multiplex (AMX1, AMX0): These bits specify address multiplexing for the DRAM connected to area 2.
Bit 4: AMX1 0 Bit 3: AMX0 0 1 1 0 1 Description 8-bit column address product value) 9-bit column address product 10-bit column address product 11-bit column address product (Initial
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Bit 2--Refresh Control (RFSH): Determines whether or not refreshing of the DRAM connected to area 2 is performed.
Bit 2: RFSH 0 1 Description No refresh value) Refresh (Initial
Bit 1--Refresh Mode (RMODE): Selects the refresh mode for the DRAM connected to area 2.
Bit 1: RMODE 0 1 Description CAS-before-RAS refresh (RFSH must be 1) value) Self-refresh (RFSH must be 1) (Initial
1 0 . 2 . 7 PCMCIA Control Register (PCR) The PCMCIA control register (PCR) is a 16-bit read/write register that specifies the OE and WE signal assert/negate timing for PCMCIA interfaces connected to areas 5 and 6. The OE and WE signal assert pulse widths are designated by the WCR2 wait control bits. This register is initialized to H'0000 by a power-on reset, but is not initialized by a manual reset or in standby mode, and retains its contents.
Bit: Bit name: Initial value: R/W: Bit: 15 -- 0 R 7 14 -- 0 R 6 13 -- 0 R 5 12 -- 0 R 4 11 -- 0 R 3 10 -- 0 R 2 9 -- 0 R 1 8 -- 0 R 0
Bit name: A5TED1 A5TED0 A6TED1 A6TED0 A5TEH1 A5TEH0 A6TEH1 A6TEH0 Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W
Bits 15 to 8--Reserved: These bits always read 0. The write value should always be 0.
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Bits 7 and 6--Area 5 Address OE/WE Assert Delay (A5TED1, A5TED0): These bits specify the address to OE/WE assert delay time for the PCMCIA interface connected to area 5.
Bit 7: A5TED1 Bit 6: A5TED0 Description 0 0 1 1 0 1 0.5 cycle delay value) 1.5 cycle delay 2.5 cycle delay 3.5 cycle delay (Initial
Bits 5 and 4--Area 6 Address OE/WE Assert Delay (A6TED1, A6TED0): These bits specify the address to OE/WE assert delay time for the PCMCIA interface connected to area 6.
Bit 5: A6TED1 Bit 4: A6TED0 Description 0 0 1 1 0 1 0.5 cycle delay value) 1.5 cycle delay 2.5 cycle delay 3.5 cycle delay (Initial
Bits 3 and 2--Area 5 OE/WE Negate Address Delay (A5TEH1, A5TEH0): These bits specify the OE/WE negate address delay time for the PCMCIA interface connected to area 5.
Bit 3: A5TEH1 Bit 2: A5TEH0 Description 0 0 1 1 0 1 0.5 cycle delay value) 1.5 cycle delay 2.5 cycle delay 3.5 cycle delay (Initial
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Bits 1 and 0--Area 6 OE/WE Negate Address Delay (A6TEH1, A6TEH0): These bits specify the OE/WE negate address delay time for the PCMCIA interface connected to area 6.
Bit 1: A6TEH1 Bit 0: A6TEH0 Description 0 0 1 1 0 1 0.5 cycle delay value) 1.5 cycle delay 2.5 cycle delay 3.5 cycle delay (Initial
1 0 . 2 . 8 Synchronous DRAM Mode Register (SDMR) The synchronous DRAM mode register (SDMR) is written to via the synchronous DRAM address bus and is a virtual 8-bit write-only register. It sets synchronous DRAM mode for areas 2 and 3. SDMR settings must be made before synchronous DRAM is accessed. Writes to the synchronous DRAM mode register use the address bus rather than the data bus. If the value to be set is X and the SDMR address is Y, the value X is written in the synchronous DRAM mode register by writing in address X + Y. Since A0 of the synchronous DRAM is connected to A2 of the chip and A1 of the synchronous DRAM is connected to A3 of the chip, the value actually written to the synchronous DRAM is the X value shifted two bits right. For example, when H'0230 is written to the SDMR register of area 2, random data is written to the address H'FFFD000 (address Y) + H'08C0 (value X), or H'FFFFD8C0. As a result, H'0230 is written to the SDMR register. When H'0230 is written to the SDMR register of area 3, random data is written to the address H'FFFE000 (address Y) + H'08C0 (value X) or H'FFFFE8C0. As a result, H'0230 is written to the SDMR register. The range for value X is H'000 to H'0FFC.
Address bits Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: -- W -- W -- W -- W -- W -- W -- -- -- -- -- -- 7 31 SDMR address * ** * * * * * * * * * * * ** * * * * * * * * * * 6 5 -- -- 4 -- W* 3 -- W* 2 -- W 1 -- W 0 12 11 10 9 8
Note: Depending on the type of synchronous DRAM.
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1 0 . 2 . 9 Refresh Timer Control/Status Register (RTCSR) The refresh timer control/status register (RTSCR) is a 16-bit read/write register that specifies the refresh cycle, whether to generate an interrupt, and the cycle of that interrupt. RTSCR is initialized to H'0000 by a power-on reset, but is not initialized by a manual reset or in standby mode. Note: The method for writing to RTCOR is different from that for general registers to prevent inadvertent overwriting. Using a word transfer instruction, place B'10100101 in the upper byte and the write data in the lower byte. For details, see section 10.2.13, Cautions on Accessing Refresh Control Related Registers.
Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: 15 -- 0 R 7 CMF 0 R/W 14 -- 0 R 6 CMIE 0 R/W 13 -- 0 R 5 CKS2 0 R/W 12 -- 0 R 4 CKS1 0 R/W 11 -- 0 R 3 CKS0 0 R/W 10 -- 0 R 2 OVF 0 R/W 9 -- 0 R 1 OVIE 0 R/W 8 -- 0 R 0 LMTS 0 R/W
Bits 15 to 8--Reserved: These bits always read 0. Bit 7--Compare Match Flag (CMF): Status flag that indicates that the values of RTCNT and RTCOR match.
Bit 7: CMF 0 Description The values of RTCNT and RTCOR do not match. Clearing condition: When a refresh is performed after 0 has been written in CMF and RFSH = 1 and RMODE = 0 (to perform a CBR refresh). (Initial value) The values of RTCNT and RTCOR match. Setting condition: RTCNT = RTCOR*
1
Note: Contents do not change when 1 is written to CMF.
Bit 6--Compare Match Interrupt Enable (CMIE): Enables or disables an interrupt request caused when the CMF bit in RTCSR is set to 1. Do not set this bit to 1 when using CAS-before-RAS refreshing or auto-refreshing.
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Bit 6: CMIE 0 1
Description Disables the interrupt request caused by CMF value) Enables the interrupt request caused by CMF (Initial
Bits 5 to 3--Clock Select Bits (CKS2-CKS0): These bits select the clock input to RTCNT. The source clock is the external bus clock (CKIO). The RTCNT count clock is CKIO scaled by the specified ratio.
Bit 5: CKS2 Bit 4: CKS1 Bit 3: CKS0 Description 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Disables clock input value) Bus clock (CKIO)/4 CKIO/16 CKIO/64 CKIO/256 CKIO/1024 CKIO/2048 CKIO/4096 (Initial
Bit 2--Refresh Count Overflow Flag (OVF): Status flag that indicates when the number of refresh requests indicated in the refresh count register (RFCR) exceeds the limit set in the LMTS bit in RTCSR.
Bit 2: OVF 0 Description RFCR has not exceeded the count limit value set in LMTS Clearing Condition: When 0 is written to OVF value) (Initial
1
RFCR has exceeded the count limit value set in LMTS Setting Condition: When the RFCR value has exceeded the count limit value set in LMTS*
Note: Contents do not change when 1 is written to OVF.
Bit 1--Refresh Count Overflow Interrupt Enable (OVIE): Selects whether to suppress generation of interrupt requests by OVF when the OVF bit of RTCSR is set to 1.
221
Bit 1: OVIE 0 1
Description Disables interrupt requests caused by OVF value) Enables interrupt requests caused by OVF (Initial
Bit 0--Refresh Count Overflow Limit Select (LMTS): Indicates the count limit value to be compared to the number of refreshes indicated in the refresh count register (RFCR). When the value RFCR exceeds the value specified by LMTS, the OVF flag is set.
Bit 0: LMTS 0 1 Description Count limit value is 1024 value) Count limit value is 512 (Initial
1 0 . 2 . 1 0 Refresh Timer Counter (RTCNT) RTCNT is a 16-bit read/write register containing an 8-bit counter that counts up on an input clock. The clock select bits (CKS2-CKS0) in RTCSR select the input clock. When RTCNT matches RTCOR, the OVF bit in RTCSR is set and RTCNT is cleared. RTCNT is initialized to H'00 by a power-on reset; it continues incrementing after a manual reset; it is not initialized in standby mode, but retains its contents. Note: The method for writing to RTCOR is different from that for general registers to prevent inadvertent overwriting. Using a word transfer instruction, place B'10100101 in the upper byte and the write data in the lower byte. For details, see section 10.2.13, Cautions on Accessing Refresh Control Related Registers.
Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 15 -- 0 R 7 14 -- 0 R 6 13 -- 0 R 5 12 -- 0 R 4 11 -- 0 R 3 10 -- 0 R 2 9 -- 0 R 1 8 -- 0 R 0
222
1 0 . 2 . 1 1 Refresh Time Constant Register (RTCOR) The refresh time constant register (RTCOR) is a 16-bit read/write register. The values of RTCOR and RTCNT (lower 8 bits) are constantly compared. When the values match, the compare match flag (CMF) in RTCSR is set and RTCNT is cleared to 0. When the refresh bit (RFSH) in the individual memory control register (MCR) is set to 1 and the refresh mode is set to CAS-beforeRAS refresh, a memory refresh cycle occurs when the CMF bit is set. RTCOR is initialized to H'00 by a power-on reset. It is not initialized by a manual reset or in standby mode, but retains its contents. Note: The method for writing to RTCOR is different from that for general registers to prevent inadvertent overwriting. Using a word transfer instruction, place B'10100101 in the upper byte and the write data in the lower byte. For details, see section 10.2.13, Cautions on Accessing Refresh Control Related Registers.
Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 15 -- 0 R 7 14 -- 0 R 6 13 -- 0 R 5 12 -- 0 R 4 11 -- 0 R 3 10 -- 0 R 2 9 -- 0 R 1 8 -- 0 R 0
1 0 . 2 . 1 2 Refresh Count Register (RFCR) The refresh count register (RFCR) is a 16-bit read/write register containing a 10-bit counter that increments every time RTCOR and RTCNT match. When RFCR exceeds the count limit value set by the LMTS bit in RTCSR, the OVF bit in RTCSR is set and RFCR is cleared. RFCR is initialized to H'0000 by a power-on reset. It is not initialized by a manual reset or in standby mode, but retains its contents. Note: The method for writing to RFCR is different from that for general registers to prevent inadvertent overwriting. Using a word transfer instruction, place B'101001 in the top 6 bits of the upper byte, and the write data in the remaining bits. For details, see section 10.2.13, Cautions on Accessing Refresh Control Related Registers.
223
Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W:
15 -- 0 R 7
14 -- 0 R 6
13 -- 0 R 5
12 -- 0 R 4
11 -- 0 R 3
10 -- 0 R 2
9
8
0 R/W 1
0 R/W 0
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
1 0 . 2 . 1 3 Cautions on Accessing Refresh Control Related Registers RFCR, RTCSR, RTCNT, and RTCOR require that a specific code be appended to the data when it is written to prevent data from being mistakenly overwritten by program overruns or other write operations (figure 10.5). Perform reads and writes using the following methods: 1. When writing to RFCR, RTCSR, RTCNT, or RTCOR, use only word transfer instructions. Byte transfer instructions cannot be used. When writing to RTCNT, RTCSR, or RTCOR, place B'10100101 in the upper byte and the write data in the lower byte. When writing to RFCR, place B'101001 in the top 6 bits and the write data in the remaining bits, as shown in figure 10.5. 2. When reading from RFCR, RTCSR, RTCNT, or RTCOR, use a 16-bit access. 0 is read from undefined bits.
15 RTCSR, RTCNT, RTCOR RFCR 1 15 1 0 1 0 0 0 1 0 0 1 0 87 1 Write data 0 Write data 0
10 9 1
Figure 10.5
Writing to RFCR, RTCSR, RTCNT, and RTCOR
224
10.3
BSC Operation
1 0 . 3 . 1 Endian/Access Size and Data Alignment The SH7708 Seires supports both big-endian mode, in which the 0 address is the most significant byte in the byte data, and little-endian mode, in which the 0 address is the least significant byte. Switching between the two is designated by an external pin (MD5 pin) at the time of a power-on reset. After a power-on reset, big-endian mode is set when MD5 is low, and little-endian mode is set when MD5 is high. Three data bus widths are available for normal memory (byte, word, longword) and two data bus widths (word and longword) for DRAM and pseudo-SRAM. Only longword is available for synchronous DRAM. For the PCMCIA interface, choose from byte and word. This means data alignment is done by matching the device's data width and endian. The access unit must also be matched to the device's bus width. This also means that when longword data is read from a bytewidth device, four read operations must be executed. In the SH7708 Series, data alignment and conversion of data length is performed automatically between the respective interfaces. Tables 10.6 through 10.11 show the relationship between endian, device data width, and access unit. Table 10.6 32-Bit External Device/Big Endian Access and Data Alignment
Data Bus Strobe Signal WE3 , WE2 , WE1 , WE0 , CASHH , CASHL , CASLH , CASLL, DQMUU DQMUL DQMLU DQMLL Asserted -- -- -- -- -- -- --
Operation Address 0 byte access Address 1 byte access Address 2 byte access Address 3 byte access Address 0 word access Address 2 word access Address 0 longword access
D31-D24D23-D16D15-D8D7-D0 Data 7-0 -- -- -- Data 15-8 -- Data 31-24 -- Data 7-0 -- -- Data 7-0 -- Data 23-16 -- -- Data 7-0 -- -- Data 15-8 Data 15-8 -- -- -- Data 7-0 -- Data 7-0 Data 7-0
Asserted -- -- --
Asserted -- -- Asserted --
Asserted Asserted -- -- --
Asserted Asserted
Asserted Asserted Asserted Asserted
225
Table 10.7 16-Bit External Device/Big Endian Access and Data Alignment
Data Bus Strobe Signal
Operation Address 0 byte access Address 1 byte access Address 2 byte access Address 3 byte access Address 0 word access Address 2 word access
WE3 , WE2 , WE1 , WE0 , D31- D23- CASHH , CASHL , CASLH , CASLL, D 2 4 D 1 6 D 15-D 8D 7-D 0 DQMUU DQMUL DQMLU DQMLL -- -- -- -- -- -- -- -- -- -- -- -- -- Data 7-0 -- Data 7-0 -- Data 15-8 Data 15-8 Data 31-24 Data 15-8 -- Data 7-0 -- Data 7-0 Data 7-0 Data 7-0 Data 23-16 Data 7-0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- Asserted -- -- Asserted
Asserted -- -- Asserted
Asserted Asserted Asserted Asserted Asserted Asserted
Address 0 1st time -- longword (address access 0) 2nd time -- (address 2)
--
--
--
Asserted Asserted
226
Table 10.8 8-Bit External Device/Big Endian Access and Data Alignment
Data Bus D31- D23- D15- D24 D16 D8 D7-D0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- Data 7-0 Data 7-0 Data 7-0 Data 7-0 Data 15-8 Data 7-0 Strobe Signal WE3 , WE2 , WE1 , WE0 , CASHH , CASHL , CASLH , CASLL, DQMUU DQMUL DQMLU DQMLL -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Asserted Asserted Asserted Asserted Asserted
Operation Address 0 byte access Address 1 byte access Address 2 byte access Address 3 byte access Address 0 word access
1st time -- (address 0) 2nd time -- (address 1)
--
--
--
--
--
Asserted
Address 2 word access
1st time -- (address 2) 2nd time -- (address 3)
--
--
Data 15-8 Data 7-0
--
--
--
Asserted
--
--
--
--
--
Asserted
Address 0 longword access
1st time -- (address 0) 2nd time -- (address 1) 3rd time -- (address 2) 4th time -- (address 3)
--
--
Data 31-24 Data 23-16 Data 15-8 Data 7-0
--
--
--
Asserted
--
--
--
--
--
Asserted
--
--
--
--
--
Asserted
--
--
--
--
--
Asserted
227
Table 10.9 32-Bit External Device/Little Endian Access and Data Alignment
Data Bus Strobe Signal WE3 , WE2 , WE1 , WE0 , CASHH , CASHL , CASLH , CASLL, DQMUU DQMUL DQMLU DQMLL -- -- -- -- -- -- Asserted
Operation
D31-D24D23-D16D15-D8 D7-D0 -- -- Data 7-0 -- -- Data 7-0 Data 23-16 -- Data 7-0 -- -- Data 15-8 -- Data 15-8 Data 7-0 -- -- -- Data 7-0 -- Data 7-0
Address 0 -- byte access Address 1 -- byte access Address 2 -- byte access Address 3 Data byte access 7-0 Address 0 -- word access Address 2 Data word access 15-8 Address 0 longword access Data 31-24
Asserted -- -- --
Asserted -- --
Asserted -- -- --
Asserted Asserted --
Asserted Asserted --
Asserted Asserted Asserted Asserted
228
Table 10.10
16-Bit External Device/Little Endian Access and Data Alignment
Data Bus D31- D23- D 2 4 D 1 6 D15-D 8D 7-D 0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- Data 7-0 -- Data 7-0 Data 15-8 Data 15-8 Data 15-8 Data 31-24 Data 7-0 -- Data 7-0 -- Data 7-0 Data 7-0 Data 7-0 Data 23-16 Strobe Signal WE3 , WE2 , WE1 , WE0 , CASHH , CASHL , CASLH , CASLL, DQMUU DQMUL DQMLU DQMLL -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Asserted
Operation Address 0 byte access Address 1 byte access Address 2 byte access Address 3 byte access Address 0 word access Address 2 word access
Asserted -- -- Asserted
Asserted -- Asserted Asserted Asserted Asserted Asserted Asserted
Address 0 1st time -- longword (address access 0) 2nd time -- (address 2)
--
--
--
Asserted Asserted
229
Table 10.11
8-Bit External Device/Little Endian Access and Data Alignment
Data Bus D31- D23- D15- D24 D16 D8 D7-D0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- Data 7-0 Data 7-0 Data 7-0 Data 7-0 Data 7-0 Strobe Signal WE3 , WE2 , WE1 , WE0 , CASHH , CASHL , CASLH , CASLL, DQMUU DQMUL DQMLU DQMLL -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Asserted Asserted Asserted Asserted Asserted
Operation Address 0 byte access Address 1 byte access Address 2 byte access Address 3 byte access
Address 0 1st time -- word (address access 0) 2nd time -- (address 1) Address 2 1st time -- word (address access 2) 2nd time -- (address 3) Address 0 1st time -- longword (address access 0) 2nd time -- (address 1) 3rd time -- (address 2) 4th time -- (address 3)
--
--
Data 15-8 Data 7-0
--
--
--
Asserted
--
--
--
--
--
Asserted
--
--
Data 15-8 Data 7-0
--
--
--
Asserted
--
--
--
--
--
Asserted
--
--
Data 15-8 Data 23-16 Data 31-24
--
--
--
Asserted
--
--
--
--
--
Asserted
--
--
--
--
--
Asserted
230
1 0 . 3 . 2 Description of Areas Area 0: Area 0 physical address bits A28-A26 are 000. Address bits A31-A29 are ignored and the address range is H'00000000 + H'20000000 x n - H'03FFFFFF + H'20000000 x n (n = 0-6, n = 1-6 is the shadow space). Normal memories such as SRAM, ROM, and burst ROM can be connected to this space. Byte, word, or longword can be selected as the bus width using external pins. MD3 and MD4 on a power-on reset. For details, see Memory Size in section 10.1.5. When the Area 0 space is accessed, the CS0 signal is asserted. The RD signal that can be used as OE and the WE0-WE3 signals for write control are also asserted. The number of bus cycles is selected between 0 and 10 wait cycles using the A0W2-A0W0 bits in WCR2. Also, any number of waits can be inserted in each bus cycle by means of the external wait pin (WAIT). When the burst function is used, the bus cycle pitch of the burst cycle is determined within a range of 2-10 according to the number of waits. Area 1: Area 1 physical address bits A28-A26 are 001. Address bits A31-A29 are ignored and the address range is H'04000000 + H'20000000 x n - H'07FFFFFF + H'20000000 x n (n = 0-6, n = 1-6 is the shadow space). Only normal memories like SRAM and ROM can be connected to this space. Byte, word, or longword can be selected as the bus width using the A1SZ1-A1SZ0 bits in BCR2. When the Area 1 space is accessed, the CS1 signal is asserted. The RD signal that can be used as OE and the WE0-WE3 signals for write control are also asserted. The number of bus cycles is selected between 0 and 3 wait cycles using the A12W1-A12W0 bits in WCR2. Also, any number of waits can be inserted in each bus cycle by means of the external wait pin (WAIT). Area 2: Area 2 physical address bits A28-A26 are 010. Address bits A31-A29 are ignored and the address range is H'08000000 + H'20000000 x n - H'0BFFFFFF + H'20000000 x n (n = 0-6, n = 1-6 is the shadow space). Normal memories like SRAM and ROM, as well as DRAM and synchronous DRAM, can be connected to this space. Byte, word, or longword can be selected as the bus width using the A2SZ1-A2SZ0 bits in BCR2 for normal memory. For synchronous DRAM, set longword using the SZ bit in MCR. When DRAM is connected to area 2, the bus width is fixed at 16 bits. The bus width for area 3 also needs to be 16 bits. When the area 2 space is accessed, the CS2 signal is asserted. When normal memories are connected, the RD signal that can be used as OE and the WE0-WE3 signals for write control are also asserted and the number of bus cycles is selected between 0 and 3 wait cycles using the A12W1 to A12W0 bits in WCR2. When normal memory is connected, only, any number of waits can be inserted in each bus cycle by means of the external wait pin (WAIT).
231
When synchronous DRAM is connected, the RAS signal, CAS signal, RD/WR signal, and byte control signals DQMHH, DQMHL, DQMLH, and DQMLL are all asserted and addresses multiplexed. Control of RAS, CAS, data timing, and address multiplexing is set with MCR. When DRAM is connected, the RAS2 signal, CAS2H signal, CAS2L signal, and RD/WR signal are all asserted and addresses multiplexed. Control of RAS2, CAS, data timing, and address multiplexing is set with DCR. Area 3: Area 3 physical address bits A28-A26 are 011. Address bits A31-A29 are ignored and the address range is H'0C000000 + H'20000000 x n - H'0FFFFFFF + H'20000000 x n (n = 0-6, n = 1-6 is the shadow space). Normal memories like SRAM and ROM, as well as DRAM, pseudo-SRAM, and synchronous DRAM, can be connected to this space. Byte, word or longword can be selected as the bus width using the A3SZ1-A3SZ0 bits in BCR2 for normal memory. For DRAM and pseudo-SRAM, word or longword can be selected using the SZ bit in MCR. When synchronous DRAM is connected, set to longword using the SZ bit in MCR. When area 3 space is accessed, CS3 is asserted. When normal memories are connected, the RD signal that can be used as OE and the WE0-WE3 signals for write control are asserted and the number of bus cycles is selected between 0 and 3 wait cycles using the A3W1-A3W0 bits in WCR2. When normal memory is connected, only, any number of waits can be inserted in each bus cycle by means of the external wait pin (WAIT). When synchronous DRAM is connected, the RAS signal, CAS signal, RD/WR signal, and byte control signals DQMHH, DQMHL, DQMLH, and DQMLL are all asserted and addresses multiplexed. When DRAM is connected, the RAS signal, CASHH signal, CASHL signal, CASLH signal, CASLL signal, and RD/WR signal are all asserted and addresses multiplexed. When pseudo-SRAM is connected, the CE signal, OE/RFSH signal, and WE0 , WE1 , WE2, and WE3 signals are asserted. For all of these, control of RAS , CAS , and data timing and of address multiplexing is set with MCR. Area 4: Area 4 physical address bits A28-A26 are 100. Address bits A31-A29 are ignored and the address range is H'10000000 + H'20000000 x n - H'13FFFFFF + H'20000000 x n (n = 0-6, n = 1-6 is the shadow space). Only normal memories like SRAM and ROM can be connected to this space. Byte, word, or longword can be selected as the bus width using the A4SZ1-A4SZ0 bits in BCR2. When the area 4 space is accessed, the CS4 signal is asserted. The RD signal that can be used as OE and the WE0-WE3 signals for write control are also asserted. The number of bus cycles is selected between 0 and 10 wait cycles using the A4W2-A4W0 bits in WCR2. Also, any number of waits can be inserted in each bus cycle by means of the external wait pin (WAIT).
232
Area 5: Area 5 physical address bits A28-A26 are 101. Address bits A31-A29 are ignored and the address range is the 64 Mbytes at H'14000000 + H'20000000 x n - H'17FFFFFF + H'20000000 x n (n = 0-6, n = 1-6 is the shadow space). Normal memories like SRAM and ROM as well as burst ROM and PCMCIA interfaces can be connected to this space. PCMCIA interfaces only use their IC memory card interface, so the address range becomes the 32 Mbytes at H'14000000 + H'20000000 x n - H'15FFFFFF + H'20000000 x n (n = 0-6, n = 1-6 is the shadow space). For normal memory and burst ROM, byte, word, or longword can be selected as the bus width using the A5SZ1-A5SZ0 bits in BCR2. For the PCMCIA interface, byte, and word can be selected as the bus width using the A5SZ1-A5SZ0 bits in BCR2. When the area 5 space is accessed and normal memory is connected, the CS5 signal is asserted. The RD signal that can be used as OE and the WE0-WE3 signals for write control are also asserted. When the PCMCIA interface is used, the CE1 signal, CE2 signal, OE signal, and WE signal are asserted. The number of bus cycles is selected between 0 and 10 wait cycles using the A5W2-A5W0 bits in WCR2. Also, any number of waits can be inserted in each bus cycle by means of the external wait pin (WAIT). When a burst function is used, the bus cycle pitch of the burst cycle is determined within a range of 2-10 according to the number of waits. The setup and hold times of address/CE1A/CE2A for the read/write strobe signals can be set within a range of 0.5-3.5 cycles using the A5TED1-A5TED0 and A5TEH1-A5TEH0 bits in the PCR register. Area 6: Area 6 physical address bits A28-A26 are 110. Address bits A31-A29 are ignored and the address range is the 64 Mbytes at H'18000000 + H'20000000 x n - H'1BFFFFFF + H'20000000 x n (n = 0-6, n = 1-6 is the shadow space). Normal memories like SRAM and ROM as well as burst ROM and PCMCIA interfaces can be connected to this space. When the PCMCIA interface is used, the IC memory card interface address range is the 32 Mbytes at H'18000000 + H'20000000 x n - H'19FFFFFF + H'20000000 x n and the I/O card interface address range is the 32 Mbytes at H'1A000000 + H'20000000 x n - H'1BFFFFFF + H'20000000 x n (n = 0-6, n = 1-6 is the shadow space). For normal memory and burst ROM, byte, word, or longword can be selected as the bus width using the A6SZ1-A6SZ0 bits in BCR2. For the PCMCIA interface, byte, and word can be selected as the bus width using the A6SZ1-A6SZ0 bits in BCR2. When the area 6 space is accessed and normal memory is connected, the CS6 signal is asserted. The RD signal that can be used as OE and the WE0-WE3 signals for write control are also asserted. When the PCMCIA interface is used, the CE1B signal, CE2B signal, OE signal, and WE1 , ICORD, and ICOWR signals are asserted.
233
The number of bus cycles is selected between 0 and 10 wait cycles using the A6W2-A6W0 bits in WCR2. Also, any number of waits can be inserted in each bus cycle by means of the external wait pin (WAIT). When the burst function is used, the bus cycle pitch of the burst cycle is determined within a range of 2-10 according to the number of waits. The setup and hold times of address/CE1B/CE2B for the read/write strobe signals can be set within a range of 0.5-3.5 cycles using A6TED1-A6TED0 and A6TEH1-A6TEH0. If PCMCIA is used in area 6, synchronous DRAM is used at the same time, and a synchronous DRAM auto-refresh (CAS-before-RAS refresh) request is issued simultaneously, area 6 card enable signals CS6 and CE2B may be asserted earlier than usual, at the same time as the immediately preceding auto-refresh cycle. When both PCMCIA and synchronous DRAM are used, they should be used in area 5. When area 5 is used, the system design should provide for CS to be asserted early without causing any problems. 1 0 . 3 . 3 Basic Interface Basic Timing: The basic interface of the SH7708 Series uses strobe signal output because mainly SRAM will be directly connected. Figure 10.6 shows the basic timing of normal space accesses. A no-wait normal access is completed in two cycles. The BS signal is asserted for one cycle to indicate the start of a bus cycle. The CSn signal is negated on the T2 clock falling edge to secure the negation period. Therefore, at minimum pitch, there is a half-cycle negation period. There is no access size specification when reading. The correct access start address is output in the least significant bit of the address, but since there is no access size specification, 32 bits are always read in a 32-bit device, and 16 bits in a 16-bit device. When writing, only the WE signal for the byte to be written is asserted. For details, see section 10.3.1, Endian/Access Size and Data Alignment. Read/write for cache fill or copy-back follows the set bus width and transfers a total of 16 bytes continuously. The bus is not released during this transfer. For cache misses that occur during byte or word operand accesses or branching to odd word boundaries, the fill is always performed by longword accesses on the chip-external interface. Write-through area write access and noncacheable read/write access is based on the actual address size.
234
T1
T2
CKIO
A25 to A0
CSn
RD/WR
RD Read D31 to D0
WEn Write D31 to D0
BS
Figure 10.6
Basic Timing of Basic Interface
235
Figures 10.7, 10.8, and 10.9 show examples of connection to 32-, 16-, and 8-bit data width SRAM.
128k x 8 bit SRAM
**** **** **** **** **** **** **** **** **** **** ****
SH7708 Series A18 A2 CSn RD D31
****
A16 A0 CS OE I/O7
D24 WE3 D23
****
****
I/O0 WE
****
D16 WE2 D15
****
****
A16 A0 CS OE I/O7 I/O0 WE
****
D0 WE0
****
****
D8 WE1 D7
****
****
A16 A0 CS OE I/O7 I/O0 WE
****
A16 A0 CS OE I/O7 I/O0 WE
Figure 10.7
Example of 32-Bit Data Width SRAM Connection
236
****
SH7708 Series
**** **** ****
128k x 8 bit SRAM
**** **** **** ****
A17 A1 CSn RD D15
****
A16 A0 CS OE I/O7
D8 WE1 D7
**** ****
****
I/O0 WE
****
D0 WE0
A16 A0 CS OE I/O7 I/O0 WE
Figure 10.8
Example of 16-Bit Data Width SRAM Connection
128k x 8 bit SRAM
SH7708 Series
**** **** ****
****
****
D0 WE0
****
I/O0 WE
Figure 10.9
Example of 8-Bit Data Width SRAM Connection
237
****
A0 CSn RD D7
A0 CS OE I/O7
****
A16
****
A16
Wait State Control: Wait state insertion on the basic interface can be controlled by the WCR2 settings. If the WCR2 wait specification bits corresponding to a particular area are not zero, a software wait is inserted in accordance with that specification. For details, see section 10.2.4, Wait Control Register 2 (WCR2). The specified number of Tw cycles is inserted as wait cycles using the basic interface wait timing shown in figure 10.10.
T1
Tw
T2
CKIO
A25 to A0
CSn
RD/WR
RD Read D31 to D0
WEn Write D31 to D0
BS
Figure 10.10
Basic Interface Wait Timing (Software Wait Only)
238
When software wait insertion is specified by WCR2, the external wait input WAIT signal is also sampled. WAIT pin sampling is shown in figure 10.11. A 2-cycle wait is specified as a software wait. Sampling is performed at the transition from the Tw state to the T2 state; therefore, the WAIT signal has no effect if asserted in the T1 cycle or the first Tw cycle. The WAIT signal is sampled on the rising edge of the clock. WAIT is a synchronous signal.
Wait states inserted by WAIT signal T1 Tw Tw Tw T2
CKIO A25 to A0 CSn RD/WR RD Read D31 to D0 WEn Write D31 to D0 WAIT BS
Figure 10.11
Basic Interface Wait State Timing (Wait State Insertion by WAIT Signal)
239
1 0 . 3 . 4 DRAM Interface DRAM Connection Method: When the memory type bits (DRAMTP2-DRAMTP0) in BCR1 are set to 100, area 3 becomes DRAM space; when set to 101, area 2 and area 3 become DRAM space. The DRAM interface function can then be used to connect the SH7708 Series directly to DRAM. 16 or 32 bits can be selected as the interface data width for area 3 when bits DRAMTP2 to DRAMTP0 are set to 100, and 16 bits can be used for both area 2 and area when bits DRAMTP2 to DRAMTP0 are set to 101. 2-CAS 16-bit DRAMs can be connected, since CAS is used to control byte access. Signals used for connection when DRAM is connected to area 3 are RAS, CASHH, CASHL, CASLH, CASLL , and RD/WR. CASHH and CASHL are not used when the data width is 16 bits. When DRAM is connected to areas 2 and 3, the signals for area 2 DRAM connection are RAS2, CAS2H, CAS2L, and RD/WR, and those for area 3 DRAM connection are RAS, CASLH, CASLL, and RD/WR. In addition to normal read and write access modes, high-speed page mode is supported for burst access. Also, for DRAM connected to area 3, EDO mode, which enables the DRAM access time to be increased by delaying the data sampling timing by 1/2 clock when reading, is supported in addition to normal read and write access for burst mode.
240
SH7708 Series A10
**** **** ****
256k x 16 bit DRAM A8 A0
****
A2
RAS RD/WR D31
****
RAS OE WE I/O15 I/O0 UCAS LCAS
**** ****
D16 CASHH CASHL D15
****
D0 CASLH CASLL
A8
****
A0
RAS OE WE I/O15
****
I/O0 UCAS LCAS
Figure 10.12
Example of DRAM Connection (32-Bit Data Width)
****
****
241
SH7708 Series
**** **** ****
256k x 16 bit DRAM
**** **** **** ****
A9 A1
A8 A0
****
D0 CASLH CASLL CAS2H CAS2L
****
**** **** ****
RAS RAS2 RD/WR D15
RAS OE WE I/O15 I/O0 UCAS LCAS
A8 A0 RAS OE WE I/O15 I/O0 UCAS LCAS
Figure 10.13
Example of DRAM Connection (16-Bit Data Width)
242
Address Multiplexing: When areas 2 and 3 are designated as DRAM space, address multiplexing is always performed in accesses to DRAM. This enables DRAM, which requires row and column address multiplexing, to be connected directly to the SH7708 Series without using an external address multiplexer circuit. Any of the four multiplexing methods shown below can be selected by setting bits AMX1 and AMX0 in MCR for area 3 DRAM, or bits AMX1 and AMX0 in DCR for area 2 DRAM. The relationship between bits AMX1 and AMX0 and address multiplexing is shown in table 10.12. The address output pins subject to address multiplexing are A15 to A1. Pins A25 to A16 carry the original address. Table 10.12
Setting AMX1 0 AMX0 0
Relationship between AMX1-0 and Address Multiplexing
Number of Column Address Bits Output Timing 8 bits Column address Row address
External Address Pins A1 to A14 A9 to A22 A1 to A14 A10 to A23 A1 to A14 A11 to A24 A1 to A14 A12 to A25 A15 A23 A15 A24 A15 A25 A15 A15
0
1
9 bits
Column address Row address
1
0
10 bits
Column address Row address
1
1
11 bits
Column address Row address
243
Basic Timing: Figure 10.14 shows the basic timing for DRAM access is 3 cycles. Tpc is the precharge cycle, Tr the RAS assert cycle, Tc1 the CAS assert cycle, and Tc2 the read data latch cycle.
Tr CKIO
Tc1
Tc2
(Tpc)
A25 to A16
A15 to A0
RD/WR
RAS
CASxx D31 to D0 (read)
D31 to D0 (write)
BS
CS2 or CS3
Figure 10.14
Basic Timing for DRAM Access
244
Wait State Control: As the clock frequency increases, it becomes impossible to complete all states in one cycle as in basic access. Therefore, provision is made for state extension by using the setting bits in WCR2, MCR, and DCR. The timing with state extension using these settings is shown in figure 10.15. Up to four additional Tpc cycles (cycles used to secure the RAS precharge time) can be inserted by means of the TPC bits in MCR and DCR. However, if there is a DRAM access request immediately after an auto-refresh (CAS-before-RAS refresh), the interval until the next assertion of RAS is 2 cycles, regardless of the values in MCR and DCR. The number of cycles from RAS assertion to CAS assertion can be set to between 1 and 4 by inserting Trw cycles by means of the RCD bits in MCR and DCR. The number of cycles from CAS assertion to the end of the access can be varied between 1 and 3 according to the setting of A1-2W (1,0) or A3W (1,0) in WCR2.
245
Tr
Trw
Trw
Tc1
Tcw
Tc2
(Tpc)
(Tpc)
CKIO
A25 to A16
Row address
A15 to A0
Row address
Column address
RD/WR
RAS
CASxx
D31 to D0 (read)
D31 to D0 (write)
BS
CS2 or CS3
Figure 10.15
DRAM Wait State Timing
246
Burst Access: In addition to the normal DRAM access mode in which a row address is output in each data access, a high-speed page mode is also provided in cases where consecutive accesses are made to the same row. This mode allows fast access to data by outputting the row address only once, then changing only the column address for each subsequent access. Normal access or burst access using high-speed page mode can be selected by means of the burst enable (BE) bit in MCR and DCR. The timing for burst access using high-speed page mode is shown in figure 10.16. In burst transfer, 4 (longword access) or 16 (cache fill or cache write-back) bytes of data are bursttransferred in a 16-bit bus size. With a 32-bit bus size, 16 bytes of data are burst-transferred (cache fill or cache write-back). In a 16-byte burst transfer (cache fill), the first access comprises a longword that includes the data requiring access. The remaining accesses are performed on 16-byte boundary data that includes the relevant data. In burst transfer (cache write-back), sequential writing is performed if first-to-last order for 16-byte boundary data.
247
Tr
Tc1
Tc2
Tc1
Tc2
Tc1
Tc2
Tc1
Tc2
(Tpc)
CKIO
A25 to A16
Row address
A15 to A0
Column address Row address
Column address
Column address
Column address
RD/WR
RAS
CASxx
D31 to D0 (read)
D31 to D0 (write)
BS
CS2 or CS3
Figure 10.16
DRAM Burst Access Timing
248
EDO Mode: In DRAM, an extended data out (EDO) mode is also provided in which, once the CAS signal is asserted while the RAS signal is asserted, even if the CAS signal is negated, data is output to the data bus until the CAS signal is next asserted. (This is in addition to the mode in which data is output to the data bus only while the CAS signal is asserted in a data read cycle.) In the SH7708 Series, the EDO mode bit (EDOMODE) in MCR enables selection, for area 3 DRAM only, of either normal access/burst access using high-speed page mode or EDO mode normal access/burst access. EDO mode normal access is shown in figure 10.17, and burst access in figure 10.18. In EDO mode, the timing for data output to the data bus in a read cycle is extended as far as the next assertion of the CAS signal. This delays the data latch timing by 1/2 cycle to the rising edge of the CKIO clock, enabling the DRAM access time to be increased.
249
Tr
Tc1
Tc2
(Tpc)
CKIO
A25-A16
Row address
A15-A0
Row address
Column address
RD/WR
RAS
CASxx
D31-D0 (Read)
D31-D0 (Write)
BS
CS2 or CS3
Figure 10.17
Normal Access Timing in DRAM EDO Mode
250
Tr
Tc1
Tc2
Tc1
Tc2
Tc1
Tc2
Tc1
Tc2
(Tpc)
CKIO
A25 to A16
Row address
A15 to A0
Column address Row address
Column address
Column address
Column address
RD/WR
RAS
CASxx
D31 to D0 (read)
D31 to D0 (write)
BS
CS2 or CS3
Figure 10.18
Burst Access Timing in DRAM EDO Mode
251
Refresh Timing: The bus state controller includes a function for controlling DRAM refreshing. Refreshing using a CAS-before-RAS cycle can be performed by clearing the RMODE bit to 0 and setting the RFSH bit to 1 in MCR for area 3 DRAM, or by clearing the RMODE bit to 0 and setting the RFSH bit to 1 in DCR for area 2 DRAM. It also supports self-refresh mode. When CAS-before-RAS refresh cycles are executed, refreshing is performed at intervals determined by the input clock selected by bits CKS2-CKS0 in RTCSR, and the value set in RTCOR. The value of bits CKS2-CKS0 in RTCOR should be set so as to satisfy the stipulation for the DRAM refresh interval. First make the settings for RTCOR, RTCNT, and the RMODE and RFSH bits in MCR, then make the CKS2-CKS0 setting. When the clock is selected by CKS2 to CKS0, RTCNT starts counting up from the value at that time. The RTCNT value is constantly compared with the RTCOR value, and if the two values are the same, a refresh request is generated and the IRQOUT pin goes low. If the SH7708 Series' external bus can be used, CAS-before-RAS refreshing is performed, and if there is no other interrupt request the IRQOUT pin goes high. At the same time, RTCNT is cleared to zero and the count-up is restarted. Figure 10.19 shows the operation of CAS-before-RAS refreshing.
RTCNT cleared to 0 when RTCNT = RTCOR
RTCOR value RTCNT
H'00000000 RTCSR.CKS(2-0) CMF CMF flag cleared by start of refresh cycle External bus CAS-before-RAS refresh cycle = 000 000
Time
Figure 10.19
CAS-Before-RAS Refresh Operation
252
Figure 10.20 shows the timing of the CAS-before-RAS refresh cycle. The number of RAS assert cycles in the refresh cycle is specified by the TRAS bits in MCR and DCR. The specification of the RAS precharge time in the refresh cycle is determined by the setting of the TPC bits in MCR and DCR in the same way as for normal access.
TRc TRr1 TRr2 (Tpc)
CKIO
RAS
CASxx
RD/WR
CS2 or CS3
(High)
Figure 10.20
DRAM CAS-Before-RAS Refresh Cycle Timing
The self-refreshing supported by the SH7708 Series is shown in figure 10.21. After the self-refresh is cleared, the refresh controller immediately generates a refresh request. The RAS precharge time immediately after the end of the self-refreshing can be set by the TPC bits in MCR and DCR. DRAMs include low-power products (L versions) with a long refresh cycle time (for example, the L version of the HM51W4160AL has a refresh cycle of 1024 cycles/128 ms compared with 1024 cycles/16 ms for the normal version). With these DRAMs, however, the same refresh cycle as the normal version is requested only when refreshing immediately after self-refreshing. Therefore, to ensure efficient DRAM refreshing, an overflow interrupt is generated and the refresh cycle is restored to its proper value. This occurs after the necessary CAS-before-RAS refreshing has been performed following self-refreshing of an L-version DRAM, using RFCR and the OVF, OVIE, and LMTS bits in RTCSR. The procedure is as follows.
253
1. Normally, set the refresh counter count value to the optimum value for the L version (e.g. 1024 cycles/128 ms). 2. When a transition is made to self-refreshing: a. Provide an interrupt handler to restore the refresh counter count value to the optimum value for the L version (e.g. 1024 cycles/128 ms) when a refresh counter overflow interrupt is generated. b. Reset the refresh counter count value to the requested short cycle (e.g. 1024 cycles/16 ms), set refresh controller overflow interruption, and clear the refresh count register (RFCR) to 0. c. Set self-refresh mode. This procedure causes refreshing immediately following a self-refresh to occur in a short cycle. When adequate refreshing ends, an interrupt is generated and the setting can be restored to the original refresh cycle. CAS-before-RAS refreshing is performed in normal operation, in sleep mode, and in a manual reset. Self-refreshing is performed in normal operation, in sleep mode, in standby mode, and in a manual reset. When the bus has been released in response to a bus arbitration request, or when a transition is made to standby mode, signals generally become high-impedance. Controlling the RAS and CAS signals to become high-impedance or continue to be output is performed with the HIZCNT bit in BCR1. This enables the DRAM to be kept in the self-refreshing state.
254
TRc
TRr1
TRrw
TSR1
TSR1
TSR2
(Tpc)
(Tpc)
CKIO
RAS
CASxx
RD/WR
CS2 or CS3
(High)
Figure 10.21
DRAM Self-Refresh Cycle Timing
Power-On Sequence: For DRAM after powering on, a minimum wait time of 100 s or 200 s, or more during which no access can be performed, should be provided, followed by the prescribed number (usually 8 or more) of dummy CAS-before-RAS refresh cycles. As the bus state controller does not perform any special operations for a power-on reset, the power-on sequence must be carried out by the initialization program executed after a power-on reset.
255
1 0 . 3 . 5 Synchronous DRAM Interface Synchronous DRAM Direct Connection: Since synchronous DRAM can be selected by the CS signal, physical space areas 2 and 3 can be connected using RAS and other control signals in common. If the memory type bits (DRAMTP2-DRAMTP0) in BCR1 are set to 010, area 2 is normal memory space and area 3 is synchronous DRAM space; if set to 011, areas 2 and 3 are both synchronous DRAM space. With the SH7708 Series, burst length 1 burst read/single write mode is supported as the synchronous DRAM operating mode. The data bus width is fixed at 32 bits, and the size bit (SZ) in MCR must be set to 1. The burst enable bit (BE) in MCR is ignored, a16-bit burst transfer is performed in a cache fill/copy-back cycle, and only one access is performed in a write-through area write or a noncacheable area read/write. The control signals for direct connection of synchronous DRAM are RAS, CAS, RD/WR, CS2 or CS3, DQMUU, DQMUL, DQMLU, DQMLL, and CKE. All the signals other than CS2 and CS3 are common to all areas, and signals other than CKE are valid and fetched to the synchronous DRAM only when CS2 or CS3 is asserted. Synchronous DRAM can therefore be connected in parallel to a number of areas. CKE is negated (low) only when self-refreshing is performed, otherwise it is asserted (high). Commands for synchronous DRAM are specified by RAS, CAS, RD/WR, and special address signals. The commands are NOP, auto-refresh (REF), self-refresh (SELF), precharge all banks (PALL), precharge specified bank (P RE), row address strobe bank active (ACTV), read (READ), read with precharge (READA), write (WRIT), write with precharge (WRITA), and mode register write (MRS). Byte specification is performed by DQMUU, DQMUL, DQMLU, and DQMLL. A read/write is performed for the byte for which the corresponding DQM is low. In big-endian mode, DQMUU specifies an access to address 4n, and DQMLL specifies an access to address 4n + 3. In little-endian mode, DQMUU specifies an access to address 4n + 3, and DQMLL specifies an access to address 4n. Figure 10.22 shows an example of the connection of 256k x 16-bit synchronous DRAMs.
256
SH7708 Series A11
**** **** ****
256k x 16-bit synchronous DRAM A9 A0 CLK CKE CS RAS CAS WE I/O15
**** **** ****
A2 CKI0 CKE CSn RAS CAS RD/WR D31 D16 DQMUU DQMUL D15
**** **** ****
I/O0 DQMU DQML A9
****
D0 DQMLU DQMLL
A0 CLK CKE CS RAS CAS WE I/O15
****
I/O0 DQMU DQML
Figure 10.22
Example of Synchronous DRAM Connection
****
****
****
257
Address Multiplexing: Synchronous DRAM can be connected without external multiplexing circuitry in accordance with the address multiplex specification bits AMX1 and AMX0 in MCR. Table 10.13 shows the relationship between the address multiplex specification bits and the bits output at the address pins. A25-A16 and A0 are not multiplexed; the original values are always output at these pins. When A0, the LSB of the synchronous DRAM address, is connected to the SH7708 Series, it performs longword address specification. Connection should therefore be made in this order: connect pin A0 of the synchronous DRAM to pin A2 of the SH7708 Series, then connect pin A1 to pin A3. Table 10.14 shows the example of correspondence between SH7708 Series and synchronous DRAM address pins. Table 10.13
Setting A M X 1 A M X 0 Output Timing A1 to A8 0 0 Column address Row address 0 1 Column address Row address 1 0 Column address Row address 1 1 Column address Row address A1 to A8 A9 to A16 A1 to A8 A10 to A17 A1 to A8 A11 to A18 A1 to A8 A9 to A16 A9 A9 A17 A9 A18 A9 A19 A9 A17
Relationship between SZ, AMX, and Address Multiplex Output
External Address Pins A10 A10 A18 A10 A19 A10 A20 L/H*1 A18 A11 A11 A19 A11 A20 A11 A21 A19*2 A19*2 A12 L/H*1 A20 L/H*1 A21 L/H*1 A22 A12 A20 A13 A21*2 A21*2 A22*2 A22*2 A23*2 A23*2 A13 A21 A14 A14 A22 A14 A23 A14 A24 A14 A22 A15 A15 A23 A15 A24 A15 A25 A15 A23
Notes: 1. L/H is a bit used in the command specification; it is fixed at L or H according to the access mode. 2. Bank address specification.
258
Table 10.14 Example of Correspondence between SH7708 Series and Synchronous DRAM Address Pins (AMX (1-0) = 11)
SH7708 Series Address Pin RAS Cycle CAS Cycle A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A0 A19 L/H A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Synchronous DRAM Address Pin A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Not used Not used --
Function BANK select bank address Address precharge setting Address
Burst Read: The timing chart for a burst read is shown in figure 10.23. In the following example it is assumed that four 2M x 8-bit synchronous DRAMs are connected and a 32-bit data width is used, and the burst length is 1. Following the Tr cycle in which ACTV command output is performed, a READ command is issued in the Tc1, Tc2, and Tc3 cycles, and a READA command in the Tc4 cycle. The read data is then accepted on the rising edge of the external command clock (CKIO) from cycle Td1 to cycle Td4. The Tpc cycle is used to wait for completion of auto-precharge based on the READA command inside the synchronous DRAM; no new access command can be issued to the same bank during this cycle, but access to synchronous DRAM for another area is possible. In the SH7708 Series, the number of Tpc cycles is determined by the TPC bit specification in MCR, and commands cannot be issued for the same synchronous DRAM during this interval. The example in figure 10.23 shows the basic timing. To connect slower synchronous DRAM, the cycle can be extended by setting the WCR2 and MCR bits. The number of cycles from the ACTV command output cycle, Tr, to the READ command output cycle, Tc1, can be specified by the RCD bit in MCR, with a value of 0 to 3 specifying 1 to 4 cycles, respectively. For 2 or more cycles, a Trw cycle, in which an NOP command is issued for the synchronous DRAM, is inserted between the Tr cycle and the Tc cycle. The number of cycles from READ and READA command output cycles Tc1-Tc4 to the first read data latch cycle, Td1, can be specified as 1 to 3 cycles independently for areas 2 and 3 by means of A1-2W1 and A1-2W0 or A3W1 and A3W0 in WCR2. This number of cycles corresponds to the number of synchronous DRAM CAS latency cycles.
259
Tr CKIO A25 to A16, A13 A12 A15, A14, A11 to A0 CS2 or CS3 RAS CAS RD/WR DQMxx D31 to D0 BS
Tc1
Tc2/Td1
Tc3/Td2
Tc4/Td3
Td4
Tpc
Figure 10.23
Basic Timing for Synchronous DRAM Burst Read
260
Figure 10.24 shows the burst read timing when RCD is set to 1, A3W1 and A3W0 are set to 10, and TPC is set to 1. The BS cycle, which is asserted for one cycle at the start of a bus cycle for normal access space, is asserted in each of cycles Td1-Td4 in a synchronous DRAM cycle. When a burst read is performed, the address is updated each time CAS is asserted. As the unit of burst transfer is 16 bytes, address updating is performed for A3 and A2 only. In a fill operation in the event of a cache miss, the order of access is: the missed data is read first, then 16-byte boundary data including the missed data is read in wraparound mode.
Tr CKIO A25 to A16, A13 A12 A15, A14, A11 to A0 CS2 or CS3 RAS CAS RD/WR DQMxx Trw Tc1 Tc2 Tc3/Td1 Tc4/Td2 Td3 Td4 Tpc
D31 to D0 BS
Figure 10.24
Synchronous DRAM Burst Read Wait Specification Timing
261
Single Read: Figure 10.25 shows the timing when a single address read is performed. As the burst length is set to 1 in synchronous DRAM burst read/single write mode, only the required data is output. Consequently, no unnecessary bus cycles are generated even when a cache-through area is accessed.
Tr CKIO A25 to A16, A13 A12 A15, A14, A11 to A0 CS2 or CS3 Tc1 Td1 Tpc
RAS
CAS RD/WR DQMxx
D31 to D0 BS
Figure 10.25
Basic Timing for Synchronous DRAM Single Read
262
Burst Write: The timing chart for a burst write is shown in figure 10.26. In the SH7708 Series, a burst write occurs only in the event of cache copy-back. In a burst write operation, following the Tr cycle in which ACTV command output is performed, a WRIT command is issued in the Tc1, Tc2, and Tc3 cycles, and a WRITA command that performs auto-precharge is issued in the Tc4 cycle. In the write cycle, the write data is output at the same time as the write command. For the write with auto-precharge command, precharging of the relevant bank is performed in the synchronous DRAM after completion of the write command, and therefore no command can be issued for the same bank until precharging is completed. Consequently, in addition to the precharge wait cycle, Tpc, used in a read access, cycle Trwl is added as a wait interval until precharging is started, following the write command. Issuance of a new command for the same bank is postponed during this interval. The number of Trwl cycles can be specified by the TRWL bit in MCR.
263
Tr CKIO
Tc1
Tc2
Tc3
Tc4
(Trwl)
(Tpc)
Address upper bits
A12, A11, A10 or A9
Address lower bits
CSn
RD/WR
RAS
CASxx
DQMxx
D31 to D0 (read)
BS
Figure 10.26
Basic Timing for Synchronous DRAM Burst Write
264
Single Write: The basic timing chart for write access is shown in figure 10.27. In a single write operation, following the Tr cycle in which ACTV command output is performed, a WRITA command that performs auto-precharge is issued in the Tc1 cycle. In the write cycle, the write data is output at the same time as the write command. For the write with auto-precharge command, precharging of the relevant bank is performed in synchronous DRAM after completion of the write command, and therefore no command can be issued for the same bank until precharging is completed. Consequently, in addition to the precharge wait cycle, Tpc, used in a read access, cycle Trwl is also added as a wait interval until precharging is started following the write command. Issuance of a new command for the same bank is postponed during this interval. The number of Trwl cycles can be specified by the TRWL bit in MCR.
265
Tr CKIO
Tc1
(Trwl)
(Tpc)
Address upper bits
A12 or A10
Address lower bits
CSn
RD/WR
RAS
CAS
DQMxx
D31 to D0
BS
CKE
Figure 10.27
Basic Timing for Synchronous DRAM Single Write
266
Refreshing: The bus state controller is provided with a function for controlling synchronous DRAM refreshing. Auto-refreshing can be performed by clearing the RMODE bit to 0 and setting the RFSH bit to 1 in MCR. If synchronous DRAM is not accessed for a long period, self-refresh mode, in which the power consumption for data retention is low, can be activated by setting both the RMODE bit and the RFSH bit to 1. 1. Auto-Refreshing Refreshing is performed at intervals determined by the input clock selected by bits CKS2-CKS0 in RTCSR, and the value set in RTCOR. The value of bits CKS2-CKS0 in RTCOR should be set so as to satisfy the refresh interval stipulation for the synchronous DRAM used. First make the settings for RTCOR, RTCNT, and the RMODE and RFSH bits in MCR, then make the CKS2 to CKS0 setting. When the clock is selected by CKS2-CKS0, RTCNT starts counting up from the value at that time. The RTCNT value is constantly compared with the RTCOR value, and if the two values are the same, a refresh request is generated and an auto-refresh is performed. At the same time, RTCNT is cleared to zero and the count-up is restarted. Figure 10.28 shows the auto refresh operation. Figure 10.29 shows the auto-refresh cycle timing. First, an REF command is issued in the TRr cycle. After the TRr cycle, new command output cannot be performed for the duration of the number of cycles specified by the TRAS bits in MCR plus the number of cycles specified by the TPC bits in MCR. The TRAS and TPC bits must be set to satisfy the synchronous DRAM refresh cycle time stipulation (active/active command delay time). Auto-refreshing is performed in normal operation, in sleep mode, and in a manual reset.
RTCNT cleared to 0 when RTCNT = RTCOR
RTCOR value RTCNT
H'00000000 RTCSR.CKS(2-0) CMF CMF flag cleared by start of refresh cycle External bus Auto-refresh cycle = 000 000
Time
Figure 10.28
Auto-Refresh Operation
267
TRr CKIO
TRrw
TRrw
(Tpc)
(Tpc)
CKE
CSn
RAS
CASxx
RD/WR
Figure 10.29
Synchronous DRAM Auto-Refresh Timing
2. Self-Refreshing Self-refresh mode is a kind of standby mode in which the refresh timing and refresh addresses are generated within the synchronous DRAM. Self-refreshing is activated by setting both the RMODE bit and the RFSH bit to 1. The self-refresh state is maintained while the CKE signal is low. Synchronous DRAM cannot be accessed while in the self-refresh state. Self-refresh mode is cleared by clearing the RMODE bit to 0. After self-refresh mode has been cleared, command issuance is disabled for the number of cycles specified by the TPC bits in MCR. Self-refresh timing is shown in figure 10.30. Settings must be made so that self-refresh clearing and data retention are performed correctly, and auto-refreshing is performed at the correct intervals. When self-refreshing is activated from the state in which auto-refreshing is set, or when exiting standby mode other than through a power-on reset, auto-refreshing is restarted if RFSH is set to 1 and RMODE is cleared to 0 when self-refresh mode is cleared. If the transition from clearing of self-refresh mode to the start of autorefreshing takes time, this time should be taken into consideration when setting the initial value of RTCNT. Making the RTCNT value 1 less than the RTCOR value will enable refreshing to be started immediately. After self-refreshing has been set, the self-refresh state continues even if the chip standby state is entered using the SH7708 Series's standby function, and is maintained even after recovery from standby mode other than through a power-on reset. For a power-on reset, the bus state controller's registers are initialized, thereby clearing the self-refresh state.
268
Self-refreshing is performed in normal operation, in sleep mode, in standby mode, and in a manual reset.
TRs1 CKIO (TRs2) (TRs2) TRs3 (Tpc) (Tpc)
CKE
CSn
RAS
CASxx
RD/WR
Figure 10.30
Synchronous DRAM Self-Refresh Timing
3. Relationship between refresh requests and bus cycle requests If a refresh request is generated during execution of a bus cycle, execution of the refresh is deferred until the bus cycle is completed. If a refresh request occurs when the bus has been released by the bus arbiter, refresh execution is deferred until the bus is acquired. If a match between RTCNT and RTCOR occurs while a refresh is waiting to be executed, thereby generating a new refresh request, the previous refresh request is eliminated. To perform normal refreshing, ensure that no bus cycle or bus mastership occurs that is longer than the refresh interval. When a refresh request is generated, the IRQOUT pin is asserted (driven low). Therefore, normal refreshing can be performed by having the IRQOUT pin monitored by a bus master other than the SH7708 Series requesting the bus, or the bus arbiter, and returning the bus to the SH7708 Series. When refreshing is started, and if no other interrupt request has been generated, the IRQOUT pin is negated (driven high).
269
Power-On Sequence: In order to use synchronous DRAM, mode setting must first be performed after powering on. To perform synchronous DRAM initialization correctly, the bus state controller registers must first be set, followed by a write to the synchronous DRAM mode register. In synchronous DRAM mode register setting, the address signal value at that time is latched by a combination of the RAS, CAS, and RD/WR signals. If the value to be set is X, the bus state controller provides for value X to be written to the synchronous DRAM mode register by performing a write to address H'FFFFD000 + X for area 2 synchronous DRAM, and to address H'FFFFE000 + X for area 3 synchronous DRAM. In this operation the data is ignored, but the mode write is performed as a byte-size access. To set burst read/write, CAS latency 1 to 3, wrap type = sequential, and burst length 1 supported by the SH7708 Series, arbitrary data is written in a byte-size access to the following addresses: Area 2 FFFFD840 FFFFD880 FFFFD8C0 Area 3 FFFFE840 FFFFE880 FFFFE8C0
CAS latency 1 CAS latency 2 CAS latency 3
Mode register setting timing is shown in figure 10.31. As a result of the write to address H'FFFFD000 + X or H'FFFFE000 + X, a precharge all banks (PALL) command is first issued in the TRp1 cycle, then a mode register write command is issued in the TMw1 cycle. Before mode register setting, a 100 s idle time (depending on the memory manufacturer) must be guaranteed after powering on requested by the synchronous DRAM. If the reset signal pulse width is greater than this idle time, there is no problem in performing mode register setting immediately. The number of dummy auto-refresh cycles specified by the manufacturer (usually 8) or more must be executed. This is usually achieved automatically through various initialization methods after auto-refresh setting. However, a more dependable method is to set a short refresh request generation interval just as these dummy cycles are being executed. With simple read or write access, the address counter in the synchronous DRAM used for auto-refreshing is not initialized, and so the cycle must always be an auto-refresh cycle.
270
TRp1 CKIO
TRp2
TRp3
TRp4
TMw1
TMw2
TMw3
TMw4
A13 or A11
A12 or A10
A11 to A2, or A9 to A2
CSn
RD/WR
RAS
CASxx
D31 to D0 CKE
(High)
Figure 10.31
Synchronous DRAM Mode Write Timing
271
1 0 . 3 . 6 Pseudo-SRAM Direct Connection When the memory type bits (DRAMTP2-0) in BCR1 are set to 001, physical space area 3 becomes pseudo-SRAM and the pseudo-SRAM interface function that allows pseudo-SRAM to be connected directly to the SH7708 Series can be used. An interface data width of 16 or 32 bits can be selected. With directly connected pseudo-SRAM, the refresh signal and output enable signal are multiplexed. The signals used for connection are CE, OE/RFSH, WE3, WE2, WE1, and WE0. WE3 and WE2 are not used with a 16-bit data width. As access modes, burst access using the static column access function is supported in addition to ordinary read/write access. Figure 10.32 shows an example of connection of 4M pseudo-SRAMs with multiplexed OE and RFSH signals, using a 32-bit data width.
272
SH7708 Series
**** **** ****
512k x 8-bit pseudo-SRAM
**** **** **** **** **** **** **** ****
A20 A2 CE OE D31
****
A18 A0 CE OE/RFSH I/O7
D24 WE3 D23
****
****
I/O0 WE
****
D16 WE2 D15
****
****
A18 A0 CE OE/RFSH I/O7 I/O0 WE
****
D0 WE0
****
****
D8 WE1 D7
****
****
A18 A0 CE OE/RFSH I/O7 I/O0 WE
****
A18 A0 CE OE/RFSH I/O7 I/O0 WE
Figure 10.32
Example of Pseudo-SRAM Connection (4M-Bit Devices)
****
273
Basic Timing: Figure 10.33 shows the basic timing for pseudo-SRAM. Tpc is the precharge cycle, and Tr is the CE assert cycle. Tc1 is the write data cycle, BS the assert cycle, and Tc2 the read data latch cycle.
Tr
Tc1
Tc2
(Tpc)
CKIO
A25 to A0
RD/WR
CE
OE/RFSH (read)
D31 to D0 (read)
WEn (write)
D31 to D0 (write)
BS
Figure 10.33
274
Basic Access Timing for Pseudo-SRAM
Wait State Control: As the clock frequency increases, it becomes impossible to complete all states in one cycle as in basic access. Therefore, provision is made for state extension by using the setting bits in WCR2 and MCR. The timing with state extension using these settings is shown in figure 10.34. Additional Tpc cycles (cycles used to secure the CE precharge time) can be inserted by means of the TPC bits in MCR. The number of OE and WEn assert cycles from RAS assertion to CAS assertion can be varied between 1 and 3 according to the setting of A3W1 and A3W0 in WCR2. Trw cycles can be inserted by means of the RCD bits in MCR, and the number of cycles from CE assertion to BS assertion and write data output can be varied between 1 and 4.
275
Tr CKIO
Trw
Tc1
Tc1w
Tc1w
Tc2
(Tpc)
A25 to A0
RD/WR
CE
OE/RFSH (read)
D31 to D0 (read)
WEn (write)
D31 to D0 (write)
BS
Figure 10.34
Pseudo-SRAM Wait State Timing
Burst Access: In addition to the normal access mode in which CE is asserted and negated in each access, some pseudo-SRAMs are provided with a static column mode for the case where consecutive accesses are made to the same row address. This mode allows fast access to data by keeping CE asserted and changing only the column address. Normal access or burst access using static column mode can be selected by means of the burst enable (BE) bit in MCR. The timing for burst access in static column mode is shown in figure 10.35. Cycles can also be inserted by the wait state control function when burst access is performed.
276
Tr CKIO
Tc1
Tc2
Tc1
Tc2
Tc1
Tc2
Tc1
Tc2
(Tpc)
A25 to A4
A3 to A0
RD/WR
CE
OE/RFSH (read)
D31 to D0 (read) WEn (write)
D31 to D0 (write)
BS
Figure 10.35
Pseudo-SRAM Static Column Mode
277
Refreshing: The bus state controller includes a function for controlling pseudo-SRAM refreshing. Distributed refreshing by means of auto-refresh cycles can be performed by clearing the RMODE bit to 0 and setting the RFSH bit to 1 in MCR. Refreshing is performed at intervals determined by the input clock selected by bits CKS2-CKS0 in RTCSR, and the value set in RTCOR. The value of bits CKS2-CKS0 in RTCOR should be set so as to satisfy the refresh interval stipulation for the pseudo-SRAM used. First set the RTCOR, RTCNT, and the RMODE and RFSH bits in MCR, then set the CKS2-CKS0. When the clock is selected by CKS2-CKS0, RTCNT starts counting up from the value at that time. The RTCNT value is constantly compared with the RTCOR value, and if the two values are the same, a refresh request is generated and an auto-refresh is performed. At the same time, RTCNT is cleared to zero and the count-up is restarted. Figure 10.36 shows the auto-refresh cycle timing. The number of OE assert cycles for auto-refreshing is specified by the TRAS bits in MCR. The precharge time from OE negation until the next assertion of CE is determined by the setting of the TPC bits in MCR. Auto-refreshing is performed in normal operation, in sleep mode, and in a manual reset.
TRc TRr1 TRr2 (Tpc)
CKIO
CE
OE/RFSH
Figure 10.36
Pseudo-SRAM Auto-Refreshing
278
With pseudo-SRAM, self-refresh mode is entered by holding the RFSH signal low for at least the prescribed time. Self-refreshing is activated by setting both the RMODE bit and the RFSH bit to 1. The self-refresh state is maintained while the CKE signal is low. Pseudo-SRAM cannot be accessed while in self-refresh state. Self-refresh mode is cleared by clearing the RMODE bit to 0. After self-refresh mode has been cleared, access to pseudo-SRAM is disabled for the number of cycles specified by the TPC bits in MCR, but if the refresh reset time needed to return from selfrefreshing is longer than this interval, coding must be provided to ensure that no access--including auto-refresh--is made to pseudo-SRAM. Self-refresh timing is shown in figure 10.37. Settings must be made so that self-refresh clearing and data retention is performed correctly after self-refresh mode is cleared, and auto-refreshing is performed at the correct intervals. If the transition from clearing of self-refresh mode to the start of auto-refreshing takes time, this time should be taken into consideration when setting the initial value of RTCNT. Self-refreshing is performed in normal operation, in sleep mode, in standby mode, and in a manual reset.
TRc CKIO TRr1 TSR TSR2 (Tpc) (Tpc)
CE
(High)
OE/RFSH
Figure 10.37
Pseudo-SRAM Self-Refreshing
Power-On Sequence: After powering pseudo-SRAM on, a minimum wait time of 100 s is requested during which no access can be performed, followed by the prescribed number (usually 8 or more) of dummy auto-refresh cycles. As the bus state controller does not perform any special operations for a power-on reset, the power-on sequence must be carried out by the initialization program executed after a power-on reset.
279
1 0 . 3 . 7 Burst ROM Interface Setting bits A0BST (1,0), A5BST (1,0), and A6BST (1,0) in BCR1 to a non-zero value allows burst ROM to be connected to areas 0, 5, and 6. The burst ROM interface provides high-speed access to ROM that has a nibble access function. The timing for nibble access to burst ROM is shown in figure 10.38. Two wait cycles are set. Basically, access is performed in the same way as for normal space, but when the first cycle ends, the CS0 signal is not negated, and only the address is changed before the next access is executed. When 8-bit ROM is connected, the number of consecutive accesses can be set as 4, 8, or 16 by bits A0BST (1,0), A5BST (1,0), or A6BST (1,0). When 16-bit ROM is connected, 4 or 8 can be set in the same way. When 32-bit ROM is connected, only 4 can be set. WAIT pin sampling is performed in the first access if one or more wait states are set, and is always performed in the second and subsequent accesses. WAIT is a synchronous signal. The second and subsequent access cycles also comprise two cycles when a burst ROM setting is made and the wait specification is 0. The timing in this case is shown in figure 10.39.
280
T1 CKIO
TW
TW
TB2
TB1
TW
TB2
T2
T2
A25 to A4
A3 to A0
CSn
RD/WE
RD
D31 to D0
BS
WAIT
Note: For a write cycle, a basic bus cycle (write cycle) is performed.
Figure 10.38
Burst ROM Wait Access Timing
281
T1 CKIO
TB2
TB1
TB2
TB1
TB2
TB1
T2
A25 to A4
A3 to A0
CSn
RD/WE
RD
D31 to D0
BS
WAIT Note: For a write cycle, a basic bus cycle (write cycle) is performed.
Figure 10.39
Burst ROM Basic Access Timing
282
1 0 . 3 . 8 PCMCIA Interface In the SH7708 Series, setting the A5PCM bit in BCR1 to 1 makes the bus interface for physical space area 5 an IC memory card interface as stipulated in JEIDA version 4.2 (PCMCIA2.1). Setting the A6PCM bit to 1 makes the bus interface for physical space area 6 an IC memory card and I/O card interface as stipulated in JEIDA version 4.2. When the IC memory card interface is selected, a BCR1 register setting enables page mode burst access mode to be used. This burst access mode is not stipulated in JEIDA version 4.2, but allows high-speed data access using ROM provided with a burst mode, etc. When the PCMCIA interface is used, a bus size of 8 or 16 bits can be set by bits A5SZ1 and A5SZ0, or A6SZ1 and A6SZ0, in BCR2. Figure 10.40 shows an example of PCMCIA card connection to the SH7708 Series. To enable active insertion of the PCMCIA cards (i.e. insertion or removal while system power is being supplied), a 3-state buffer must be connected between the SH7708 Series's bus interface and the PCMCIA cards. As operation in big-endian mode is not explicitly stipulated in the JEIDA/PCMCIA specifications, the PCMCIA interface for the SH7708 Series in big-endian mode is stipulated independently. If PCMCIA is used in area 6, synchronous DRAM is used at the same time, and a synchronous DRAM auto-refresh (CAS-before-RAS refresh) request is issued simultaneously, area 6 card enable signals CS6 and CE2B may be asserted earlier than usual, at the same time as the immediately preceding auto-refresh cycle. When both PCMCIA and synchronous DRAM are used, they should be used in area 5. When area 5 is used, the system design should provide for CS to be asserted early without causing any problems.
283
A24 to A0 D15 to D0 RD/WR CE1B/(CS6) CE1A/(CS5) CE2B CE2A SH7708 Series RD WE1 ICIORD ICIOWR WAIT IOIS16 Card detection circuit Output port D7 to D0 G DIR D15 to D8 G DIR D7 to D0 G DIR D15 to D8 G DIR G
A25 to A0
D15 to D0
PC card (memory/IO)
G
CE1 CE2 OE WE/PGM (IORD) (IOWR) WAIT (IOIS16) CD1, CD2
A25 to A0 G D15 to D0
PC card (memory/IO)
G
CE1 CE2 OE WE/PGM WAIT Card detection circuit CD1, CD2
Figure 10.40
284
Example of PCMCIA Interface
Memory Card Interface Basic Timing: Figure 10.41 shows the basic timing for the PCMCIA IC memory card interface. When physical space areas 5 and 6 are designated as PCMCIA interface areas, bus accesses are automatically performed as IC memory card interface accesses when the lower address 32 Mbyte space of each area is accessed. With a high external bus frequency (CKIO), the setup and hold times for the address (A24-A0), card enable (CS5, CE2A, CS6, CE2B), and write data (D15-D0) in a write cycle, become insufficient with respect to RD and WR (the WE1 pin in the SH7708 Series). The SH7708 Series provides for this by enabling setup and hold times to be set for physical space areas 5 and 6 in the PCR register. Also, software waits by means of a WCR2 register setting and hardware waits by means of the WAIT pin can be inserted in the same way as for the basic interface. WAIT is a synchronous signal. Figure 10.42 shows the PCMCIA memory bus wait timing.
285
Tpcm1
Tpcm2
CKIO
A25 to A0
CExx
RD/WR
RD (read)
D15 to D0 (read)
WE1 (write)
D15 to D0 (read)
BS
Figure 10.41
Basic Timing for PCMCIA Memory Card Interface
286
Tpcm0 CKIO
Tpcm0w
Tpcm1
Tpcm1w Tpcm1w
Tpcm2
Tpcm2w
A25 to A0
CExx
RD/WR
RD (read)
D15 to D0 (read)
WE1 (write)
D15 to D0 (write)
BS
WAIT
Figure 10.42
Wait Timing for PCMCIA Memory Card Interface
287
Memory Card Interface Burst Timing: In the SH7708 Series, when the IC memory card interface is selected, page mode burst access mode can be used, for read access only, by setting bits A5BST1 and A5BST0 in BCR for physical space area 5, or bits A6BST1 and A6BST0 for area 6. This burst access mode is not stipulated in JEIDA version 4.2 (PCMCIA2.1), but allows highspeed data access using ROM provided with a burst mode, etc. Burst access mode timing is shown in figures 10.43 and 10.44.
Tpcm1 CKIO
Tpcm2
Tpcm1
Tpcm2
Tpcm1
Tpcm2
Tpcm1
Tpcm2
A25 to A4
A3 to A0
CExx
RD/WR
RD (read)
D15 to D0 (read)
BS
Figure 10.43
Basic Timing for PCMCIA Memory Card Interface Burst Access
288
Tpcm0
Tpcm1 Tpcm1w Tpcm1w Tpcm1w Tpcm2
Tpcm1 Tpcm1w
Tpcm2 Tpcm2w
CKIO
A25 to A4
A3 to A0
CExx
RD/WR RD (read)
D15 to D0 (read) BS
WAIT
Figure 10.44
Wait Timing for PCMCIA Memory Card Interface Burst Access
When the entire 32-Mbyte memory space is used as IC memory card interface space, the common memory/attribute memory switching signal REG is generated using a port, etc. If 16-Mbytes or less of memory space is sufficient, using 16M bytes of memory space as common memory space and 16 Mbytes as attribute memory space enables the A24 pin to be used for the REG signal.
289
32-Mbyte capacity (REG = I/O port) Area 5: H'14000000 Area 5: H'16000000 Area 6: H'18000000 Area 6: H'1A000000 Common memory/ attribute memory I/O space Common memory/ attribute memory
Up to 16-Mbyte capacity (REG = A24) Area 5: H'14000000 Area 5: H'15000000 H'16000000 Area 6: H'18000000 Area 6: H'19000000 Area 6: H'1A000000 H'1B000000 Attribute memory Common memory I/O space Attribute memory Common memory
Figure 10.45
PCMCIA Space Allocation
I/O Card Interface Timing: Figures 10.46 and 10.47 show the timing for the PCMCIA I/O card interface. The I/O card interface is supported only for physical space area 6. Switching between the I/O card interface and the IC memory card interface is performed according to the accessed address. When PCMCIA is designated for physical space area 6, the bus access is automatically performed as an I/O card interface access when a physical address from H'1A000000 to H'1BFFFFFF is accessed. When accessing a PCMCIA I/O card, the access should be performed using a noncacheable area in virtual space (P2 or P3 space) or an area specified as noncacheable by the MMU. When an I/O card interface access is made to a PCMCIA card in little-endian mode, dynamic sizing of the I/O bus width is possible using the IOIS16 pin. When a 16-bit bus width is set for area 6, if the IOIS16 signal is high during a word-size I/O bus cycle, the I/O port is recognized as being 8 bits in width. In this case, a data access for only 8 bits is performed in the I/O bus cycle being executed, followed automatically by a data access for the remaining 8 bits.
290
Figure 10.48 shows the basic timing for dynamic bus sizing. In big-endian mode, the IOIS16 signal is not supported. In big-endian mode, the IOIS16 signal should be fixed low.
291
Tpci1
Tpci2
CKIO
A25 to A0
CExx
RD/WR
ICIORD (read)
D15 to D0 (read)
ICIOWR (write)
D15 to D0 (write)
BS
Figure 10.46
Basic Timing for PCMCIA I/O Card Interface
292
Tpci0 CKIO
Tpci0w
Tpci1
Tpci1w
Tpci1w
Tpci2
Tpci2w
A25 to A0
CExx
RD/WR
ICIORD (read)
D15 to D0 (read) ICIOWR (write)
D15 to D0 (write)
BS
WAIT
IOIS16
Figure 10.47
Wait Timing for PCMCIA I/O Card Interface
293
Tpci0 CKIO
Tpci1 Tpci1w Tpci2
Tpci1
Tpci1w Tpci2 Tpci2w
A25 to A1
A0
CExx
RD/WR
ICIORD (read)
D15 to D0 (read) ICIOWR (write)
D15 to D0 (write) BS
WAIT
IOIS16
Figure 10.48
Dynamic Bus Sizing Timing for PCMCIA I/O Card Interface
294
1 0 . 3 . 9 Waits between Access Cycles A problem associated with higher external memory bus operating frequencies is that data buffer turn-off on completion of a read from a low-speed device may be too slow, causing a collision with data in the next access. This results in lower reliability or incorrect operation. To avoid this problem, a data collision prevention feature has been provided. This memorizes the preceding access area and the kind of read/write. If there is a possibility of a bus collision when the next access is started, a wait cycle is inserted before the access cycle thus preventing a data collision. There are two cases in which a wait cycle is inserted: when an access is followed by an access to a different area, and when a read access is followed by a write access from the SH7708 Series. When the SH7708 Series performs consecutive write cycles, the data transfer direction is fixed (from the SH7708 Series to other memory) and there is no problem. With read accesses to the same area, in principle, data is output from the same data buffer, and wait cycle insertion is not performed. Bits AnIW1 and AnIW0 (n = 0-6) in WCR1 specify the number of idle cycles to be inserted between access cycles when a physical space area access is followed by an access to another area, or when the SH7708 Series performs a write access after a read access to physical space area n. If there is originally space between accesses, the number of idle cycles inserted is the specified number of idle cycles minus the number of empty cycles. Waits are not inserted between accesses when bus arbitration is performed, since empty cycles are inserted for arbitration purposes.
T1 CKIO A25 to A0 CSm CSn BS RD/WR RD D31 to D0 Area m read Area n space read Area n space write Area m inter-access wait specification Area n inter-access wait specification T2 Twait T1 T2 Twait T1 T2
Figure 10.49
Waits between Access Cycles
295
1 0 . 3 . 1 0 Bus Arbitration When a bus release request (BREQ) is received from an external device, buses are released after the bus cycle being executed is completed and a bus grant signal (BACK) is output. The bus is not released during burst transfers for cache fills. In the case of multiple bus cycles generated because the data bus width is smaller than the access size--for example, in longword access to 8-bit-wide memory--bus arbitration is not performed between bus cycles. At the negation of BREQ, BACK is negated and bus use is restarted. See Appendix B, Pin States, for the pin status when the bus is released. The SH7708 Series sometimes needs to retrieve a bus it has released. For example, when memory generates a refresh request or an interrupt request internally, the SH7708 Series must perform the appropriate processing. The SH7708 Series has a bus request signal (IRQOUT) for this purpose. When it must retrieve the bus, it asserts the IRQOUT signal. Devices asserting an external bus release request receive the assertion of the IRQOUT signal and negate the BREQ signal to release the bus. The SH7708 Series retrieves the bus and carries out the processing. IRQOUT Pin Assertion Conditions: * When a memory refresh request has been generated but the refresh cycle has not yet begun * When an interrupt is generated with an interrupt request level higher than the setting of the interrupt mask bits (I3-I0) in the status register (SR). (This does not depend on the SR.BL bit.)
296
Section 11 Timer (TMU)
11.1 Overview
The SH7708 Series uses a three-channel 32-bit timer unit (TMU). 1 1 . 1 . 1 Features The TMU has the following features: * Each channel is provided with an auto-reload 32-bit down counter * Channel 2 is provided with an input capture function * All channels are provided with 32-bit constant registers and 32-bit down counters that can be read or written to at any time * All channels generate interrupt requests when the 32-bit down counter underflows (H'00000000 H'FFFFFFFF) * Allows selection between 6 counter input clocks: External clock (TCLK), on-chip RTC output clock (16 kHz), P/4, P/16, P/64, P/256. (P is the internal clock for peripheral modules and can be selected as 1/4, 1/2, or the same frequency as that of the CPU operating clock .) See section 9, On-Chip Oscillation Circuits, for more information on the clock pulse generator. * All channels can operate when the SH7708 Series is in standby mode: When the RTC output clock is being used as the counter input clock, the SH7708 Series is still able to count in standby mode. * Synchronized read: TCNT is a sequentially changing 32-bit register. Since the peripheral module used has an internal bus width of 16 bits, a time lag can occur between the time when the upper 16 bits and lower 16 bits are read. To correct the discrepancy in the counter read value caused by this time lag, a synchronization circuit is built into the TCNT so that the entire 32bit data in the TCNT can be read at once. * The maximum operating frequency of the 32-bit counter is 2 MHz on all channels: Operate the SH7708 Series so that the clock input to the timer counters of each channel (obtained by dividing the external clock and internal clock with the prescaler) does not exceed the maximum operating frequency. 1 1 . 1 . 2 Block Diagram Figure 11.1 shows a block diagram of the TMU.
297
P
Prescaler TOCR
TCLK RTCCLK
Clock controller Ch. 0
TSTR TCR0
Counter controller
TCNT0 TCOR0
TUNI0
Interrupt controller Ch. 1 TCR1 Counter controller TCNT1 TCOR1
TUNI1
Interrupt controller Ch. 2
TCR2 Counter controller TCPR2 TCNT2 TCOR2
TUNI2 TICPI2
Interrupt controller
Module bus
TMU TOCR: Timer output control register TSTR: Timer start register TCR: Timer control register TCNT: 32-bit timer counter TCOR: 32-bit timer constant register TCPR2: 32-bit input capture register
Figure 11.1
TMU Block Diagram
298
Internal bus
Bus interface
1 1 . 1 . 3 Pin Configuration Table 11.1 shows the pin configuration of the TMU. Table 11.1Pin Configuration
Channel Pin I/O I/O Description External clock input pin/input capture control input pin/realtime clock (RTC) output pin
Clock input/clock output TCLK
1 1 . 1 . 4 Register Configuration Table 11.2 shows the TMU register configuration. Table 11.2TMU Register Configuration
Channel Register Common Timer output control register Timer start register 0 Abbreviation R / W I n i t i a l Value* TOCR TSTR R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W H'00 H'00 Address H'FFFFFE90 H'FFFFFE92 Acces s Size 8 8 32 32 16 32 32 16 32 32 16 32
Timer constant register 0 TCOR0 Timer counter 0 Timer control register 0 TCNT0 TCR0
H'FFFFFFFF H'FFFFFE94 H'FFFFFFFF H'FFFFFE98 H'0000 H'FFFFFE9C
1
Timer constant register 1 TCOR1 Timer counter 1 Timer control register 1 TCNT1 TCR1
H'FFFFFFFF H'FFFFFEA0 H'FFFFFFFF H'FFFFFEA4 H'0000 H'FFFFFEA8
2
Timer constant register 2 TCOR2 Timer counter 2 Timer control register 2 Input capture register 2 TCNT2 TCR2 TCPR2
H'FFFFFFFF H'FFFFFEAC H'FFFFFFFF H'FFFFFEB0 H'0000 Undefined H'FFFFFEB4 H'FFFFFEB8
Note: Initialized by a power-on reset or manual reset.
299
11.2
TMU Registers
1 1 . 2 . 1 Timer Output Control Register (TOCR) TOCR is an 8-bit read/write register that selects whether to use the external TCLK pin as an external clock or an input capture control usage input pin, or an output pin for the on-chip RTC output clock. TOCR is initialized to H'00 by a power-on reset or manual reset, but is not initialized in standby mode, and its contents are retained.
Bit: Bit name: Initial value: R/W: 7 -- 0 R 6 -- 0 R 5 -- 0 R 4 -- 0 R 3 -- 0 R 2 -- 0 R 1 -- 0 R 0 TCOE 0 R/W
Bits 7 to 1--Reserved: These bits always read 0. The write value should always be 0. Bit 0--Timer Clock Pin Control (TCOE): Selects use of the timer clock pin (TCLK) as an external clock input pin or input pin for input capture control for the on-chip timer, or as an output pin for the on-chip RTC output clock.
Bit 0: TCOE 0 Description Timer clock pin (TCLK) used as external clock input or input capture control input pin for the on-chip timer (Initial value) Timer clock pin (TCLK) used as output pin for on-chip RTC output clock
1
300
1 1 . 2 . 2 Timer Start Register (TSTR) TSTR is an 8-bit read/write register that selects whether to run or halt the timer counters (TCNT) for channels 0-2. TSTR is initialized to H'00 by a power-on reset or manual reset. In standby mode, when the PLL1 multiplication factor is changed in clock mode 0, 1, 2, or 7, or when the MSTP2 bit is set to 1 in STBCR, TSTR is initialized only when the input clock selected for the channel is an external clock (TCLK) or the peripheral clock (Po).
Bit: Bit name: Initial value: R/W: 7 -- 0 R 6 -- 0 R 5 -- 0 R 4 -- 0 R 3 -- 0 R 2 STR2 0 R/W 1 STR1 0 R/W 0 STR0 0 R/W
Bits 7 to 3--Reserved: These bits always read 0. The write value should always be 0. Bit 2--Counter Start 2 (STR2): Selects whether to run or halt timer counter 2 (TCNT2).
Bit 2: STR2 0 1 Description Halt TCNT2 count value) Start TCNT2 counting (Initial
Bit 1--Counter Start 1 (STR1): Selects whether to run or halt timer counter 1 (TCNT1).
Bit 1: STR1 0 1 Description Halt TCNT1 count value) Start TCNT1 counting (Initial
Bit 0--Counter Start 0 (STR0): Selects whether to run or halt timer counter 0 (TCNT0).
Bit 0: STR0 0 1 Description Halt TCNT0 count value) Start TCNT0 counting (Initial
301
1 1 . 2 . 3 Timer Control Register (TCR) The timer control registers (TCR) control the timer counters (TCNT) and interrupts. The TMU has three TCR, registers one for each channel. The TCR registers are 16-bit read/write registers that control the issuance of interrupts when the flag indicating timer counter (TCNT) underflow has been set to 1, and also carry out counter clock selection. When the external clock has been selected, they also select its edge. Additionally, TCR2 controls the channel 2 input capture function and the issuance of interrupts during input capture. The TCRs are initialized to H'0000 by a power-on reset and manual reset. In standby mode, when the PLL1 multiplication factor is changed in clock mode 0, 1, 2, or 7, or when the MSTP2 bit is set to 1 in STBCR, the TCRs retain their contents when the input clock selected for the channel is an external clock (TCLK) or the peripheral clock (Po), and continue operating when the selected clock is the on-chip RTC output clock (RTCCLK). Channel 0 and 1 TCR Bit Configuration:
Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: 15 -- 0 R 7 -- 0 R 14 -- 0 R 6 -- 0 R 13 -- 0 R 5 UNIE 0 R/W 12 -- 0 R 4 CKEG1 0 R/W 11 -- 0 R 3 CKEG0 0 R/W 10 -- 0 R 2 TPSC2 0 R/W 9 -- 0 R 1 TPSC1 0 R/W 8 UNF 0 R/W 0 TPSC0 0 R/W
Channel 2 TCR Bit Configuration:
Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: 15 -- 0 R 7 ICPE1 0 R/W 14 -- 0 R 6 ICPE0 0 R/W 13 -- 0 R 5 UNIE 0 R/W 12 -- 0 R 4 CKEG1 0 R/W 11 -- 0 R 3 CKEG0 0 R/W 10 -- 0 R 2 TPSC2 0 R/W 9 ICPF 0 R/W 1 TPSC1 0 R/W 8 UNF 0 R/W 0 TPSC0 0 R/W
302
Bits 15 to 10, 9 (except TCR2), 7, and 6 (except TCR2)--Reserved: These bits always read 0. The write value should always be 0. Bit 9--Input Capture Interrupt Flag (ICPF): A function of channel 2 only: the flag is set when input capture is requested via the TCLK pin.
Bit 9: ICPF 0 Description No input capture request has been issued. Clearing condition: When 0 is written to ICPF value) (Initial
1
Input capture has been requested via the TCLK pin. Setting condition: When an input capture is requested via the TCLK pin*
Note: Contents do not change when 1 is written to ICPF.
Bit 8--Underflow Flag (UNF): Status flag that indicates occurrence of a TCNT underflow.
Bit 8: UNF 0 Description TCNT has not underflowed. Clearing condition: When 0 is written to UNF value) TCNT has underflowed (H'00000000 H'FFFFFFFF). Setting condition: When TCNT underflows* (Initial
1
Note: Contents do not change when 1 is written to UNF.
Bits 7 and 6--Input Capture Control (ICPE1, ICPE0): A function of channel 2 only: determines whether the input capture function can be used, and when used, whether or not to enable interrupts. When using this input capture function it is necessary to set the TCLK pin to input mode with the TCOE bit in the TOCR register. Additionally, use the CKEG bit to designate use of either the rising or falling edge of the TCLK pin to set the value in TNCT2 in the input capture register (TCPR2).
Bit 7: ICPE1 0 Bit 6: ICPE0 0 1 1 0 1 Description Input capture function is not used. value) Reserved (cannot be set) Input capture function is used. Interrupts due to ICPF (TICPI2) are not enabled. Input capture function is used. Interrupts due to ICPF (TICPI2) are enabled. (Initial
303
Bit 5--Underflow Interrupt Control (UNIE): Controls enabling of interrupt generation when the status flag (UNF) indicating TCNT underflow has been set to 1.
Bit 5: UNIE 0 1 Description Interrupts due to UNF (TUNI) are not enabled. value) Interrupts due to UNF (TUNI) are enabled. (Initial
Bits 4 and 3--Clock Edge 1, 0 (CKEG1, CKEG0): These bits select the external clock edge when the external clock is selected, or when the input capture function is used.
Bit 4: CKEG1 Bit 3: CKEG0 Description 0 0 1 1 -- Count/capture register set on rising edge value) Count/capture register set on falling edge Count/capture register set on both rising and falling edge (Initial
Bits 2 to 0--Timer Prescalers 2-0 (TPSC2-TPSC0): These bits select the TCNT count clock.
Bit 2: TPSC2 Bit 1: TPSC1 Bit 0: TPSC0 Description 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Internal clock: count on P/4 value) Internal clock: count on P/16 Internal clock: count on P/64 Internal clock: count on P/256 Internal clock: count on clock output of on-chip RTC (RTCCLK) External clock: count on TCLK pin input Reserved ( Do not set) Reserved (Do not set) (Initial
304
1 1 . 2 . 4 Timer Constant Register (TCOR) The timer constant registers are 32-bit registers. The TMU has three TCOR registers, one for each of the three channels. TCOR is a 32-bit read/write register. When a TCNT count-down results in an underflow, the TCOR value is set in TCNT and the count-down continues from that value. TCOR is initialized to H'FFFFFFFF by a power-on reset or manual reset; it is not initialized in standby mode, and retains its contents. TCOR:
Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W 15 1 R/W 14 1 R/W 13 1 R/W 12 1 R/W 11 1 R/W 10 1 R/W 9 1 R/W 8 1 R/W 23 1 R/W 22 1 R/W 21 1 R/W 20 1 R/W 19 1 R/W 18 1 R/W 17 1 R/W 16 31 30 29 28 27 26 25 24
305
1 1 . 2 . 5 Timer Counters (TCNT) The timer counters are 32-bit read/write registers. The TMU has three timer counters, one for each channel. TCNT counts down upon input of a clock. The clock input is selected using the TPSC2-TPSC0 bits in the timer control register (TCR). When a TCNT count-down results in an underflow (H'00000000 H'FFFFFFFF), the underflow flag (UNF) in the timer control register (TCR) of the relevant channel is set. The TCOR value is simultaneously set in TCNT itself and the count-down continues from that value. Because the internal bus for the SH7708 Series on-chip supporting modules is 16 bits wide, a time lag can occur between the time when the upper 16 bits and lower 16 bits are read. Since TCNT counts sequentially, this time lag can create discrepancies between the data in the upper and lower halves. To correct the discrepancy, a buffer register is connected to TCNT so that upper and lower halves are not read separately. The entire 32-bit data in TCNT can thus be read at once. TCNT is initialized to H'FFFFFFFF by a power-on reset or manual reset. In standby mode, when the PLL1 multiplication factor is changed in clock mode 0, 1, 2, or 7, or when the MSTP2 bit is set to 1 in STBCR, TCNT retains its contents when the input clock selected for the channel is an external clock (TCLK) or the peripheral clock (Po), and continues operating when the selected clock is the on-chip RTC output clock (RTCCLK). TCNT:
Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 15 1 R/W 14 1 R/W 13 1 R/W 12 1 R/W 11 1 R/W 10 1 R/W 9 1 R/W 8 1 R/W 23 1 R/W 22 1 R/W 21 1 R/W 20 1 R/W 19 1 R/W 18 1 R/W 17 1 R/W 16 31 30 29 28 27 26 25 24
306
Bit: Bit name: Initial value: R/W:
7
6
5
4
3
2
1
0
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 1 . 2 . 6 Input Capture Register (TCPR2) The input capture register (TCPR2) is a read-only 32-bit register built only into timer 2. Control of TCPR2 setting conditions due to the TCLK pin is affected by the input capture function bits (ICPE1/ICPE2 and CKEG1/CKEG0)) in TCR2. When a TCPR2 setting indication due to the TCLK pin occurs, the value of TCNT2 is copied into TCPR2. TCNT2 is not initialized by a power-on reset or manual reset, or in standby mode. TCPR2:
Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: -- R -- R -- R -- R -- R -- R -- R -- R -- R 7 -- R 6 -- R 5 -- R 4 -- R 3 -- R 2 -- R 1 -- R 0 -- R 15 -- R 14 -- R 13 -- R 12 -- R 11 -- R 10 -- R 9 -- R 8 -- R 23 -- R 22 -- R 21 -- R 20 -- R 19 -- R 18 -- R 17 -- R 16 31 30 29 28 27 26 25 24
307
11.3
TMU Operation
1 1 . 3 . 1 Overview Each of the three channels has a 32-bit timer counter (TCNT) and a 32-bit timer constant register. The TCNT counts down. The auto-reload function enables synchronized counting and counting by external events. Channel 2 has an input capture function. 1 1 . 3 . 2 Basic Functions Counter Operation: When the STR0-STR2 bits in the timer start register (TSTR) are set, the corresponding timer counter (TCNT) starts counting. When a TCNT underflows (H'00000000 H'FFFFFFFF), the UNF flag of the corresponding timer control register (TCR) is set. At this time, if the UNIE bit in TCR is 1, an interrupt request is sent to the CPU. Also at this time, the value is copied from TCOR to TCNT and the down-count operation is continued. The count operation is set as follows (figure 11.2): 1. Select the counter clock with the TPSC2-TPSC0 bits in the timer control register (TCR). If the external clock is selected, set the TCLK pin to input mode with the TOCE bit in TOCR, and select its edge with the CKEG1 and CKEG0 bits in TCR. 2. Use the UNIE bit in TCR to set whether to generate an interrupt when TCNT underflows. 3. When using the input capture function, set the ICPE bits in TCR, including the choice of whether or not to use the interrupt function (channel 2 only). 4. Set a value in the timer constant register (TCOR) (the cycle is the set value plus 1). 5. Set the initial value in the timer counter (TCNT). 6. Set the STR bit in the timer start register (TSTR) to 1 to start operation.
308
Operation selection Select counter clock
(1)
Set underflow interrupt generation
(2) When using input capture function Set interrupt generation (3)
Set timer constant register Initialize timer counter
(4)
(5)
Start counting
(6)
Note: When an interrupt has been generated, clear the flag in the interrupt handler that caused it. If interrupts are enabled without clearing the flag, another interrupt will be generated.
Figure 11.2
Setting the Count Operation
309
Auto-Reload Count Operation: Figure 11.3 shows the TCNT auto-reload operation.
TCOR value set to TCNT during underflow
TCNT value TCOR
H'00000000 STR0-STR2 UNF
Time
Figure 11.3 TCNT Count Timing:
Auto-Reload Count Operation
* Internal Clock Operation: Set the TPSC2-TPSC0 bits in TCR to select whether peripheral module clock P or one of the four internal clocks created by dividing it is used (P/4, P/16, P/64, P/256). Figure 11.4 shows the timing.
P Internal clock TCNT input clock TCNT N+1 N N-1
Figure 11.4
Count Timing when Internal Clock Is Operating
* External Clock Operation: Set the TPSC2-TPSC0 bits in TCR to select the external clock (TCLK) as the timer clock. Use the CKEG1 and CKEG0 bits in TCR to select the detection edge. Rise, fall or both may be selected. The pulse width of the external clock must be at least 1.5 peripheral module clock cycles for single edges or 2.5 peripheral module clock cycles for both edges. A shorter pulse width will result in inaccurate operation. Figure 11.5 shows the timing for both-edge detection.
310
P External clock input pin TCNT input clock TCNT N+1 N N-1
Figure 11.5
Count Timing when External Clock Is Operating (Both Edges Detected)
* On-Chip RTC Clock Operation: Set the TPSC2-TPSC0 bits in TCR to select the on-chip RTC clock as the timer clock. Figure 11.6 shows the timing.
RTC output clock TCNT input clock TCNT N + 1 N N-1
Figure 11.6
Count Timing when On-Chip RTC Clock Is Operating
Input Capture Function: Channel 2 has an input capture function (figure 11.7). When using the input capture function, set the TCLK pin to input mode with the TCOE bit in the timer output control register (TOCR) and set the timer operation clock to internal clock or on-chip RTC clock with the TPCS2-TPCS0 bits in the timer control register (TCR). Also, designate use of the input capture function and whether to generate interrupts on using it with the IPCE1-IPCE0 bits in TCR, and designate the use of either the rising or falling edge of the TCLK pin to set the timer counter (TNCT) value into the input capture register (TCPR) with the CKEG1-CKEG0 bits in TCR. The input capture function cannot be used in standby mode.
311
TCNT value TCOR
TCOR value set to TCNT during underflow
H'00000000 TCLK
Time
TCPR2
Set TCNT value
ICPI
Figure 11.7
Operation Timing when Using the Input Capture Function (Using TCLK Rising Edge)
11.4
Interrupts
There are two sources of TMU interrupts: underflow interrupts (TUNI) and interrupts when using the input capture function (TICPI2). 1 1 . 4 . 1 Status Flag Set Timing UNF is set to 1 when the TCNT underflows (H'00000000 H'FFFFFFFF). Figure 11.8 shows the timing.
P TCNT Underflow signal UNF TUNI H'00000000 TCOR value
Figure 11.8
UNF Set Timing
312
1 1 . 4 . 2 Status Flag Clear Timing The status flag can be cleared by writing a 0 from the CPU. Figure 11.9 shows the timing.
TCR write cycle T1 P Peripheral address bus UNF, ICPF TCR address T2 T3
Figure 11.9
Status Flag Clear Timing
1 1 . 4 . 3 Interrupt Sources and Priorities The TMU produces underflow interrupts for each channel. When the interrupt request flag and interrupt enable bit are both set to 1, the interrupt is requested. Codes are set in the exception source register (INTEVT) for these interrupts and interrupt handling occurs according to the codes. The relative priorities of channels can be changed using the interrupt controller (see section 6, Interrupt Controller) and section 4, Exception Handling. Table 11.3 lists TMU interrupt sources. Table 11.3 TMU Interrupt Sources
Channel 0 1 2 2 Interrupt Source TUNI0 TUNI1 TUNI2 TICPI2 Description Underflow interrupt 0 Underflow interrupt 1 Underflow interrupt 2 Priority High

Input capture interrupt 2 Low
313
11.5
Usage Notes
1 1 . 5 . 1 Writing to Registers Synchronization processing is not performed for timer counting during register writes. When writing to registers, always clear the appropriate start bits for the channel (STR2-STR0) in the timer start register (TSTR) to halt timer counting. 1 1 . 5 . 2 Reading Registers Synchronization processing is performed for timer counting during register reads. When timer counting and register read processing are performed simultaneously, the register value before TCNT counting down (with synchronization processing) is read. 1 1 . 5 . 3 Clearing UNF in the TCR Register When the RTC (realtime clock) is specified for use as the TMU (timer) clock source in the SH7708, the procedure shown in the flowchart below should be used to clear the underflow flag (UNF) in the timer control register (TCR).
Clear UNF flag
Read UNF flag UNF = 0? Yes
No
Figure 11.10
UNF Flag Clearing
314
Section 12 Realtime Clock (RTC)
12.1 Overview
The SH7708 Series has a realtime clock (RTC) with its own 32.768-kHz crystal oscillator. 1 2 . 1 . 1 Features * Clock and calendar functions (BCD display): seconds, minutes, hours, date, day of the week, month, and year * 1-Hz to 64-Hz timer (binary display) * Start/stop function * 30-second adjust function * Alarm interrupt: frame comparison of seconds, minutes, hours, date, day of the week, and month can be used as conditions for the alarm interrupt * Cyclic interrupts: the interrupt cycle may be 1/256 second, 1/64 second, 1/16 second, 1/4 second, 1/2 second, 1 second, or 2 seconds * Carry interrupt: a carry interrupt indicates when a carry occurs during a counter read * Automatic leap year correction 1 2 . 1 . 2 Block Diagram The following abbreviations are used in the block diagram of the RTC (figure 12.1): R64CNT: 64-Hz counter RSECCNT: Second counter RMINCNT: Minute counter RHRCNT: Hour counter RWKCNT: Day of the week counter RDAYCNT: Date counter RMONCNT: Month counter RYRCNT: Year counter RSECAR: Second alarm register RMINAR: Minute alarm register RHRAR: Hour alarm register RWKAR: Day of the week alarm register RDAYAR: Date alarm register RMONAR: Month alarm register RCR1: RTC control register 1 RCR2: RTC control register 2
315
Externally connected circuit EXTAL2 Oscillator circuit XTAL2 32.768 kHz Prescaler (/ 2) RTCCLK 16.384 kHz 128 Hz
30second Reset ADJ
RSECCNT RMINCNT RHRCNT RWKCNT Prescaler (/ 128) RDAYCNT RMONCNT RYRCNT
ATI PRI
RSECAR RMINAR CUI Carry detection circuit RHRAR RWKAR RDAYAR RMONAR
RCR1 RCR2
Figure 12.1
RTC Block Diagram
316
Module bus
Interrupt control circuit
Comparator
RTC
Internal bus
R64CNT
Bus interface
1 2 . 1 . 3 Pin Configuration Table 12.1 shows the RTC pin configuration. Table 12.1RTC Pin Configuration
Pin RTC oscillator crystal pin RTC oscillator crystal pin Clock input/clock output AbbreviationI/O Description EXTAL2 XTAL2 TCLK I O Connects crystal to RTC oscillator Connects crystal to RTC oscillator
I/O External clock input pin/input capture control input pin/realtime clock (RTC) output pin (shared by TMU) -- -- Dedicated power-supply pin for RTC* Dedicated GND pin for RTC*
Dedicated power-supply pin for RTC Dedicated GND pin for RTC
Vcc (RTC) Vss (RTC)
Note: Power must be supplied to the RTC power supply pins even when the RTC is not used. Except in hardware standby mode, power must be supplied to all power supply pins, including these, even if only the RTC is used.
317
1 2 . 1 . 4 RTC
Register Configuration
Table 12.2 shows the RTC register configuration. Table 12.2RTC Registers
Name 64-Hz counter Second counter Minute counter Hour counter Day of week counter Date counter Month counter Year counter Second alarm register Minute alarm register Hour alarm register Day of week alarm register Date alarm register Month alarm register RTC control register 1 RTC control register 2 AbbreviationR/W R64CNT RSECCNT RMINCNT RHRCNT RWKCNT RDAYCNT RMONCNT RYRCNT RSECAR RMINAR RHRAR RWKAR RDAYAR RMONAR RCR1 RCR2 R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value Address Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* H'00 H'09 H'FFFFFEC0 H'FFFFFEC2 H'FFFFFEC4 H'FFFFFEC6 H'FFFFFEC8 H'FFFFFECA H'FFFFFECC H'FFFFFECE H'FFFFFED0 H'FFFFFED2 H'FFFFFED4 H'FFFFFED6 H'FFFFFED8 H'FFFFFEDA H'FFFFFEDC H'FFFFFEDE Access Size 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8
Note: Only the ENB bits of each register are initialized.
12.2
RTC Registers
1 2 . 2 . 1 64-Hz Counter (R64CNT) The 64-Hz counter (R64CNT) is an 8-bit read-only register that indicates the status of the RTC divider circuit between 64 Hz and 1 Hz. R64CNT is reset to H'00 by setting the RESET bit in RTC control register 2 (RCR2) or the ADJ bit in RCR2 to 1.
318
R64CNT is not initialized by a power-on reset or manual reset, or in standby mode. Bit 7 always reads 0.
Bit: Bit name: Initial value: R/W: 7 -- 0 R 6 1Hz -- R 5 2Hz -- R 4 4Hz -- R 3 8Hz -- R 2 16Hz -- R 1 32Hz -- R 0 64Hz -- R
1 2 . 2 . 2 Second Counter (RSECCNT) The second counter (RSECCNT) is an 8-bit read/write register used for setting/counting in the BCD-coded second section of the RTC. The count operation is performed by a carry for each second of the 64 Hz counter. The range that can be set is 00-59 (decimal). Errant operation will result if any other value is set. Carry out write processing after halting the count operation with the START bit in RCR2, or perform a write using the carry flag as shown in figure 12.2. RSECCNT is not initialized by a power-on reset or manual reset, or in standby mode.
Bit: Bit name: Initial value: R/W: 7 -- 0 R -- R/W 6 5 10 seconds -- R/W -- R/W -- R/W 4 3 2 1 0
1 second -- R/W -- R/W -- R/W
1 2 . 2 . 3 Minute Counter (RMINCNT) The minute counter (RMINCNT) is an 8-bit read/write register used for setting/counting in the BCD-coded minute section of the RTC. The count operation is performed by a carry for each minute of the second counter. The range that can be set is 00-59 (decimal). Errant operation will result if any other value is set. Carry out write processing after halting the count operation with the START bit in RCR2, or perform a write using the carry flag as shown in figure 12.2.
319
RMINCNT is not initialized by a power-on reset or manual reset, or in standby mode.
Bit: Bit name: Initial value: R/W: 7 -- 0 R -- R/W 6 5 10 minutes -- R/W -- R/W -- R/W 4 3 2 1 minute -- R/W -- R/W -- R/W 1 0
1 2 . 2 . 4 Hour Counter (RHRCNT) The hour counter (RHRCNT) is an 8-bit read/write register used for setting/counting in the BCDcoded hour section of the RTC. The count operation is performed by a carry for each 1 hour of the minute counter. The range that can be set is 00-23 (decimal). Errant operation will result if any other value is set. Carry out write processing after halting the count operation with the START bit in RCR2, or perform a write using the carry flag as shown in figure 12.2. RHRCNT is not initialized by a power-on reset or manual reset, or in standby mode.
Bit: Bit name: Initial value: R/W: 7 -- 0 R 6 -- 0 R 5 4 3 2 1 hour -- R/W -- R/W -- R/W -- R/W 1 0
10 hours -- R/W -- R/W
1 2 . 2 . 5 Day of the Week Counter (RWKCNT) The day of the week counter (RWKCNT) is an 8-bit read/write register used for setting/counting in the BCD-coded day of week section of the RTC. The count operation is performed by a carry for each day of the date counter. The range that can be set is 0-6 (decimal). Errant operation will result if any other value is set. Carry out write processing after halting the count operation with the START bit in RCR2, or perform a write using the carry flag as shown in figure 12.2. RWKCNT is not initialized by a power-on reset or manual reset, or in standby mode.
Bit: Bit name: Initial value: R/W: 7 -- 0 R 6 -- 0 R 5 -- 0 R 4 -- 0 R 3 -- 0 R -- R/W 2 1 Day of week -- R/W -- R/W 0
320
Days of the week are coded as shown in table 12.3. Table 12.3Day-of-Week Codes (RWKCNT)
Day of Week Sunday Monday Tuesday Wednesday Thursday Friday Saturday Code 0 1 2 3 4 5 6
1 2 . 2 . 6 Date Counter (RDAYCNT) The date counter (RDAYCNT) is an 8-bit read/write register used for setting/counting in the BCDcoded date section of the RTC. The count operation is performed by a carry for each day of the hour counter. The range that can be set is 01-31 (decimal). Errant operation will result if any other value is set. Carry out write processing after halting the count operation with the START bit in RCR2, or perform a write using the carry flag as shown in figure 12.2. RDAYCNT is not initialized by a power-on reset or manual reset, or in standby mode. The RDAYCNT range that can be set changes with each month and in leap years. Please confirm the correct setting.
Bit: Bit name: Initial value: R/W: 7 -- 0 R 6 -- 0 R 5 10 days -- R/W -- R/W -- R/W -- R/W 4 3 2 1 day -- R/W -- R/W 1 0
321
1 2 . 2 . 7 Month Counter (RMONCNT) The month counter (RMONCNT) is an 8-bit read/write register used for setting/counting in the BCD-coded month section of the RTC. The count operation is performed by a carry for each month of the date counter. The range that can be set is 00-12 (decimal). Errant operation will result if any other value is set. Carry out write processing after halting the count operation with the START bit in RCR2, or perform a write using the carry flag as shown in figure 12.2. RMONCNT is not initialized by a power-on reset or manual reset, or in standby mode.
Bit: Bit name: Initial value: R/W: 7 -- 0 R 6 -- 0 R 5 -- 0 R 4 10 months -- R/W -- R/W 3 2 1 month -- R/W -- R/W -- R/W 1 0
1 2 . 2 . 8 Year Counter (RYRCNT) The year counter (RYRCNT) is an 8-bit read/write register used for setting/counting in the BCDcoded year section of the RTC. The least significant 2 digits of the western calendar year are displayed. The count operation is performed by a carry for each year of the month counter. The range that can be set is 00-99 (decimal). Errant operation will result if any other value is set. Carry out write processing after halting the count operation with the START bit in RCR2, or perform a write using the carry flag as shown in figure 12.2. RYRCNT is not initialized by a power-on reset or manual reset, or in standby mode. Leap years are recognized by dividing the year counter value by 4 and obtaining a fractional result of 0.
Bit: Bit name: Initial value: R/W: -- R/W 7 6 10 years -- R/W -- R/W -- R/W -- R/W -- R/W 5 4 3 2 1 year -- R/W -- R/W 1 0
322
1 2 . 2 . 9 Second Alarm Register (RSECAR) The second alarm register (RSECAR) is an 8-bit read/write register, and an alarm register corresponding to the BCD-coded second section counter RSECCNT of the RTC. When the ENBbit is set to 1, a comparison with the RSECCNT value is performed. From among the RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, RMONAR registers, the counter and alarm register comparison is performed only on those with ENB bits set to 1, and if each of those coincide, an RTC alarm interrupt is generated. The range that can be set is 00-59 (decimal) + ENB bit. Errant operation will result if any other value is set. The ENB bit in RSECAR is initialized to 0 by a power-on reset. The remaining RSECAR fields are not initialized by a power-on reset or manual reset, or in standby mode.
Bit: Bit name: Initial value: R/W: 7 ENB 0 R/W -- R/W 6 5 10 seconds -- R/W -- R/W -- R/W 4 3 2 1 0
1 second -- R/W -- R/W -- R/W
1 2 . 2 . 1 0 Minute Alarm Register (RMINAR) The minute alarm register (RMINAR) is an 8-bit read/write register, and an alarm register corresponding to the BCD-coded minute section counter RMINCNT of the RTC. When the ENB bit is set to 1, a comparison with the RMINCNT value is performed. From among the RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, RMONAR registers, the counter and alarm register comparison is performed only on those with ENB bits set to 1, and if each of those coincide, an RTC alarm interrupt is generated. The range that can be set is 00-59 (decimal) + ENB bit. Errant operation will result if any other value is set. The ENB bit in RMINAR is initialized by a power-on reset. The remaining RMINAR fields are not initialized by a power-on reset or manual reset, or in standby mode. Contents are retained in a manual reset and in standby mode.
Bit: Bit name: Initial value: R/W: 7 ENB 0 R/W -- R/W 6 5 10 minutes -- R/W -- R/W -- R/W 4 3 2 1 minute -- R/W -- R/W -- R/W 1 0
323
1 2 . 2 . 1 1 Hour Alarm Register (RHRAR) The hour alarm register (RHRAR) is an 8-bit read/write register, and an alarm register corresponding to the BCD-coded hour section counter RHRCNT of the RTC. When the ENB bitisset to 1, a comparison with the RHRCNT value is performed. From among the RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, RMONAR registers, the counter and alarm register comparison is performed only on those with ENB bits set to 1, and if each of those coincide, an RTC alarm interrupt is generated. The range that can be set is 00-23 (decimal) + ENB bit. Errant operation will result if any other value is set. The ENB bit in RHRAR is initialized by a power-on reset. The remaining RHRAR fields are not initialized by a power-on reset or manual reset, or in standby mode. Contents are retained in a manual reset and in standby mode.
Bit: Bit name: Initial value: R/W: 7 ENB 0 R/W 6 -- 0 R 5 4 10 hours -- R/W -- R/W -- R/W -- R/W 3 2 1 hour -- R/W -- R/W 1 0
1 2 . 2 . 1 2 Day of the Week Alarm Register (RWKAR) The day of the week alarm register (RWKAR) is an 8-bit read/write register, and an alarm register corresponding to the BCD-coded day of week section counter RWKCNT of the RTC. When the ENB bit is set to 1, a comparison with the RWKCNT value is performed. From among the RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, RMONAR registers, the counter and alarm register comparison is performed only on those with ENB bits set to 1, and if each of those coincide, an RTC alarm interrupt is generated. The range that can be set is 0-6 (decimal) + ENB bit. Errant operation will result if any other value is set. The ENB bit in RWKAR is initialized by a power-on reset. The remaining RWKAR fields are not initialized by a power-on reset or manual reset, or in standby mode. Contents are retained in a manual reset and in standby mode.
Bit: Bit name: Initial value: R/W: 7 ENB 0 R/W 6 -- 0 R 5 -- 0 R 4 -- 0 R 3 -- 0 R -- R/W 2 1 Day of week -- R/W -- R/W 0
324
Days of the week are coded as shown in table 12.4. Table 12.4Day-of-Week Codes (RWKAR)
Day of Week Sunday Monday Tuesday Wednesday Thursday Friday Saturday Code 0 1 2 3 4 5 6
1 2 . 2 . 1 3 Date Alarm Register (RDAYAR) The date alarm register (RDAYAR) is an 8-bit read/write register, and an alarm register corresponding to the BCD-coded date section counter RDAYCNT of the RTC. When the ENB bit is set to 1, a comparison with the RDAYCNT value is performed. From among the registers RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, RMONAR, the counter and alarm register comparison is performed only on those with ENB bits set to 1, and if each of those coincide, an RTC alarm interrupt is generated. The range that can be set is 01-31 (decimal) + ENB bit. Errant operation will result if any other value is set. The RDAYCNT range that can be set changes with some months and in leap years. Please confirm the correct setting. The ENB bit in RDAYAR is initialized by a power-on reset. The remaining RDAYAR fields are not initialized by a power-on reset or manual reset, or in standby mode. Contents are retained in a manual reset and in standby mode.
Bit: Bit name: Initial value: R/W: 7 ENB 0 R/W 6 -- 0 R 5 10 days -- R/W -- R/W -- R/W -- R/W 4 3 2 1 day -- R/W -- R/W 1 0
325
1 2 . 2 . 1 4 Month Alarm Register (RMONAR) The month alarm register (RMONAR) is an 8-bit read/write register, and an alarm register corresponding to the BCD-coded month section counter RMONCNT of the RTC. When the ENB bit is set to 1, a comparison with the RMONCNT value is performed. From among the registers RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, RMONAR, the counter and alarm register comparison is performed only on those with ENB bits set to 1, and if each of those coincide, an RTC alarm interrupt is generated. The range that can be set is 01-12 (decimal) + ENB bit. Errant operation will result if any other value is set. The ENB bit in RMONAR is initialized by a power-on reset. The remaining RMONAR fields are not initialized by a power-on reset or manual reset, or in standby mode. Contents are retained in a manual reset and in standby mode.
Bit: Bit name: Initial value: R/W: 7 ENB 0 R/W 6 -- 0 R 5 -- 0 R 4 10 months -- R/W -- R/W 3 2 1 month -- R/W -- R/W -- R/W 1 0
1 2 . 2 . 1 5 RTC
Control Register 1 (RCR1)
The RTC control register 1 (RCR1) is an 8-bit read/write register that affects carry flags and alarm flags. It also selects whether to generate interrupts for each flag. Because flags are sometimes set after an operand read, do not use this register in read-modify-write processing. RCR1 is initialized to H'00 by a power-on reset. In a manual reset, all bits are initialized to 0 except for the CF flag, which is undefined. When using the CF flag, it must be initialized beforehand. This register is not initialized in standby mode.
Bit: Bit name: Initial value: R/W: 7 CF 0 R/W 6 -- 0 R 5 -- 0 R 4 CIE 0 R/W 3 AIE 0 R/W 2 -- 0 R 1 -- 0 R 0 AF 0 R/W
326
Bit 7--Carry Flag (CF): Status flag that indicates that a carry has occurred. CF is set to 1 when a count-up to R64CNT or RSECCNT occurs. A count register value read at this time cannot be guaranteed; another read is required.
Bit 7: CF 0 Description No count up of R64CNT or RSECCNT. Clearing condition: When 0 is written to CF value) Count up of R64CNT or RSECCNT. Setting condition: When 1 is written to CF (Initial
1
Bits 6, 5, 2, and 1--Reserved: These bits always read 0. The write value should always be 0. Bit 4--Carry Interrupt Enable Flag (CIE): When the carry flag (CF) is set to 1, the CIE bit enables interrupts.
Bit 4: CIE 0 1 Description A carry interrupt is not generated when the CF flag is set to 1 value) A carry interrupt is generated when the CF flag is set to 1 (Initial
Bit 3--Alarm Interrupt Enable Flag (AIE): When the alarm flag (AF) is set to 1, the AIE bit allows interrupts.
Bit 3: AIE 0 Description An alarm interrupt is not generated when the AF flag is set to 1 (Initial value) 1 An alarm interrupt is generated when the AF flag is set to 1
Bit 0--Alarm Flag (AF): The AF flag is set to 1 when the alarm time set in an alarm register (only registers with ENB bit set to 1) matches the clock and calendar time. This flag is cleared to 0 by writing 0, but retains its previous value if 1 is written.
Bit 0: AF 0 1 Description Clock/counter and alarm register have not matched since last reset to 0. Clearing condition: When 0 is written to AF (Initial value) Setting condition: Clock/counter and alarm register have matched (only registers with ENB set)*
Note: Contents do not change when 1 is written to AF.
327
1 2 . 2 . 1 6 RTC
Control Register 2 (RCR2)
The RTC control register 2 (RCR2) is an 8-bit read/write register for periodic interrupt control, 30second adjustment ADJ, divider circuit RESET, and RTC count start/stop control. It is initialized to H'09 by a power-on reset. It is not initialized by a manual reset or in standby mode, and retains its contents.
Bit: Bit name: Initial value: R/W: 7 PEF 0 R/W 6 PES2 0 R/W 5 PES1 0 R/W 4 PES0 0 R/W 3 RTCEN 1 R/W 2 ADJ 0 R/W 1 RESET 0 R/W 0 START 1 R/W
Bit 7--Periodic Interrupt Flag (PEF): Indicates interrupt generation with the period designated by the PES bits. When set to 1, PEF generates periodic interrupts.
Bit 7: PEF 0 Description Interrupts not generated with the period designated by the PES bits. Clearing condition: When 0 is written to PEF (Initial value) Interrupts generated with the period designated by the PES bits. Setting condition: When 1 is written to PEF
1
Bits 6-4--Periodic Interrupt Flags (PES2-PES0): These bits specify the periodic interrupt.
Bit 6: PES2 Bit 5: PES1 Bit 4: PES0 Description 0 0 0 1 1 0 1 1 0 0 1 1 0 1 No periodic interrupts generated (Initial value) Periodic interrupt generated every 1/256 second Periodic interrupt generated every 1/64 second Periodic interrupt generated every 1/16 second Periodic interrupt generated every 1/4 second Periodic interrupt generated every 1/2 second Periodic interrupt generated every 1 second Periodic interrupt generated every 2 seconds
Bit 3--RTCEN: Controls the operation of the crystal oscillator for the RTC.
328
Bit 3: RTCEN 0 1
Description Halts the crystal oscillator for the RTC. Runs the crystal oscillator for the RTC. value) (Initial
Bit 2--30-Second Adjustment (ADJ): When 1 is written to the ADJ bit, times of 29 seconds or less will be rounded to 00 seconds and 30 seconds or more to 1 minute. The divider circuit will be simultaneously reset. This bit always reads 0.
Bit 2: ADJ 0 1 (write) Description Runs normally. value) 30-second adjustment. (Initial
Bit 1--Reset (RESET): When 1 is written, initializes the divider circuit. This bit always reads 0.
Bit 1: RESET 0 1 Description Runs normally. value) Divider circuit is reset. (Initial
Bit 0--Start Bit (START): Halts and restarts the counter (clock).
Bit 0: START 0 1 Description Second, minute, hour, day, week, month, year counter halts. Second, minute, hour, day, week, month, year counter runs normally. (Initial value)
Note: The 64-Hz counter always runs unless stopped with the RTCEN bit.
12.3
RTC Operation
1 2 . 3 . 1 Initial Settings of Registers after Power-On All the registers should be set after the power is turned on. 1 2 . 3 . 2 Setting the Time
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Part (a) in figure 12.2 shows how to set the time when the clock is stopped. This works when the entire calendar or clock is to be set. Part (b) in figure 12.2 describes how to set the clock when the clock is running. This works when only part of the calendar or clock needs to be reset (e.g., changing only the seconds or only the hour). The write status is checked using the carry flags. When there is a carry during the writing of new data, the new data is automatically updated. Since this causes errors in the data, the data must be rewritten if the carry flag is set to 1. The interrupt function can be used to determine the status of the carry flag.
a. To reset the divider circuit and set the counter Write 1 to RESET and 0 to START in the RCR2 register
Stop clock, reset divider circuit Set seconds, minutes, hour, day, day of the week, month and year
Order is irrelevant
Start clock
Write 1 to START in the RCR2 register
b. To set the seconds-year counter
Clear the carry flag
Write 0 to CF in RCR1 Note: Set AF to 1 so that alarm flag is not cleared
Write the counter register
Yes Carry flag = 1? No Read RCR1 and check CF
Figure 12.2
Setting the Time
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1 2 . 3 . 3 Reading the Time Figure 12.3 shows how to read the time. If a carry occurs while reading the time, the correct time will not be obtained, so it must be read again. Part (a) in figure 12.3 shows the method of reading the time without using interrupts; part (b) in figure 12.3 shows the method using carry interrupts. To keep programming simple, method (a) should normally be used.
a. To read the time without using interrupts Disable the carry interrupt Clear the carry flag Read counter register Yes Carry flag = 1? No b. To use interrupts Read RCR1 and check CF Write 0 to CIE in RCR1 Write 0 to CF in RCR1 Note: Set AF to 1 so that alarm flag is not cleared.
Enable the carry interrupt Clear the carry flag Read counter register Yes Interrupt generated? No Disable the carry interrupt
Write 1 to CIE in RCR1, and write 0 to CF in RCR1 Note: Set AF in RCR1 to 1 so that alarm flag is not cleared.
Write 0 to CIE in RCR1
Figure 12.3
Reading the Time
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1 2 . 3 . 4 Alarm Function Figure 12.4 shows how to use the alarm function. Alarms can be generated using seconds, minutes, hours, day of the week, date, month, or any combination of these. Set the ENB bit (bit 7) in the register on which the alarm is placed to 1, and then set the alarm time in the lower bits. Clear the ENB bit in the register on which the alarm is placed to 0. When the clock and alarm times match, a 1 is set in the AF bit (bit 0) in RCR1. Alarm detection can be checked by reading this bit, but normally it is done by interrupt. If 1 is placed in the AIE bit (bit 3) in RCR1, an interrupt is generated when an alarm occurs.
Clock running
Clear alarm interrupt
Temporarily disable interrupts (clear AIE bit in RCR1 register to 0) to prevent erroneous interruption
Set alarm time
Set alarm interrupt Clear alarm flag
When interrupts are used, enable interrupts (set AIE bit in RCR1 register to 1) Flag must be reset (by clearing AF bit in RCR1 register to 0) since it was set during alarm time setting
Monitor alarm time (wait for interrupt or check alarm flag)
Figure 12.4
Using the Alarm Function
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1 2 . 3 . 5 Crystal Oscillator Circuit Crystal oscillator circuit constants (recommended values) are shown in table 12.5, and the RTC crystal oscillator circuit in figure 12.5. Table 12.5Recommended Oscillator Circuit Constants (Recommended Values)
fo s c 32.768 kHz Cin 10 to 22 pF C out 10 to 22 pF
SH7708 Series EXTAL2
Rf RD XTAL2
XTAL Cin Cout
Notes: 1. Select either the Cin or Cout side for frequency adjustment variable capacitor according to requirements such as frequency range, degree of stability, etc. 2. Built-in resistance value Rf (Typ value) = 10 M, RD (Typ value) = 400 k 3. Cin and Cout values include floating capacitance due to the wiring. Take care when using a ground plane. 4. The crystal oscillation settling time depends on the mounted circuit constants, floating capacitance, etc., and should be decided after consultation with the crystal resonator manufacturer. 5. Place the crystal resonator and load capacitors Cin and Cout as close as possible to the chip. (Correct oscillation may not be possible if there is externally induced noise in the EXTAL2 and XTAL2 pins.) 6. Ensure that the crystal resonator connection pin (EXTAL2, XTAL2) wiring is routed as far away as possible from other power lines (except GND) and signal lines.
Figure 12.5
Example of Crystal Oscillator Circuit Connection
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12.4
Usage Notes
1 2 . 4 . 1 Flag Clearing With the SH7708, the procedure shown in the flowchart below should be used to clear the carry flag (CF) and alarm flag (AF) in realtime clock (RTC) register RCR1 (RTC control register 1) and the peripheral interrupt flag (PEF) in register RCR2 (RTC control register 2).
Entire lot Clear AF flag
Wait for 63 s or more
1. Transition to standby mode 2. Change STC0, STC1 in FEQCR (frequency control register) 3. Change MSTP1 in STBCR (standby control register)
Figure 12.6
AF Flag Clearing
If an interval of at least 63 s is not allowed, the AF flag may not be set even if the setting conditions are satisfied. Use the same procedure for clearing the CF and PEF flags.
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Section 13 Serial Communication Interface (SCI)
13.1 Overview
The SH7708 Series has an on-chip serial communication interface (SCI) that supports both asynchronous and synchronous serial communication. It also has a multiprocessor communication function for serial communication among two or more processors. The SCI supports a smart card interface, which is a serial communications feature for IC card interfaces that conforms to the ISO/IEC standard 7816-3 for identification cards. See section 14, Smart Card Interface, for more information. 1 3 . 1 . 1 Features SCI features are listed below. * Asynchronous or synchronous can be selected as the serial communication mode. * Asynchronous mode: Serial data communication is synchronized in start-stop mode in character units. The SCI can communicate with a universal asynchronous receiver/transmitter (UART), an asynchronous communication interface adapter (ACIA), or any other communications chip that employs a standard asynchronous serial system. It can also communicate with two or more other processors using the multiprocessor communication function. The maximum bit rate is 937.5 kbps. There are twelve selectable serial data communication formats. Data length: Seven or eight bits Stop bit length: One or two bits Parity: Even, odd, or none Multiprocessor bit: 1 or 0 Receive error detection: Parity, overrun, and framing errors Break detection: By reading the RxD level directly from the serial port register (SCSPTR) when a framing error occurs * Synchronous mode: Serial data communication is synchronized with a clock signal. The SCI can communicate with other chips having a synchronous communication function. The maximum bit rate is 5 Mbps. There is one serial data communication format. Data length: Eight bits Receive error detection: Overrun errors * Full duplex communication: The transmitting and receiving sections are independent, so the SCI can transmit and receive simultaneously. Both sections use double buffering, so continuous data transfer is possible in both the transmit and receive directions. * On-chip baud rate generator with selectable bit rates
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* Internal or external transmit/receive clock source: From either baud rate generator (internal) or SCK pin (external) * Four types of interrupts: Transmit-data-empty, transmit-end, receive-data-full, and receive-error interrupts are requested independently. * When the SCI is not in use, it can be stopped by halting the clock supplied to it, saving power. 1 3 . 1 . 2 Block Diagram Figure 13.1 shows a block diagram of the SCI.
Bus interface
Module data bus
Internal data bus
SCRDR
SCTDR
RxD
SCRSR
SCTSR
TxD
SCSSR SCSCR SCSMR SCSPTR Transmit/ receive control
SCBRR P Baud rate generator P/4 P/16 P/64 Clock
Parity generation Parity check
SCK
External clock TEI TXI RXI ERI
SCI SCRSR: SCRDR: SCTSR: SCTDR: Receive shift register Receive data register Transmit shift register Transmit data register SCSMR: SCSCR: SCSSR: SCBRR: SCSPTR: Serial mode register Serial control register Serial status register Bit rate register Serial port register
Figure 13.1
SCI Block Diagram
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1 3 . 1 . 3 Pin Configuration The SCI has the serial pins summarized in table 13.1. Table 13.1SCI Pins
Pin Name Serial clock pin Receive data pin Transmit data pin AbbreviationInput/Output Function SCK RxD TxD Input/output Input Output Clock input/output Receive data input Transmit data output
Note: These pins function as mode input pins MD0-MD02 after a power-on reset. They are made to function as serial pins by performing SCI operation settings with the TE, RE, CKEI, and CKE0 bits in SCSCR and the C/A bit in SCSMR. Break status transmission and detection can be performed by means of the SCI's SCSPTR register.
1 3 . 1 . 4 Register Configuration Table 13.2 summarizes the SCI internal registers. These registers select the communication mode (asynchronous or synchronous), specify the data format and bit rate, and control the transmitter and receiver sections. Table 13.2 Registers
Name Serial mode register Bit rate register Serial control register Transmit data register Serial status register Receive data register Serial port register Abbreviation R / W SCSMR SCBRR SCSCR SCTDR SCSSR SCRDR SCSPTR R/W R/W R/W R/W R/(W)* R R/W
1
Initial Value* 2 H'00 H'FF H'00 H'FF H'84 H'00 Undefined (Initialized)*3
Address H'FFFFFE80 H'FFFFFE82 H'FFFFFE84 H'FFFFFE86 H'FFFFFE88 H'FFFFFE8A H'FFFFFF7C
Access Size 8 8 8 8 8 8 8
Notes: 1 Only 0 can be written, to clear the flags. 2 Initialized by power-on reset or manual reset. 3. All bits except 2 and 0 are initialized to 0. The value of bits 2 and 0 is undefined.
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13.2
Register Descriptions
1 3 . 2 . 1 Receive Shift Register (SCRSR) The receive shift register (SCRSR) receives serial data. Data input at the RxD pin is loaded into SCRSR in the order received, LSB (bit 0) first, converting the data to parallel form. When one byte has been received, it is automatically transferred to SCRDR. The CPU cannot read or write SCRSR directly.
Bit: Bit name: R/W: -- -- -- -- -- -- -- -- 7 6 5 4 3 2 1 0
1 3 . 2 . 2 Receive Data Register (SCRDR) The receive data register (SCRDR) stores serial receive data. The SCI completes the reception of one byte of serial data by moving the received data from the receive shift register (SCRSR) into SCRDR for storage. SCRSR is then ready to receive the next data. This double buffering allows the SCI to receive data continuously. The CPU can read but not write to SCRDR. SCRDR is initialized to H'00 by a reset and in standby or module standby mode.
Bit: Bit name: Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 7 6 5 4 3 2 1 0
1 3 . 2 . 3 Transmit Shift Register (SCTSR) The transmit shift register (SCTSR) transmits serial data. The SCI loads transmit data from the transmit data register (SCTDR) into SCTSR, then transmits the data serially from the TxD pin, LSB (bit 0) first. After transmitting one data byte, the SCI automatically loads the next transmit data from SCTDR into SCTSR and starts transmitting again. If the TDRE bit in SCSSR is 1, however, the SCI does not load the SCTDR contents into SCTSR. The CPU cannot read or write to SCTSR directly.
Bit: Bit name: R/W: 338 -- -- -- -- -- -- -- -- 7 6 5 4 3 2 1 0
1 3 . 2 . 4 Transmit Data Register (SCTDR) The transmit data register (SCTDR) is an 8-bit register that stores data for serial transmission. When the SCI detects that the transmit shift register (SCTSR) is empty, it moves transmit data written in SCTDR into SCTSR and starts serial transmission. Continuous serial transmission is possible by writing the next transmit data in SCTDR during serial transmission from SCTSR. The CPU can always read and write to SCTDR. SCTDR is initialized to H'FF by a reset and in standby or module standby mode.
Bit: Bit name: Initial value: R/W: 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 7 6 5 4 3 2 1 0
1 3 . 2 . 5 Serial Mode Register (SCSMR) The serial mode register (SCSMR) is an 8-bit register that specifies the SCI serial communication format and selects the clock source for the baud rate generator. The CPU can always read and write to SCSMR. SCSMR is initialized to H'00 by a reset and in standby or module standby mode.
Bit: Bit name: Initial value: R/W: 7 C/A 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 O/E 0 R/W 3 STOP 0 R/W 2 MP 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W
Bit 7--Communication Mode (C/A): Selects whether the SCI operates in asynchronous or synchronous mode.
Bit 7: C/A 0 1 Description Asynchronous mode value) Synchronous mode (Initial
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Bit 6--Character Length (CHR): Selects 7-bit or 8-bit data in asynchronous mode. In synchronous mode, the data length is always 8 bits, regardless of the CHR setting.
Bit 6: CHR 0 1 Description 8-bit data value) (Initial
7-bit data. (When 7-bit data is selected, the MSB (bit 7) of the transmit data register is not transmitted.)
Bit 5--Parity Enable (PE): Selects whether to add a parity bit to transmit data and to check the parity of receive data, in asynchronous mode. In synchronous mode, a parity bit is neither added nor checked, regardless of the PE setting.
Bit 5: PE 0 1 Description Parity bit not added or checked value) (Initial
Parity bit added and checked. When PE is set to 1, an even or odd parity bit is added to transmit data, depending on the parity mode (O/E) setting. Receive data parity is checked according to the even/odd (O/E) mode setting.
Bit 4--Parity Mode (O/E): Selects even or odd parity when parity bits are added and checked. The O/E setting is used only in asynchronous mode and only when the parity enable bit (PE) is set to 1 to enable parity addition and checking. The O/E setting is ignored in synchronous mode, and in asynchronous mode when parity addition and checking is disabled.
Bit 4: O/E 0 Description Even parity value) (Initial
If even parity is selected, the parity bit is added to transmit data to make an even number of 1s in the transmitted character and parity bit combined. Receive data is checked to see if it has an even number of 1s in the received character and parity bit combined. 1 Odd parity If odd parity is selected, the parity bit is added to transmit data to make an odd number of 1s in the transmitted character and parity bit combined. Receive data is checked to see if it has an odd number of 1s in the received character and parity bit combined.
340
Bit 3--Stop Bit Length (STOP): Selects one or two bits as the stop bit length in asynchronous mode. This setting is used only in asynchronous mode. It is ignored in synchronous mode because no stop bits are added. In receiving, only the first stop bit is checked, regardless of the STOP bit setting. If the second stop bit is 1, it is treated as a stop bit, but if the second stop bit is 0, it is treated as the start bit of the next incoming character.
Bit 3: STOP 0 Description One stop bit value) (Initial
In transmitting, a single 1-bit is added at the end of each transmitted character. 1 Two stop bits In transmitting, two 1-bits are added at the end of each transmitted character.
Bit 2--Multiprocessor Mode (MP): Selects multiprocessor format. When multiprocessor format is selected, settings of the parity enable (PE) and parity mode (O/E) bits are ignored. The MP bit setting is used only in asynchronous mode; it is ignored in synchronous mode. For the multiprocessor communication function, see section 13.3.3, Multiprocessor Communication.
Bit 2: MP 0 1 Description Multiprocessor function disabled value) Multiprocessor format selected (Initial
Bits 1 and 0--Clock Select 1 and 0 (CKS1 and CKS0): These bits select the internal clock source of the on-chip baud rate generator. Four clock sources are available: P, P/4, P/16 and P/64. For further information on the clock source, bit rate register settings, and baud rate, see section 13.2.9, Bit Rate Register.
Bit 1: CKS1 0 Bit 0: CKS0 0 1 1 0 1 Note: P: Peripheral clock Description P value) P/4 P/16 P/64 (Initial
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1 3 . 2 . 6 Serial Control Register (SCSCR) The serial control register (SCSCR) operates the SCI transmitter/receiver, selects the serial clock output in asynchronous mode, enables/disables interrupt requests, and selects the transmit/receive clock source. The CPU can always read and write to SCSCR. SCSCR is initialized to H'00 by a reset and in standby or module standby mode.
Bit: Bit name: Initial value: R/W: 7 TIE 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W 2 TEIE 0 R/W 1 CKE1 0 R/W 0 CKE0 0 R/W
Bit 7--Transmit Interrupt Enable (TIE): Enables or disables the transmit-data-empty interrupt (TXI) requested when the transmit data register empty bit (TDRE) in the serial status register (SCSSR) is set to 1 due to transfer of serial transmit data from SCTDR to SCTSR.
Bit 7: TIE 0 Description Transmit-data-empty interrupt request (TXI) is disabled. value) (Initial
The TXI interrupt request can be cleared by reading TDRE after it has been set to 1, then clearing TDRE to 0, or by clearing TIE to 0. 1 Transmit-data-empty interrupt request (TXI) is enabled.
Bit 6--Receive Interrupt Enable (RIE): Enables or disables the receive-data-full interrupt (RXI) requested when the receive data register full bit (RDRF) in the serial status register (SCSSR) is set to 1 due to transfer of serial receive data from SCRSR to SCRDR. It also enables or disables receive-error interrupt (ERI) requests.
Bit 6: RIE 0 Description Receive-data-full interrupt (RXI) and receive-error interrupt (ERI) requests are disabled. (Initial value) RXI and ERI interrupt requests can be cleared by reading the RDRF flag or error flag (FER, PER, or ORER) after it has been set to 1, then clearing the flag to 0, or by clearing RIE to 0. 1 Receive-data-full interrupt (RXI) and receive-error interrupt (ERI) requests are enabled.
Bit 5--Transmit Enable (TE): Enables or disables the SCI serial transmitter.
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Bit 5: TE 0
Description Transmitter disabled value) (Initial
The transmit data register empty bit (TDRE) in the serial status register (SCSSR) is locked at 1. 1 Transmitter enabled Serial transmission starts when the transmit data register empty (TDRE) bit in the serial status register (SCSSR) is cleared to 0 after writing of transmit data into SCTDR. Select the transmit format in SCSMR before setting TE to 1.
Bit 4--Receive Enable (RE): Enables or disables the SCI serial receiver.
Bit 4: RE 0 Description Receiver disabled value) (Initial
Clearing RE to 0 does not affect the receive flags (RDRF, FER, PER, ORER). These flags retain their previous values. 1 Receiver enabled Serial reception starts when a start bit is detected in asynchronous mode, or synchronous clock input is detected in synchronous mode. Select the receive format in SCSMR before setting RE to 1.
Bit 3--Multiprocessor Interrupt Enable (MPIE): Enables or disables multiprocessor interrupts. The MPIE setting is used only in asynchronous mode, and only if the multiprocessor mode bit (MP) in the serial mode register (SCSMR) is set to 1 during reception. The MPIE setting is ignored in synchronous mode or when the MP bit is cleared to0.
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Bit 3: MPIE 0
Description Multiprocessor interrupts are disabled (normal receive operation). (Initial value) MPIE is cleared to 0 by writing 0 to it, or when the multiprocessor bit (MPB) is set to 1 in receive data. Multiprocessor interrupts are enabled. Receive-data-full interrupt requests (RXI), receive-error interrupt requests (ERI), and setting of the RDRF, FER, and ORER status flags in the serial status register (SCSSR) are disabled until data with a multiprocessor bit of 1 is received. The SCI does not transfer receive data from SCRSR to SCRDR, does not detect receive errors, and does not set the RDRF, FER, and ORER flags in the serial status register (SCSSR). When it receives data that includes MPB = 1, the SCSSR's MPB flag is set to 1, and the SCI automatically clears MPIE to 0, generates RXI and ERI interrupts (if the TIE and RIE bits in SCSCR are set to 1), and allows the FER and ORER bits to be set.
1
Bit 2--Transmit-End Interrupt Enable (TEIE): Enables or disables the transmit-end interrupt (TEI) requested if SCTDR does not contain new transmit data when the MSB is transmitted.
Bit 2: TEIE 0 1 Description Transmit-end interrupt (TEI) requests are disabled.* value) Transmit-end interrupt (TEI) requests are enabled.* (Initial
Note: The TEI request can be cleared by reading the TDRE bit in the serial status register (SCSSR) after it has been set to 1, then clearing TDRE to 0 and clearing the transmit end (TEND) bit to 0, or by clearing the TEIE bit to 0.
Bits 1 and 0--Clock Enable 1 and 0 (CKE1 and CKE0): These bits select the SCI clock source and enable or disable clock output from the SCK pin. Depending on the combination of CKE1 and CKE0, the SCK pin can be used for serial clock output or serial clock input. The CKE0 setting is valid only in asynchronous mode, and only when the SCI is internally clocked (CKE1 = 0). The CKE0 setting is ignored in synchronous mode, or when an external clock source is selected (CKE1 = 1). Before selecting the SCI operating mode in the serial mode register (SCSMR), set CKE1 and CKE0. For further details on selection of the SCI clock source, see table 13.9 in section 13.3, Operation.
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Bit 1: Bit 0: C K E 1 C K E 0 Description 0 0 Asynchronous mode Internal clock, SCK pin used for input pin (input signal is ignored) (Initial value) Internal clock, SCK pin used for serial clock output (Initial value) Internal clock, SCK pin used for clock output*1 Internal clock, SCK pin used for serial clock output External clock, SCK pin used for clock input*2 External clock, SCK pin used for serial clock input External clock, SCK pin used for clock input*2 External clock, SCK pin used for serial clock input
Synchronous mode
1
Asynchronous mode Synchronous mode
1
0
Asynchronous mode Synchronous mode
1
Asynchronous mode Synchronous mode
Notes: 1. The output clock frequency is the same as the bit rate. 2 The input clock frequency is 16 times the bit rate.
1 3 . 2 . 7 Serial Status Register (SCSSR) The serial status register (SCSSR) is an 8-bit register containing multiprocessor bit values, and status flags that indicate the SCI operating status. The CPU can always read and write to SCSSR, but cannot write 1 in the status flags (TDRE, RDRF, ORER, PER, and FER). These flags can be cleared to 0 only if they have first been read (after being set to 1). Bits 2 (TEND) and 1 (MPB) are read-only bits that cannot be written. SCSSR is initialized to H'84 by a reset and in standby or module standby mode.
Bit: Bit name: Initial value: R/W: 7 TDRE 1 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 FER 0 R/(W)* 3 PER 0 R/(W)* 2 TEND 1 R 1 MPB 0 R 0 MPBT 0 R/W
Note: Only 0 can be written, to clear the flag.
Bit 7--Transmit Data Register Empty (TDRE): Indicates that the SCI has loaded transmit data from SCTDR into SCTSR and new serial transmit data can be written in SCTDR.
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Bit 7: TDRE 0
Description SCTDR contains valid transmit data. TDRE is cleared to 0 when software reads TDRE after it has been set to 1, then writes 0 in TDRE, or data is written in SCTDR.
1
SCTDR does not contain valid transmit data. value)
(Initial
TDRE is set to 1 when the chip is reset or enters standby mode, the TE bit in the serial control register (SCSCR) is cleared to 0, or SCTDR contents are loaded into SCTSR, so new data can be written in SCTDR.
Bit 6--Receive Data Register Full (RDRF): Indicates that SCRDR contains received data.
Bit 6: RDRF 0 Description SCRDR does not contain valid received data. value) (Initial
RDRF is cleared to 0 when the chip is reset or enters standby mode, software reads RDRF after it has been set to 1, then writes 0 in RDRF, or data is read from SCRDR. 1 SCRDR contains valid received data. RDRF is set to 1 when serial data is received normally and transferred from SCRSR to SCRDR. Note: SCRDR and RDRF are not affected by detection of receive errors or by clearing of the RE bit to 0 in the serial control register. They retain their previous contents. If RDRF is still set to 1 when reception of the next data ends, an overrun error (ORER) occurs and the receive data is lost.
Bit 5--Overrun Error (ORER): Indicates that data reception aborted due to an overrun error.
Bit 5: ORER 0 Description Receiving is in progress or has ended normally. value) (Initial
Clearing the RE bit to 0 in the serial control register does not affect the ORER bit, which retains its previous value. ORER is cleared to 0 when the chip is reset or enters standby mode or software reads ORER after it has been set to 1, then writes 0 in ORER. 1 A receive overrun error occurred. SCRDR continues to hold the data received before the overrun error, so subsequent receive data is lost. Serial receiving cannot continue while ORER is set to 1. In synchronous mode, serial transmitting is also disabled. ORER is set to 1 if reception of the next serial data ends when RDRF is set to 1.
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Bit 4--Framing Error (FER): Indicates that data reception aborted due to a framing error in asynchronous mode.
Bit 4: FER 0 Description Receiving is in progress or has ended normally. value) (Initial
Clearing the RE bit to 0 in the serial control register does not affect the FER bit, which retains its previous value. FER is cleared to 0 when the chip is reset or enters standby mode or software reads FER after it has been set to 1, then writes 0 in FER. 1 A receive framing error occurred. When the stop bit length is two bits, only the first bit is checked. The second stop bit is not checked. When a framing error occurs, the SCI transfers the receive data into SCRDR but does not set RDRF. Serial receiving cannot continue while FER is set to 1. In synchronous mode, serial transmitting is also disabled. FER is set to 1 if the stop bit at the end of receive data is checked and found to be 0.
Bit 3--Parity Error (PER): Indicates that data reception (with parity) aborted due to a parity error in asynchronous mode.
Bit 3: PER 0 Description Receiving is in progress or has ended normally. value) (Initial
Clearing the RE bit to 0 in the serial control register does not affect the PER bit, which retains its previous value. PER is cleared to 0 when the chip is reset or enters standby mode or software reads PER after it has been set to 1, then writes 0 in PER. 1 A receive parity error occurred. When a parity error occurs, the SCI transfers the receive data into SCRDR but does not set RDRF. Serial receiving cannot continue while PER is set to 1. In synchronous mode, serial transmitting is also disabled. PER is set to 1 if the number of 1s in receive data, including the parity bit, does not match the even or odd parity setting of the parity mode bit (O/E) in the serial mode register (SCSMR).
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Bit 2--Transmit End (TEND): Indicates that when the last bit of a serial character was transmitted, SCTDR did not contain valid data, so transmission has ended. TEND is a read-only bit and cannot be written.
Bit 2: TEND 0 Description Transmission is in progress. TEND is cleared to 0 when software reads TDRE after it has been set to 1, then writes 0 in TDRE, or data is written in SCTDR. 1 End of transmission. value) (Initial
TEND is set to 1 when the chip is reset or enters standby mode, TE is cleared to 0 in the serial control register (SCSCR), or TDRE is 1 when the last bit of a one-byte serial character is transmitted.
Bit 1--Multiprocessor Bit (MPB): Stores the value of the multiprocessor bit in receive data when a multiprocessor format is selected for receiving in asynchronous mode. MPB is a read-only bit and cannot be written.
Bit 1: MPB 0 Description Multiprocessor bit value in receive data is 0. value) (Initial
If RE is cleared to 0 when a multiprocessor format is selected, the MPB retains its previousvalue. 1 Multiprocessor bit value in receive data is 1.
Bit 0--Multiprocessor Bit Transfer (MPBT): Stores the value of the multiprocessor bit added to transmit data when a multiprocessor format is selected for transmitting in asynchronous mode. The MPBT setting is ignored in synchronous mode, when a multiprocessor format is not selected, or when the SCI is not transmitting.
Bit 0: MPBT 0 1 Description Multiprocessor bit value in transmit data is 0. value) Multiprocessor bit value in transmit data is 1. (Initial
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1 3 . 2 . 8 Serial Port Register (SCSPTR) The serial port register (SCSPTR) is an 8-bit register that the CPU can always read and write. It controls I/O and data of the port multiplexed with the serial communications interface (SCI) pins. Input data can be read from the RxD pin and output data can be transmitted to the TxD pin; this controls breaks for serial transmission and reception. SCSPTR is initialized to H'00 by a power-on reset. It is not initialized by a manual reset or in standby mode.
Bit: Bit name: Initial value: R/W: 7 -- 0 R 6 -- 0 R 5 -- 0 R 4 -- 0 R 3 2 1 0
SPB1IO SPB1DT SPB0IO SPB0DT 0 R/W -- R/W 0 R/W -- R/W
Bits 7 to 4--Reserved: These bits always read 0. The write value should always be 0. Bit 3--Serial Port Clock Port I/O (SPB1IO): Specifies serial port SCK pin input/output. When the SCK pin is actually set as a port output pin and outputs the value set by the SPB1DT bit, the C/A bit in SCSMR and the CKE1 and CKE0 bits in SCSCR should be cleared to 0.
Bit 3: SPB1IO 0 1 Description The SPB1DT value is not output to the SCK pin. The SPB1DT bit value is output to the SCK pin. (Initial value)
Bit 2--Serial Port Clock Port Data (SPB1DT): Specifies the serial port SCK pin input/output data. Input or output is specified by the SPB1IO bit (see the description of SPB1IO for details). When output is specified, the value of the SPB1DT bit is output to the SCK pin. The SCK pin value is read from the SPB1DT bit regardless of the value of the SPB1IO bit. The initial value of this bit after a power-on reset is undefined.
Bit 2: SPB1DT 0 1 Description I/O data level is low. I/O data level is high. (Initial value)
Bit 1--Serial Port Break I/O (SPB0IO): Specifies the serial port TxD pin output condition. When the TxD pin is actually set as a port output pin and outputs the value set by the SPB0DT bit, the TE bit in SCSCR should be cleared to 0.
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Bit 1: SPB0IO 0 1
Description The SPB0DT bit value is not output to the TxD pin. The SPB0DT bit value is output to the TxD pin. (Initial value)
Bit 0--Serial Port Break Data (SPB0DT): Specifies the serial port I/O data. Use the SPB0IO bit to specify input or output of TxD pin. See the description of SPB0IO for details. SPB0DT bit is output to the TxD pin when specified as output. The RxD pin value is read from the SPB0IO bit regardless of the SPB0IO bit value. The initial value is undefined.
Bit 0 : SPB0DT 0 1 Description I/O data level is low. I/O data level is high. (Initial value)
Block diagrams of the SCI I/O port pins are shown in figures 15.2 to 15.4 in section 15, I/O Ports. 1 3 . 2 . 9 Bit Rate Register (SCBRR)
The bit rate register (SCBRR) is an 8-bit register that, together with the baud rate generator clock source selected by the CKS1 and CKS0 bits in the serial mode register (SCSMR), determines the serial transmit/receive bit rate. The CPU can always read and write to SCBRR. SCBRR is initialized to H'FF by a reset and in module standby or standby mode. Each channel has independent baud rate generator control, so different values can be set in the two channels.
Bit: Bit name: Initial value: R/W: 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 7 6 5 4 3 2 1 0
The SCBRR setting is calculated as follows: Asynchronous mode: N = [P/(64 x 22n - 1 x B)] x 106 - 1 Synchronous mode: N = [P/(8 x 22n - 1 x B)] x 106 - 1 B: Bit rate (bit/s) N: SCBRR setting for baud rate generator (0 N 255) P: Operating frequency for peripheral modules (MHz) n: Baud rate generator clock source (n = 0, 1, 2, 3) (for the clock sources and values of n, see table 13.3.)
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Table 13.3 SCSMR Settings
SCSMR Settings n 0 1 2 3 Clock Source P P/4 P/16 P/64 CKS1 0 0 1 1 CKS0 0 1 0 1
Note: The bit rate error for asynchronous mode is given by the following formula: Error (%) = {P( x 106)/[(N + 1) x B x 64 x 22n - 1] - 1 }x 100
Table 13.4 lists examples of SCBRR settings in asynchronous mode; table 13.5 lists examples of SCBRR settings in synchronous mode. Table 13.4 Bit Rates and SCBRR Settings in Asynchronous Mode
P (MHz) 2 Bit Rate (Bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 1 1 0 0 0 0 0 0 0 0 0 N 141 103 207 103 51 25 12 6 2 1 1 Error (%)n 0.03 0.16 0.16 0.16 0.16 0.16 0.16 -6.99 8.51 0.00 -18.62 1 1 0 0 0 0 0 0 0 0 0 2.097152 N 148 108 217 108 54 26 13 6 2 1 1 Error (%)n -0.04 0.21 0.21 0.21 -0.70 1.14 -2.48 -2.48 13.78 4.86 -14.67 1 1 0 0 0 0 0 0 0 0 0 N 174 127 255 127 63 31 15 7 3 1 1 2.4576 Error (%) -0.26 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 22.88 0.00
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Table 13.4 Bit Rates and SCBRR Settings in Asynchronous Mode (cont)
P (MHz) 3 Bit Rate (Bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 1 1 1 0 0 0 0 0 0 0 -- N 212 155 77 155 77 38 19 9 4 2 -- Error (%)n 0.03 0.16 0.16 0.16 0.16 0.16 -2.34 -2.34 -2.34 0.00 -- 2 1 1 0 0 0 0 0 0 -- 0 N 64 191 95 191 95 47 23 11 5 -- 2 3.6864 Error (%)n 0.70 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -- 0.00 2 1 1 0 0 0 0 0 0 0 0 N 70 207 103 207 103 51 25 12 6 3 2 4 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -6.99 0.00 8.51
P (MHz) 4.9152 Bit Rate (Bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 1 1 0 0 0 0 0 0 0 0 N 86 255 127 255 127 63 31 15 7 4 3 Error (%)n 0.31 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 2 2 1 1 0 0 0 0 0 0 0 N 88 64 129 64 129 64 32 15 7 4 3 5 Error (%)n -0.25 0.16 0.16 0.16 0.16 0.16 -1.36 1.73 1.73 0.00 1.73 2 2 1 1 0 0 0 0 0 0 0 N 106 77 155 77 155 77 38 19 9 5 4 6 Error (%) -0.44 0.16 0.16 0.16 0.16 0.16 0.16 -2.34 -2.34 0.00 -2.34
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Table 13.4 Bit Rates and SCBRR Settings in Asynchronous Mode (cont)
P (MHz) 6.144 Bit Rate (Bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 2 1 1 0 0 0 0 0 0 0 N 108 79 159 79 159 79 39 19 9 5 4 Error (%)n 0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 2.40 0.00 2 2 1 1 0 0 0 0 0 0 0 N 130 95 191 95 191 95 47 23 11 6 5 7.3728 Error (%)n -0.07 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 5.33 0.00 2 2 1 1 0 0 0 0 0 0 0 N 141 103 207 103 207 103 51 25 12 7 6 8 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 -6.99
P (MHz) 9.8304 Bit Rate (Bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 2 1 1 0 0 0 0 0 0 0 N 174 127 255 127 255 127 63 31 15 9 7 Error (%) n -0.26 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 2 2 2 1 1 0 0 0 0 0 0 N 177 129 64 129 64 129 64 32 15 9 7 10 Error (%) n -0.25 0.16 0.16 0.16 0.16 0.16 0.16 2 2 2 1 1 0 0 N 212 155 77 155 77 155 77 38 19 11 9 12 Error (%) n 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 2 2 2 1 1 0 0 0 0 0 12.288 N 217 159 79 159 79 159 79 39 19 11 9 Error (%) 0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 2.40 0.00
-1.36 0 1.73 0.00 1.73 0 0 0
-2.34 0
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Table 13.4 Bit Rates and SCBRR Settings in Asynchronous Mode (cont)
P (MHz) 14.7456 Bit Rate (Bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 3 2 2 1 1 0 0 0 0 0 0 N 64 191 95 191 95 191 95 47 23 14 11 Error (%) n 0.70 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 3 2 2 1 1 0 0 0 0 0 0 N 70 207 103 207 103 207 103 51 25 15 12 16 Error (%) n 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 0.16 3 2 2 1 1 0 0 0 0 0 0 19.6608 N 86 255 127 255 127 255 127 63 31 19 15 Error (%) n 0.31 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 3 3 2 2 1 0 0 0 0 0 0 N 88 64 129 64 129 64 129 64 32 19 15 20 Error (%) -0.25 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -1.36 0.00 1.73
P (MHz) 24 Bit Rate (Bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 3 3 2 2 1 1 0 0 0 0 0 N 106 77 155 77 155 77 155 77 38 23 19 Error (%) n -0.44 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 -2.34 3 3 2 2 1 1 0 0 0 0 0 24.576 N 108 79 159 79 159 79 159 79 39 24 19 Error (%) n 0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 3 3 2 2 1 1 0 0 0 0 0 28.7 N 126 92 186 92 186 92 186 92 46 28 22 Error (%) n 0.31 0.46 3 3 N 132 97 194 97 194 97 194 97 48 29 23 30 Error (%) 0.13 -0.35 0.16 -0.35 0.16 -0.35 -1.36 -0.35 -0.35 0.00 1.73
-0.08 2 0.46 2
-0.08 1 0.46 -0.08 0.46 -0.61 -1.03 1.55 1 0 0 0 0 0
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Table 13.5 Bit Rates and SCBRR Settings in Synchronous Mode
P (MHz) Bit Rate (Bit/s) 110 250 500 1k 2.5k 5k 10k 25k 50k 100k 250k 500k 1M 2M 4 n -- 2 2 1 1 0 0 0 0 0 0 0 0 -- N -- 249 124 249 99 199 99 39 19 9 3 1 0* -- n -- 3 2 2 1 1 0 0 0 0 0 0 0 0 8 N -- 124 249 124 199 99 199 79 39 19 7 3 1 0* n -- 3 3 2 2 1 1 0 0 0 0 0 0 0 16 N -- 249 124 249 99 199 99 159 79 39 15 7 3 1 n -- -- 3 3 2 2 1 1 0 0 -- -- -- -- 28.7 N -- -- 223 111 178 89 178 71 143 71 -- -- -- -- n -- -- 3 3 2 2 1 1 0 0 0 0 -- -- 30 N -- -- 233 116 187 93 187 74 149 74 29 14 -- --
Note: Settings with an error of 1% or less are recommended. Legend Blank: No setting possible --: Setting possible, but error occurs *: Continuous transmit/receive operation not possible
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Table 13.6 shows the maximum bit rates in asynchronous mode when the baud rate generator is being used. Tables 13.7 and 13.8 list the maximum rates for external clock input. Table 13.6 Maximum Bit Rates for Various Frequencies with Baud Rate Generator (Asynchronous Mode)
Settings P (MHz) 2 2.097152 2.4576 3 3.6864 4 4.9152 8 9.8304 12 14.7456 16 19.6608 20 24 24.576 28.7 30 Maximum Bit Rate (Bit/s) 62500 65536 76800 93750 115200 125000 153600 250000 307200 375000 460800 500000 614400 625000 750000 768000 896875 937500 n 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 N 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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Table 13.7 Maximum Bit Rates during External Clock Input (Asynchronous Mode)
P (MHz) 2 2.097152 2.4576 3 3.6864 4 4.9152 8 9.8304 12 14.7456 16 19.6608 20 24 24.576 28.7 30 External Input Clock (MHz) 0.5000 0.5243 0.6144 0.7500 0.9216 1.0000 1.2288 2.0000 2.4576 3.0000 3.6864 4.0000 4.9152 5.0000 6.0000 6.1440 7.1750 7.5000 Maximum Bit Rate (Bit/s) 31250 32768 38400 46875 57600 62500 76800 125000 153600 187500 230400 250000 307200 312500 375000 384000 448436 468750
Table 13.8 Maximum Bit Rates during External Clock Input (Synchronous Mode)
P (MHz) 8 16 24 28.7 30 External Input Clock (MHz) 1.3333 2.6667 4.0000 4.7833 5.0000 Maximum Bit Rate (Bit/s) 1333333.3 2666666.7 4000000.0 4783333.3 5000000.0
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13.3
Operation
1 3 . 3 . 1 Overview For serial communication, the SCI has an asynchronous mode in which characters are synchronized individually, and a synchronous mode in which communication is synchronized with clock pulses. Asynchronous/synchronous mode and the transmission format are selected in the serial mode register (SCSMR), as shown in table 13.9. The SCI clock source is selected by the combination of the C/A bit in the serial mode register (SCSMR) and the CKE1 and CKE0 bits in the serial control register (SCSCR), as shown in table 13.10. Asynchronous Mode: * Data length is selectable: seven or eight bits. * Parity and multiprocessor bits are selectable, as is the stop bit length (one or two bits). The combination of the preceding selections constitutes the communication format and character length. * In receiving, it is possible to detect framing errors (FER), parity errors (PER), overrun errors (ORER) and breaks. * An internal or external clock can be selected as the SCI clock source. When an internal clock is selected, the SCI operates using the on-chip baud rate generator, and can output a serial clock signal with a frequency matching the bit rate. When an external clock is selected, the external clock input must have a frequency 16 times the bit rate. (The on-chip baud rate generator is not used.) Synchronous Mode: * The transmission/reception format has a fixed eight-bit data length. * In receiving, it is possible to detect overrun errors (ORER). * An internal or external clock can be selected as the SCI clock source. When an internal clock is selected, the SCI operates using the on-chip baud rate generator, and outputs a serial clock to external devices. When an external clock is selected, the SCI operates on the input serial clock. The on-chip baud rate generator is not used.
358
Table 13.9 Serial Mode Register Settings and SCI Communication Formats
SCSMR Settings Mode Asynchronous SCI Communication Format Multipro- Stop Bit cessor Length Bit 1 bit 2 bits Used 1 bit 2 bits 7-bit Not used 1 bit 2 bits Used 1 bit 2 bits 8-bit Not used Used 1 bit 2 bits 7-bit 1 bit 2 bits 8-bit Not used None
Bit 7 Bit 6 Bit 5 Bit 2 Bit 3 D a t a Parity C/A CHR P E MP S T O P Length B i t 0 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 8-bit
Not used Not used
Asynchronous (multiprocessor format)
0
* *
1
0 1 0 1
1
* *
Synchronous
1
*
*
*
*
Note: Asterisks (*) indicate don't-care bits.
Table 13.10
SCSMR and SCSCR Settings and SCI Clock Source Selection
SCSMR Bit 7 C/A SCSCR Settings Bit 1 Bit 0 CKE1 CKE0 0 0 1 1 0 1 External SCI Transmit/Receive Clock Clock S our ce Internal SCK Pin Function SCI does not use the SCK pin Outputs a clock with frequency matching the bit rate Inputs a clock with frequency 16 times the bit rate Outputs the serial clock
Mode
Asynchronous 0 mode
Synchronous mode
1
0
0 1
Internal
1
0 1
External
Inputs the serial clock
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1 3 . 3 . 2 Operation in Asynchronous Mode In asynchronous mode, each transmitted or received character begins with a start bit and ends with a stop bit. Serial communication is synchronized one character at a time. The transmitting and receiving sections of the SCI are independent, so full-duplex communication is possible. The transmitter and receiver are both double-buffered, so data can be written and read while transmitting and receiving are in progress, enabling continuous transmitting and receiving. Figure 13.2 shows the general format of asynchronous serial communication. In asynchronous serial communication, the communication line is normally held in the mark (high) state. The SCI monitors the line and starts serial communication when the line goes to the space (low) state, indicating a start bit. One serial character consists of a start bit (low), data (LSB first), parity bit (high or low), and stop bit (high), in that order. When receiving in asynchronous mode, the SCI synchronizes on the falling edge of the start bit. The SCI samples each data bit on the eighth pulse of a clock with a frequency 16 times the bit rate. Receive data is latched at the center of each bit.
Idle (mark) state 1 0/1 Parity bit Transmit/receive data 1 bit 7 or 8 bits 1 or no bit 1 or 2 bits 1 1 Stop bit
1 Serial data 0 Start bit
(LSB) D0 D1 D2 D3 D4 D5 D6
(MSB) D7
One unit of communication data (character or frame)
Figure 13.2
Data Format in Asynchronous Communication (Example: 8-Bit Data with Parity and 2 Stop Bits)
Transmit/Receive Formats: Table 13.11 lists the 12 communication formats that can be selected in asynchronous mode. The format is selected by settings in the serial mode register (SCSMR).
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Table 13.11
Serial Communication Formats (Asynchronous Mode)
Serial Transmit/Receive Format and Frame Length 1 S S S S S S S S S S S S 2 3 4 5 6 7 8 9 10 STOP STOP STOP P P STOP STOP STOP P P STOP STOP STOP MPB MPB MPB MPB STOP STOP STOP STOP STOP STOP STOP STOP STOP 11 12
SCSMR Bits CHR P E M P S T O P 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 -- -- -- -- 0 0 0 0 0 0 0 0 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1
8-bit data 8-bit data 8-bit data 8-bit data 7-bit data 7-bit data 7-bit data 7-bit data 8-bit data 8-bit data 7-bit data 7-bit data
Legend --: S: STOP: P: MPB:
Don't care bits Start bit Stop bit Parity bit Multiprocessor bit
Clock: An internal clock generated by the on-chip baud rate generator or an external clock input from the SCK pin can be selected as the SCI transmit/receive clock. The clock source is selected by the C/A bit in the serial mode register (SCSMR) and bits CKE1 and CKE0 in the serial control register (SCSCR) (table 13.10). When an external clock is input at the SCK pin, it must have a frequency equal to 16 times the desired bit rate. When the SCI operates on an internal clock, it can output a clock signal at the SCK pin. The frequency of this output clock is equal to the bit rate. The phase is aligned as shown in figure 13.3 so that the rising edge of the clock occurs at the center of each transmit data bit.
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0
D0
D1
D2
D3
D4
D5
D6
D7
0/1
1
1
1 frame
Figure 13.3
Output Clock and Serial Data Timing (Asynchronous Mode)
Transmitting and Receiving Data (SCI Initialization (Asynchronous Mode)): Before transmitting or receiving, clear the TE and RE bits to 0 in the serial control register (SCSCR), then initialize the SCI as follows. When changing the operation mode or communication format, always clear the TE and RE bits to 0 before following the procedure given below. Clearing TE to 0 sets TDRE to 1 and initializes the transmit shift register (SCTSR). Clearing RE to 0, however, does not initialize the RDRF, PER, FER, and ORER flags or receive data register (SCRDR), which retain their previous contents. When an external clock is used, the clock should not be stopped during initialization or subsequent operation. SCI operation becomes unreliable if the clock is stopped. Figure 13.4 is a sample flowchart for initializing the SCI. The procedure for initializing the SCI is: 1. Select the clock source in the serial control register (SCSCR). Leave RIE, TIE, TEIE, MPIE, TE, and RE cleared to 0. If clock output is selected in asynchronous mode, clock output starts immediately after the setting is made in SCSCR. 2. Select the communication format in the serial mode register (SCSMR). 3. Write the value corresponding to the bit rate in the bit rate register (SCBRR) unless an external clock is used. 4. Wait for at least the interval required to transmit or receive one bit, then set TE or RE in the serial control register (SCSCR) to 1. Also set RIE, TIE, TEIE, and MPIE as necessary. Setting TE or RE enables the SCI to use the TxD or RxD pin. The initial states are the mark transmit state, and the idle receive state (waiting for a start bit).
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Initialize Clear TE and RE bits in SCSCR to 0 Set CKE1 and CKE0 bits in SCSCR (TE and RE bits are 0) Select transmit/receive format in SCSMR Set value to SCBRR Wait Has a 1-bit interval elapsed? Yes Set TE and RE bits in SCSCR to 1 and set RIE, TEIE, and MPIE bits (4) No
(1)
(2)
(3)
End
Note:
Circled numbers refer to the preceding procedure.
Figure 13.4
Sample Flowchart for SCI Initialization
Transmitting Serial Data (Asynchronous Mode): Figure 13.5 shows a sample flowchart for transmitting serial data. The procedure for transmitting serial data is: 1. SCI status check and transmit data write: Read the serial status register (SCSSR), check that the TDRE bit is 1, then write transmit data in the transmit data register (SCTDR) and clear TDRE to0. 2. To continue transmitting serial data: Read the TDRE bit to check whether it is safe to write (if it reads 1); if so, write data in SCTDR, then clear TDRE to 0. 3. To output a break at the end of serial transmission: Clear the SPB0DT bit in the SCSPTR, set the SPB0IO bit to 1 and then clear the TE bit to 0 in SCSCR.
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Start transmission
Read TDRE bit in SCSSR
(1) No
TDRE = 1? Yes Write transmit data to TDR and clear TDRE bit in SCSSR to 0 (2) All data transmitted? Yes Read TEND bit in SCSSR
No
TEND = 1? Yes Break output? (3) Yes Clear SPB0DT to 0 and set SPB0IO to 1 Clear TE bit in SCSCR to 0
No
No
End transmission
Note:
Circled numbers refer to the preceding procedure.
Figure 13.5
Sample Flowchart for Transmitting Serial Data
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In transmitting serial data, the SCI operates as follows: 1. The SCI monitors the TDRE bit in SCSSR. When TDRE is cleared to 0, the SCI recognizes that the transmit data register (SCTDR) contains new data, and loads this data from SCTDR into the transmit shift register (SCTSR). 2. After loading the data from SCTDR into SCTSR, the SCI sets the TDRE bit to 1 and starts transmitting. If the transmit-data-empty interrupt enable bit (TIE) is set to 1 in SCSCR, the SCI requests a transmit-data-empty interrupt (TXI) at this time. Serial transmit data is transmitted in the following order from the TxD pin: a. Start bit: One 0 bit is output. b. Transmit data: Seven or eight bits of data are output, LSB first. c. Parity bit or multiprocessor bit: One parity bit (even or odd parity) or one multiprocessor bit is output. Formats in which neither a parity bit nor a multiprocessor bit is output can also be selected. d. Stop bit: One or two 1 bits (stop bits) are output. e. Marking: Output of 1 bits continues until the start bit of the next transmit data. 3. The SCI checks the TDRE bit when it outputs the stop bit. If TDRE is 0, the SCI loads new data from SCTDR into SCTSR, outputs the stop bit, then begins serial transmission of the next frame. If TDRE is 1, the SCI sets the TEND bit to 1 in SCSSR, outputs the stop bit, then continues output of 1 bits (marking). If the transmit-end interrupt enable bit (TEIE) in SCSCR is set to 1, a transmit-end interrupt (TEI) is requested.
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Figure 13.6 shows an example of SCI transmit operation in asynchronous mode.
Start bit 0 D0 D1 Parity Stop Start bit bit bit D7 0/1 1 0 D0 D1 Parity Stop bit bit D7 0/1 1
1 Serial data
Data
Data
1 Idle (mark) state
TDRE
TEND TXI interrupt request TXI interrupt TXI interrupt handler writes request data to SCTDR and clears TDRE bit to 0 1 frame TEI interrupt request
Figure 13.6
SCI Transmit Operation in Asynchronous Mode (Example: 8-Bit Data with Parity and One Stop Bit)
Receiving Serial Data (Asynchronous Mode): Figure 13.7 shows a sample flowchart for receiving serial data. The procedure for receiving serial data after enabling the SCI for reception is: 1. Receive error handling and break detection: If a receive error occurs, read the ORER, PER and FER bits in SCSSR to identify the error. After executing the necessary error handling, clear ORER, PER and FER all to 0. Receiving cannot resume if ORER, PER or FER remain set to 1. When a framing error occurs, the RxD pin can be read to detect the break state. 2. SCI status check and receive-data read: Read the serial status register (SCSSR), check that RDRF is set to 1, then read receive data from the receive data register (SCRDR) and clear RDRF to 0. The RXI interrupt can also be used to determine if the RDRF bit has changed from 0 to 1. 3. To continue receiving serial data: Read the RDRF and SCRDR bits and clear RDRF to 0 before the stop bit of the current frame is received.
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Start reception
Read ORER, PER, and FER bits in SCSSR Yes (1) (2) Error handling
PER, FER, ORER = 1? No Read the RDRF bit in SCSSR No
RDRF = 1? Yes
Read reception data of SCRDR (3) and clear RDRF bit in SCSSR to 0
No
All data received? Yes Clear the RE bit in SCSCR to 0
End reception
Note:
Circled numbers refer to the preceding procedure.
Figure 13.7
Sample Flowchart for Receiving Serial Data
367
Error handling
No
ORER = 1? Yes Overrun error handling
No
FER = 1? Yes Break? No Framing error handling Clear RE bit in SCSCR to 0 Yes
No
PER = 1? Yes Parity error handling
Clear ORER, PER, and FER bits in SCSSR to 0 End
Figure 13.7
Sample Flowchart for Receiving Serial Data (cont)
368
In receiving, the SCI operates as follows: 1. The SCI monitors the communication line. When it detects a start bit (0), the SCI synchronizes internally and starts receiving. 2. Receive data is shifted into SCRSR in order from the LSB to the MSB. 3. The parity bit and stop bit are received. After receiving these bits, the SCI makes the following checks: a. Parity check: The number of 1s in the receive data must match the even or odd parity setting of the O/E bit in SCSMR. b. Stop bit check: The stop bit value must be 1. If there are two stop bits, only the first stop bit is checked. c. Status check: RDRF must be 0 so that receive data can be loaded from SCRSR into SCRDR. If these checks all pass, the SCI sets RDRF to 1 and stores the received data in SCRDR. If one of the checks fails (receive error), the SCI operates as indicated in table 13.12. Note: When a receive error flag is set, further receiving is disabled. The RDRF bit is not set to 1. Be sure to clear the error flags. 4. After setting RDRF to 1, if the receive-data-full interrupt enable bit (RIE) is set to 1 in SCSCR, the SCI requests a receive-data-full interrupt (RXI). If one of the error flags (ORER, PER, or FER) is set to 1 and the receive-data-full interrupt enable bit (RIE) in SCSCR is also set to 1, the SCI requests a receive-error interrupt (ERI). Table 13.12 Receive Error Conditions and SCI Operation
Data Transfer Receive data not loaded from SCRSR into SCRDR Receive data loaded from SCRSR into SCRDR
Receive Error Abbreviation Condition Overrun error Framing error Parity error ORER FER PER Receiving of next data ends while RDRF is still set to 1 in SCSSR Stop bit is 0
Parity of receive data differs from Receive data loaded from even/odd parity setting in SCSMR SCRSR into SCRDR
Figure 13.8 shows an example of SCI receive operation in asynchronous mode.
369
1 Serial data
Start bit 0 D0 D1
Data D7
Parity Stop Start bit bit bit 0/1 1 0 D0 D1
Data D7
Parity Stop bit bit 0/1 1
1 Idle (mark) state
RDRF RXI interrupt request 1 frame RXI interrupt handler reads data and clears RDRF bit to 0 ERI interrupt request generated by framing error
FER
Figure 13.8
SCI Receive Operation (Example: 8-bit Data with Parity and One Stop Bit)
1 3 . 3 . 3 Multiprocessor Communication The multiprocessor communication function enables several processors to share a single serial communication line. The processors communicate in asynchronous mode using a format with an additional multiprocessor bit (multiprocessor format). In multiprocessor communication, each receiving processor is addressed by a unique ID. A serial communication cycle consists of an ID-sending cycle that identifies the receiving processor, and a data-sending cycle. The multiprocessor bit distinguishes ID-sending cycles from data-sending cycles. The transmitting processor starts by sending the ID of the receiving processor with which it wants to communicate as data with the multiprocessor bit set to 1. Next the transmitting processor sends transmit data with the multiprocessor bit cleared to 0. Receiving processors skip incoming data until they receive data with the multiprocessor bit set to 1. When they receive data with the multiprocessor bit set to 1, receiving processors compare the data with their IDs. The receiving processor with a matching ID continues to receive further incoming data. Processors with IDs not matching the received data skip further incoming data until they again receive data with the multiprocessor bit set to 1. Multiple processors can send and receive data in this way.
370
Figure 13.9 shows an example of communication among processors using the multiprocessor format.
Transmitting station Serial communication circuit
Receiving station A (ID = 01)
Receiving station B (ID = 02)
Receiving station C (ID = 03)
Receiving station D (ID = 04)
Serial data
H'01 (MPB = 1) ID transmit cycle = specifies receiving station
H'AA (MPB = 0) Data transmit cycle = data transmission to receiving station specified by ID
MPB: Multiprocessor bit
Figure 13.9 Communication Among Processors Using Multiprocessor Format (Example:Sending Data H'AA to Receiving Processor A) Communication Formats: Four formats are available. Parity-bit settings are ignored when the multiprocessor format is selected. For details see table 13.11. Clock: See the description in the asynchronous mode section. Transmitting Multiprocessor Serial Data: Figure 13.10 shows a sample flowchart for transmitting multiprocessor serial data. The procedure for transmitting multiprocessor serial data is: 1. SCI status check and transmit data write: Read the serial status register (SCSSR), check that the TDRE bit is 1, then write transmit data in the transmit data register (SCTDR). Also set MPBT (multiprocessor bit transfer) to 0 or 1 in SCSSR. Finally, clear TDRE to 0. 2. To continue transmitting serial data: Read the TDRE bit to check whether it is safe to write (if it reads 1); if so, write data in SCTDR, then clear TDRE to 0. 3. To output a break at the end of serial transmission: Set the SPB0DT bit in the SCSPTR register to 0, set SPB0IO to 1, then clear TE to 0 in SCSCR.
371
Start transmission Read TDRE bit in SCSSR
(1) No
TDRE = 1? Yes Write transmission data to TDR and set MPBT bit in SCSSR Clear TDRE bit to 0
Transmission ended? Yes Read TEND bit in SCSSR
No
(2)
TEND = 1? Yes Break output? Yes (3) Clear SPB0DT to 0, set SPB0IO to 1 Clear TE bit SCSCR to 0 End transmission
No
No
Note:
Circled numbers refer to the preceding procedure.
Figure 13.10
Sample Flowchart for Transmitting Multiprocessor Serial Data
372
In transmitting serial data, the SCI operates as follows: 1. The SCI monitors the TDRE bit in SCSSR. When TDRE is cleared to 0 the SCI recognizes that the transmit data register (SCTDR) contains new data, and loads this data from SCTDR into the transmit shift register (SCTSR). 2. After loading the data from SCTDR into SCTSR, the SCI sets the TDRE bit to 1 and starts transmitting. If the transmit-data-empty interrupt enable bit (TIE) in the SCSCR is set to 1, the SCI requests a transmit-data-empty interrupt (TXI) at this time. Serial transmit data is transmitted in the following order from the TxD pin: a. Start bit: One 0 bit is output. b. Transmit data: Seven or eight bits are output, LSB first. c. Multiprocessor bit: One multiprocessor bit (MPBT value) is output. d. Stop bit: One or two 1 bits (stop bits) are output. e. Marking: Output of 1 bits continues until the start bit of the next transmit data. 3. The SCI checks the TDRE bit when it outputs the stop bit. If TDRE is 0, the SCI loads data from SCTDR into SCTSR, outputs the stop bit, then begins serial transmission of the next frame. If TDRE is 1, the SCI sets the TEND bit in SCSSR to 1, outputs the stop bit, then continues output of 1 bits in the mark state. If the transmit-end interrupt enable bit (TEIE) in the SCSCR is set to 1, a transmit-end interrupt (TEI) is requested at this time.
373
Figure 13.11 shows SCI transmission with the multiprocessor format.
Multiprocessor bit Stop Start Data bit bit D0 D1 D7 0/1 1 0 D0 D1 Multiprocessor bit Stop Data bit D7 0/1 1
1 Serial data
Start bit 0
1 Idle (mark) state
TDRE
TEND
TXI interrupt request
TXI interrupt handler writes data to TDR and clears TDRE bit to 0 1 frame
TXI interrupt request
TEI interrupt request
Figure 13.11
SCI Multiprocessor Transmit Operation (Example: 8-Bit Data with Multiprocessor Bit and One Stop Bit)
Receiving Multiprocessor Serial Data: Figure 13.12 shows a sample flowchart for receiving multiprocessor serial data. The procedure for receiving multiprocessor serial data is: 1. ID receive cycle: Set the MPIE bit in the serial control register (SCSCR) to 1. 2. SCI status check and compare to ID reception: Read the serial status register (SCSSR), check that RDRF is set to 1, then read data from the receive data register (SCRDR) and compare with the processor's own ID. If the ID does not match the receive data, set MPIE to 1 again and clear RDRF to 0. If the ID matches the receive data, clear RDRF to 0. 3. SCI status check and data receiving: Read SCSSR, check that RDRF is set to 1, then read data from the receive data register (SCRDR). 4. Receive error handling and break detection: If a receive error occurs, read the ORER and FER bits in SCSSR to identify the error. After executing the necessary error handling, clear both ORER and FER to 0. Receiving cannot resume if ORER or FER remain set to 1. When a framing error occurs, the RxD pin can be read to detect the break state.
374
Start reception Set MPIE bit in SCSCR to 1 Read ORER and FER bits in SCSSR FER = 1 or ORER = 1? No Read RDRF bit in SCSSR No Yes (1)
(2)
RDRF = 1? Yes Read receive data in SCRDR
No
Is ID the station's ID? Yes Read ORER and FER bits in SSCSR FER = 1 or ORER = 1? No Read RDRF bit in SCSSR RDRF = 1? Yes Read receive data in SCRDR (3) No Yes
No
All data received? Yes Clear RE bit in SCSCR to 0 End reception
(4) Error handling
Figure 13.12
Sample Flowchart for Receiving Multiprocessor Serial Data
375
Error handling
No
ORER = 1? Yes Overrun error handling
No
FER = 1? Yes Break? No Framing error handling Clear RE bit in SCSCR to 0 Yes
Clear ORER and FER bits in SCSSR to 0
End
Figure 13.12
Sample Flowchart for Receiving Multiprocessor Serial Data (cont)
376
Figures 13.13 (a) and (b) show examples of SCI receive operation using a multiprocessor format.
Start bit 0 Data (ID1) D0 D1 D7 Stop Start Data bit (data 1) MPB bit 1 1 0 D0 D1 D7 Stop MPB bit 0 1
1 Serial data MPIE
1 Idle (mark) state
RDRF
RDR value RXI interrupt request (multiprocessor interrupt), MPIE = 0 RXI interrupt handler reads RDR data and clears RDRF bit to 0
ID1
ID is not station's No RXI interrupt, ID, so MPIE bit is RDR state set to 1 again is maintained
Figure 13.13 (a) Example of SCI Receive Operation: Own ID Does Not Match Data (8-Bit Data with Multiprocessor Bit and One Stop Bit)
Start bit 0 Data (ID2) D0 D1 D7 Data Stop Start bit bit (Data 2) 1 0 D0 D1 D7 Stop MPB bit 0 1
1 Serial data MPIE
MPB 1
1 Idle (mark) state
RDRF
RDR value
ID1
ID2
Data2
RXI interrupt request (multiprocessor interrupt), MPIE = 0
RXI interrupt handler reads RDR data and clears RDRF bit to 0
ID is that of station, so reception continues unchanged and data is received by the RXI interrupt handler
MPIE bit set to 1 again
Figure 13.13 (b) Example of SCI Receive Operation: Own ID Matches Data (8-BitDatawithMultiprocessor Bit and One Stop Bit)
377
1 3 . 3 . 4 Synchronous Operation In synchronous mode, the SCI transmits and receives data in synchronization with clock pulses. This mode is suitable for high-speed serial communication. The SCI transmitter and receiver are independent, so full-duplex communication is possible while sharing the same clock. The transmitter and receiver are also double-buffered, so continuous transmitting or receiving is possible by reading or writing data while transmitting or receiving is in progress. Figure 13.14 shows the general format in synchronous serial communication.
One unit of communication data (character or frame) * Serial clock Don't care Serial data Don't care *
LSB Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6
MSB Bit 7
Note:
High except in continuous transmitting or receiving
Figure 13.14
Data Format in Synchronous Communication
In synchronous serial communication, each data bit is output on the communication line from one falling edge of the serial clock to the next. Data is guaranteed valid at the rising edge of the serial clock. In each character, the serial data bits are transmitted in order from the LSB (first) to the MSB (last). After output of the MSB, the communication line remains in the state of the MSB. In synchronous mode, the SCI transmits or receives data by synchronizing with the falling edge of the serial clock. Communication Format: The data length is fixed at eight bits. No parity bit or multiprocessor bit can be added. Clock: An internal clock generated by the on-chip baud rate generator or an external clock input from the SCK pin can be selected as the SCI transmit/receive clock. The clock source is selected by the C/A bit in the serial mode register (SCSMR) and bits CKE1 and CKE0 in the serial control register (SCSCR). See table 13.10. When the SCI operates on an internal clock, it outputs the clock signal at the SCK pin. Eight clock pulses are output per transmitted or received character. When the SCI is not transmitting or receiving, the clock signal remains in the high state. When only receiving, the SCI receives in 2378
character units, so a 16 pulse synchronization clock is output. To receive in 1-character units, select an external clock source. Transmitting and Receiving Data: SCI Initialization (synchronous mode). Before transmitting, receiving, or changing the mode or communication format, the software must clear the TE and RE bits to 0 in the serial control register (SCSCR), then initialize the SCI. Clearing TE to 0 sets TDRE to 1 and initializes the transmit shift register (SCTSR). Clearing RE to 0, however, does not initialize the RDRF, PER, FER, and ORER flags and receive data register (SCRDR), which retain their previous contents. Figure 13.15 is a sample flowchart for initializing the SCI. The procedure for initializing the SCI is: 1. Select the clock source in the serial control register (SCSCR). Leave RIE, TIE, TEIE, MPIE, TE and RE cleared to 0. 2. Select the communication format in the serial mode register (SCSMR). 3. Write the value corresponding to the bit rate in the bit rate register (SCBRR) unless an external clock is used. 4. Wait for at least the interval required to transmit or receive one bit, then set TE or RE in the serial control register (SCSCR) to 1. Also set RIE, TIE, TEIE and MPIE. Setting TE and RE allows use of the TxD and RxD pins.
379
Initialize Clear TE and RE bits in SCSCR to 0 Set RIE, TIE, TEIE, MPIE, CKE1, and CKE0 bits in SCSCR (TE and RE are 0)
(1)
Set transmit/receive format in SCSMR (2) Set value in SCBRR Wait Has a 1-bit period elapsed? Yes Set TE and RE bits in SCSCR to 1 and set RIE, TIE, TEIE, and MPIE bits (4) No
(3)
End
Figure 13.15
Sample Flowchart for SCI Initialization
380
Transmitting Serial Data (Synchronous Mode): Figure 13.16 shows a sample flowchart for transmitting serial data. The procedure for transmitting serial data is: 1. SCI status check and transmit data write: Read the serial status register (SCSSR), check that the TDRE bit is 1, then write transmit data in the transmit data register (SCTDR) and clear TDRE to0. 2. To continue transmitting serial data: Read the TDRE bit to check whether it is safe to write (if it reads 1); if so, write data in SCTDR, then clear TDRE to 0.
Start transmission
Read TDRE bit in SCSSR No
(1)
TDRE = 1? Yes
Write transmit data to SCTDR and clear TDRE bit in SCSSR to 0
All data transmitted? Yes Read TEND bit in SCSSR
No
(2)
TEND = 1? Yes Clear TE bit in SCSCR to 0 End transmission
No
Figure 13.16
Sample Flowchart for Serial Transmitting
381
In transmitting serial data, the SCI operates as follows: 1. The SCI monitors the TDRE bit in SCSSR. When TDRE is cleared to 0 the SCI recognizes that the transmit data register (SCTDR) contains new data and loads this data from SCTDR into the transmit shift register (SCTSR). 2. After loading the data from SCTDR into SCTSR, the SCI sets the TDRE bit to 1 and starts transmitting. If the transmit-data-empty interrupt enable bit (TIE) in SCSCR is set to 1, the SCI requests a transmit-data-empty interrupt (TXI) at this time. If clock output mode is selected, the SCI outputs eight synchronous clock pulses. If an external clock source is selected, the SCI outputs data in synchronization with the input clock. Data is output from the TxD pin in order from the LSB (bit 0) to the MSB (bit 7). 3. The SCI checks the TDRE bit when it outputs the MSB (bit 7). If TDRE is 0, the SCI loads data from SCTDR into SCTSR, then begins serial transmission of the next frame. If TDRE is 1, the SCI sets the TEND bit in SCSSR to 1, transmits the MSB, then holds the transmit data pin (TxD) in the MSB state. If the transmit-end interrupt enable bit (TEIE) in the SCSCR is set to 1, a transmit-end interrupt (TEI) is requested at this time. 4. After the end of serial transmission, the SCK pin is held in the high state. Figure 13.17 shows an example of SCI transmit operation.
Transfer direction
Serial clock LSB Bit 0 MSB Bit 7
Serial data
Bit 1
Bit 0
Bit 1
Bit 6
Bit 7
TDRE TEND
TXI interrupt request
TXI interrupt handler writes data to TDR and clears TDRE bit to 0 1 frame
TXI interrupt request
TEI interrupt request
Figure 13.17
Example of SCI Transmit Operation
382
Receiving Serial Data (Synchronous Mode): Figure 13.18 shows a sample flowchart for receiving serial data. When switching from asynchronous mode to synchronous mode, make sure that ORER, PER, and FER are cleared to 0. If PER or FER is set to 1, the RDRF bit will not be set and both transmitting and receiving will be disabled. The procedure for receiving serial data is: 1. Receive error handling and break detection: If a receive error occurs, read the ORER bit in SCSSR to identify the error. After executing the necessary error handling, clear ORER to 0. Transmitting/receiving cannot resume if ORER remains set to 1. 2. SCI status check and receive data read: Read the serial status register (SCSSR), check that RDRF is set to 1, then read receive data from the receive data register (SCRDR) and clear RDRF to 0. The RXI interrupt can also be used to determine if the RDRF bit has changed from 0 to 1. 3. To continue receiving serial data: Read SCRDR, and clear RDRF to 0 before the MSB (bit 7) of the current frame is received.
383
Start reception
Read ORER bit in SCSSR Yes
ORER = 1? No
(1) Read RDRF bit in SCSSR No (2) Error handling
RDRF = 1? Yes
No
ORER = 1? Yes Overrun error handling
Read receive data in SCRDR and (3) clear RDRF bit in SCSSR to 0 No
All data received? Yes Clear RE bit in SCSCR to 0 End reception
Clear ORER bit in SCSSR to 0 End
Figure 13.18
Sample Flowchart for Serial Receiving
384
In receiving, the SCI operates as follows: 1. The SCI synchronizes with serial clock input or output and initializes internally. 2. Receive data is shifted into SCRSR in order from the LSB to the MSB. After receiving the data, the SCI checks that RDRF is 0 so that receive data can be loaded from SCRSR into SCRDR. If this check is passed, the SCI sets RDRF to 1 and stores the received data in SCRDR. If the check is not passed (receive error), the SCI operates as indicated in table 13.12. This state prevents further transmission or reception. While receiving, the RDRF bit is not set to 1. Be sure to clear the error flag. 3. After setting RDRF to 1, if the receive-data-full interrupt enable bit (RIE) is set to 1 in SCSCR, the SCI requests a receive-data-full interrupt (RXI). If the ORER bit is set to 1 and the receive-data-full interrupt enable bit (RIE) in SCSCR is also set to 1, the SCI requests a receive-error interrupt (ERI). Figure 13.19 shows an example of the SCI receive operation.
Transfer direction Serial clock
Serial data RDRF ORER
Bit 7
Bit 0
Bit 7
Bit 0
Bit 1
Bit 6
Bit 7
RXI interrupt RXI interrupt handler RXI interrupt request request reads data and clears RDRF bit to 0 1 frame
ERI interrupt request generated by overrun error
Figure 13.19
Example of SCI Receive Operation
385
Transmitting and Receiving Serial Data Simultaneously (Synchronous Mode): Figure 13.20 shows a sample flowchart for transmitting and receiving serial data simultaneously. The procedure for setting the SCI to transmit and receive serial data simultaneously is: 1. SCI status check and transmit data write: Read the serial status register (SCSSR), check that the TDRE bit is 1, then write transmit data in the transmit data register (SCTDR) and clear TDRE to 0. The TXI interrupt can also be used to determine if the TDRE bit has changed from 0 to 1. 2. Receive error handling: If a receive error occurs, read the ORER bit in SCSSR to identify the error. After executing the necessary error handling, clear ORER to 0. Transmitting/receiving cannot resume if ORER remains set to 1. 3. SCI status check and receive data read: Read the serial status register (SCSSR), check that RDRF is set to 1, then read receive data from the receive data register (SCRDR) and clear RDRF to 0. The RXI interrupt can also be used to determine if the RDRF bit has changed from 0 to 1. 4. To continue transmitting and receiving serial data: Read the RDRF bit and SCRDR, and clear RDRF to 0 before the MSB (bit 7) of the current frame is received. Also read the TDRE bit to check whether it is safe to write (if it reads 1); if so, write data in SCTDR, then clear TDRE to 0 before the MSB (bit 7) of the current frame is transmitted.
386
Start transmission/reception
Read TDRE bit in SCSSR No
(1)
TDRE = 1? Yes Write transmission data to SCTDR and clear TDRE bit in SCSSR to 0 Read ORER bit in SCSSR Yes (2) Error handling
ORER = 1? No
Read RDRF bit in SCSSR No
(3)
RDRF = 1? Yes Read receive data of SCRDR and clear RDRF bit in SCSSR to 0 (4)
No
All data transmitted/received? Yes Clear TE and RE bits in SCSCR to 0 End transmission/reception
Note:
When switching from transmitting or receiving to simultaneous transmitting and receiving, simultaneously clear TE and RE to 0, then simultaneously set TE and RE to 1.
Figure 13.20
Sample Flowchart for Serial Transmitting
387
13.4
SCI Interrupt Sources
The SCI has four interrupt sources in each channel: transmit-end (TEI), receive-error (ERI), receivedata-full (RXI), and transmit-data-empty (TXI). Table 13.13 lists the interrupt sources and indicates their priority. These interrupts can be enabled and disabled by the TIE, RIE, and TEIE bits in the serial control register (SCSCR). Each interrupt request is sent separately to the interrupt controller. TXI is requested when the TDRE bit in SCSSR is set to 1. TDRE is automatically cleared to 0 when data is written in the transmit data register (SCTDR). RXI is requested when the RDRF bit in SCSSR is set to 1. RDRF is automatically cleared to 0 when the receive data register (SCRDR) is read. ERI is requested when the ORER, PER, or FER bit in SCSSR is set to 1. TEI is requested when the TEND bit in SCSSR is set to 1. Where the TXI interrupt indicates that transmit data writing is enabled, the TEI interrupt indicates that the transmit operation is complete. Table 13.13 SCI Interrupt Sources
Description Receive error (ORER, PER, or FER) Receive data full (RDRF) Transmit data empty (TDRE) Transmit end (TEND) Low Priority When Reset Is Cleared High
Interrupt Source ERI RXI TXI TEI
See section 4, Exception Handling, for information on the priority order and relationship to nonSCI interrupts.
13.5
Usage Notes
Note the following points when using the SCI. SCTDR Write and TDRE Flags: The TDRE bit in the serial status register (SCSSR) is a status flag indicating loading of transmit data from SCTDR into SCTSR. The SCI sets TDRE to 1 when it transfers data from SCTDR to SCTSR. Data can be written to SCTDR regardless of the TDRE bit status. If new data is written in SCTDR when TDRE is 0, however, the old data stored in SCTDR will be lost because the data has not yet been transferred to SCTSR. Before writing transmit data to SCTDR, be sure to check that TDRE is set to 1. Simultaneous Multiple Receive Errors: Table 13.14 shows the state of the SCSSR status flags when multiple receive errors occur simultaneously. When an overrun error occurs, the SCRSR contents cannot be transferred to SCRDR, so receive data is lost.
388
Table 13.14
SCSSR Status Flags and Transfer of Receive Data
Receive Data Transfer RDRF O R E R F E R P E R SCRSR SCRDR 1 0 0 1 1 0 1 0 0 1 1 0 1 0 1 0 1 0 1 1 0 0 1 0 1 1 1 X O O X X O X SCSSR Status Flags
Receive Error Status Overrun error Framing error Parity error Overrun error + framing error Overrun error + parity error Framing error + parity error
Overrun error + framing error + parity error 1
O: Receive data is transferred from SCRSR to SCRDR. X: Receive data is not transferred from SCRSR to SCRDR.
Break Detection and Processing: Break signals can be detected by reading the RxD pin directly when a framing error (FER) is detected. In the break state, the input from the RxD pin consists of all 0s, so FER is set and the parity error flag (PER) may also be set. In the break state, the SCI receiver continues to operate, so if the FER bit is cleared to 0, it will be set to 1 again. Sending a Break Signal: The input/output direction and level of the TxD pin can be set using the SPB0IO and SPB0DT bits in the serial port register (SCSPTR). Use these bits to send breaks. After initialization, the pin will not function as a TxD pin until the TE bit is set to 1 (enabling transmission). Through this period, the value of the SPB0DT bit substitutes for the mark state. For this reason, the SPB0IO and SPB0DT bits are initially set to 1 (output, high level). To send a break during serial transmission, clear the SPB0DT bit to 0 (low level), then clear TE to 0 (halting transmission). When the TE bit is cleared to 0, the transmitter is initialized without regard to the current transmission status, and 0 is output from the TxD pin. Receive Error Flags and Transmitter Operation (Synchronous Mode Only): W h e n a receive error flag (ORER, PER, or FER) is set to 1, the SCI will not start transmitting even if TDRE is set to 1. Be sure to clear the receive error flags to 0 before starting to transmit. Note that clearing RE to 0 does not clear the receive error flags. Receive Data Sampling Timing and Receive Margin in Asynchronous Mode: I n asynchronous mode, the SCI operates on a base clock of 16 times the transfer rate frequency. In receiving, the SCI synchronizes internally with the falling edge of the start bit, which it samples on the base clock. Receive data is latched on the rising edge of the eighth base clock pulse (figure 13.21).
389
16 clock cycles 8 clock cycles
0 1 2 3 4 5 6 7 8 9 10111213 1415 0 1 2 3 4 5 6 7 8 9 10111213 1415 0 1 2 3 4 5
Base clock -7.5 clock cycles Receive data (RxD) Synchronization sampling timing Data sampling timing Start bit +7.5 clock cycles D0 D1
Figure 13.21
Receive Data Sampling Timing in Asynchronous Mode
The receive margin in the asynchronous mode can therefore be expressed as shown in equation 1. Equation 1:
M = 0.5 - 1 D - 0.5 (1 + F) x 100% - (L - 0.5)F - 2N N
Where: M = Receive margin (%) N = Ratio of clock frequency to bit rate (N = 16) D = Clock duty cycle (D = 0-1.0) L = Frame length (L = 9-12) F = Absolute deviation of clock frequency From equation (1), if F = 0 and D = 0.5, the receive margin is 46.875%, as shown in equation 2. Equation 2:
M = (0.5 - 1/(2 x 16)) x 100% = 46.875%
This is a theoretical value. A reasonable margin to allow in system designs is 20-30%.
390
Cautions on Use of Clock Synchronous External Clock Mode: * Set TE = RE = 1 only when the external clock SCK is 1. * Do not set TE = RE = 1 until at least four peripheral operating clock cycles after the external clock SCK has changed from 0 to 1. * When receiving, RDRF is 1 when RE is set to zero 2.5-3.5 peripheral operating clock cycles after the rising edge of the RxD D7 bit SCK input, but it cannot be copied to SCRDR. Caution on Use of Clock Synchronous Internal Clock Mode: When receiving, RDRF is 1 when RE is set to zero 1.5 peripheral operating clock cycles after the rising edge of the RxD D7 bit SCK output, but it cannot be copied to SCRDR.
391
392
Section 14 Smart Card Interface
14.1 Overview
As an added serial communications interface function, the SCI supports an IC card (smart card) interface that conforms to the ISO/IEC standard 7816-3 for identification of cards. Register settings are used to switch between the ordinary serial communication interface and the smart card interface. 14.1.1 Features
The smart card interface has the following features: * Asynchronous mode Data length: Eight bits Parity bit generation and check Receive mode error signal detection (parity error) Transmit mode error signal detection and automatic re-transmission of data Supports both direct convention and inverse convention * Bit rate can be selected using on-chip baud rate generator. * Three types of interrupts: Transmit-data-empty, receive-data-full, and communication-error interrupts are requested independently.
393
14.1.2
Block Diagram
Figure 14.1 shows a block diagram of the smart card interface.
Bus interface
Module data bus
Internal data bus
SCRDR
SCTDR
RxD
SCRSR
SCTSR
TxD
SCSCMR SCSSR SCSCR SCSMR SCSPTR Transmit/ receive control
SCBRR
Baud rate generator
P P/4 P/16 P/64
Parity generation Parity check
Clock External clock TXI RXI ERI
SCK
SCI SCSCMR: SCRSR: SCRDR: SCTSR: SCTDR: SCSMR: SCSCR: SCSSR: SCBRR: SCSPTR: Smart card mode register Receive data register Receive data register Transmit shift register Transmit data register Serial mode register Serial control register Serial status register Bit rate register Serial port register
Figure 14.1
Smart Card Interface Block Diagram
394
14.1.3
Pin Configuration
Table 14.1 summarizes the smart card interface pins. Table 14.1 SCI Pins
Pin Name Serial clock pin Receive data pin Transmit data pin AbbreviationInput/Output Function SCK RxD TxD Output Input Output Clock output Receive data input Transmit data output
14.1.4
Register Configuration
Table 14.2 summarizes the registers used by the smart card interface. The SCSMR, SCBRR, SCSCR, SCTDR, and SCRDR registers are the same as in the ordinary SCI function. They are described in section 13, Serial Communication Interface. Table 14.2 Registers
Name Serial mode register Bit rate register Serial control register Transmit data register Serial status register Receive data register AbbreviationR/W SCSMR SCBRR SCSCR SCTDR SCSSR SCRDR R/W R/W R/W R/W
1
Initial Value* 3 H'00 H'FF H'00 H'FF
Address H'FFFFFE80 H'FFFFFE82 H'FFFFFE84 H'FFFFFE86 H'FFFFFE88 H'FFFFFE8A H'FFFFFE8C
Access Size 8 8 8 8 8 8 8
R/(W)* H'84 R R/W H'00 *
2
Smart card mode register SCSCMR
Notes: 1. Only 0 can be written, to clear the flags. 2. Bits 0, 2, and 3 are cleared. The value of the other bits is undefined. 3. Initialized by a power-on or manual reset.
14.2
Register Descriptions
This section describes the registers added for the smart card interface and the bits whose functions are changed.
395
14.2.1
Smart Card Mode Register (SCSCMR)
The smart card mode register (SCSCMR) is an 8-bit read/write register that selects smart card interface functions. SCSMR bits 0, 2, and 3 are initialized to 0 by a reset and in standby mode.
Bit: Bit name: Initial value: R/W: 7 -- -- R 6 -- -- R 5 -- -- R 4 -- -- R 3 SDIR 0 R/W 2 SINV 0 R/W 1 -- -- R 0 SMIF 0 R/W
Bits 7 to 4 and 1--Reserved: An undefined value will be returned if these bits are read. Bit 3--Smart Card Data Transfer Direction (SDIR): Selects the serial/parallel conversion format.
Bit 3: SDIR 0 Description Contents of SCTDR are transferred LSB first, receive data is stored in SCRDR LSB first. (Initial value) Contents of SCTDR are transferred MSB first, receive data is stored in SCRDR MSB first.
1
Bit 2--Smart Card Data Inversion (SINV): Specifies whether to invert the logic level of the data. This function is used in combination with bit 3 for transmitting and receiving with an inverse convention card. SINV does not affect the logic level of the parity bit. See section 14.3.4, Register Settings, for information on how parity is set.
Bit 2: SINV 0 1 Description Contents of SCTDR are transferred unchanged, receive data is stored in SCRDR unchanged. (Initial value) Contents of SCTDR are inverted before transfer, receive data is inverted before storage in SCRDR.
Bit 0--Smart Card Interface Mode Select (SMIF): Enables the smart card interface function.
Bit 0 : SMIF 0 1 Description Smart card interface function disabled (Initial value) Smart card interface function enabled
396
14.2.2
Serial Status Register (SCSSR)
In the smart card interface mode, the function of SCSSR bit 4 is changed. The setting conditions for bit 2, the TEND bit, are also changed.
Bit: Bit name: Initial value: R/W: 7 TDRE 1 R/(W)* 6 RDRF 0 R/(W)* 5 4 3 PER 0 R/(W)* 2 TEND 1 R 1 MPB 0 R 0 MPBT 0 R/W
ORER FER/ERS 0 R/(W)* 0 R/(W)*
Note: Only 0 can be written, to clear the flag.
Bits 7 to 5: These bits have the same function as in the ordinary SCI. See section 13, Serial Communication Interface, for more information. Bit 4--Error Signal Status (ERS): In the smart card interface mode, bit 4 indicates the status of the error signal returned from the receiving side during transmission. The smart card interface cannot detect framing errors.
Bit 4: ERS 0 Description Receiving ended normally with no error signal. (Initial value) ERS is cleared to 0 when the chip is reset or enters standby mode, or when software reads ERS after it has been set to 1, then writes 0 in ERS. 1 An error signal indicating a parity error was transmitted from the receiving side. ERS is set to 1 if the error signal sampled is low. Note: The ERS flag maintains its status even when the TE bit in SCSCR is cleared to 0.
397
Bits 3 to 0: These bits have the same function as in the ordinary SCI. See section 13, Serial Communication Interface, for more information. The setting conditions for bit 2, the transmit end bit (TEND), are changed as follows.
Bit 2: TEND 0 Description Transmission is in progress. TEND is cleared to 0 when software reads TDRE after it has been set to 1, then writes 0 in TDRE, or when data is written in SCTDR. 1 End of transmission. (Initial value) TEND is set to 1 when: * the chip is reset or enters standby mode, * the TE bit in SCSCR is 0 and the FER/ERS bit is also 0, * the C/A bit in SCSMR is 0, and TDRE = 1 and FER/ERS = 0 (normal transmission) 2.5 etu after a one-byte serial character is transmitted, or * the C/A bit in SCSMR is 1, and TDRE = 1 and FER/ERS = 0 (normal transmission) 1.0 etu after a one-byte serial character is transmitted. Note: etu is an abbreviation of elementary time unit, which is the period for the transfer of 1 bit.
14.3
14.3.1
Operation
Overview
The primary functions of the smart card interface are described below. 1. Each frame consists of 8 data bits and 1 parity bit. 2. During transmission, the card leaves a guard time of at least 2 etu (elementary time units: the period for 1 bit to transfer) from the end of the parity bit to the start of the next frame. 2. During reception, the card outputs an error signal low level for 1 etu after 10.5 etu has elapsed from the start bit if a parity error was detected. 4. During transmission, it automatically transmits the same data after allowing at least 2 etu from the time the error signal is sampled. 5. The specification complies with ISO/ICE7816-3, but the only type of data transmission protocol supported is protocol type T = 0 : asynchronous double-character transmission protocol.
398
14.3.2
Pin Connections
Figure 14.2 shows the pin connection diagram for the smart card interface. During communication with an IC card, transmission and reception are both carried out over the same data transfer line, so connect the TxD and RxD pins on the chip. Pull up the data transfer line to the power supply VCC side with a resistor. When using the clock generated by the smart card interface on an IC card, input the SCK pin output to the IC card's CLK pin. This connection is not necessary when the internal clock is used on the IC card. Use the chip's port output as the reset signal. Apart from these pins, the power and ground pin connections are usually also required. Note: When the IC card is not connected and both RE and TE are set to 1, closed communication is possible and auto-diagnosis can be performed.
VCC
TxD Data line RxD SCK Px (port) Clock line
IO
CLK LSI Reset line RST IC card
Connected device
Figure 14.2
Pin Connection Diagram for the Smart Card Interface
399
14.3.3
Data Format
Figure 14.3 shows the data format for the smart card interface. In this mode, parity is checked every frame while receiving and error signals sent to the transmitting side whenever an error is detected so that data can be re-transmitted. During transmission, error signals are sampled and data re-transmitted whenever an error signal is detected.
With no parity error
Ds
D0
D1
D2
D3
D4
D5
D6
D7
Dp
Transmitting station output
With parity error
Ds
D0
D1
D2
D3
D4
D5
D6
D7
Dp
DE
Transmitting station output Receiving station output
Ds: D0-D7: Dp: DE:
Start bit Data bits Parity bit Error signal
Figure 14.3
Data Format for Smart Card Interface
400
The operating sequence is: 1. The data line is high impedance when not in use and is fixed high with a pull-up resistor. 2. The transmitting side starts one frame of data transmission. The data frame starts with a start bit (Ds, low level). The start bit is followed by eight data bits (D0-D7) and a parity bit (Dp). 3. On the smart card interface, the data line returns to high impedance after this. The data line is pulled high with a pull-up resistor. 4. The receiving side checks parity. When the data is received normally with no parity errors, the receiving side then waits to receive the next data. When a parity error occurs, the receiving side outputs an error signal (DE, low level) and requests re-transfer of data. The receiving station returns the signal line to high impedance after outputting the error signal for a specified period. The signal line is pulled high with a pull-up resistor. 5. The transmitting side transmits the next frame of data unless it receives an error signal. If it does receive an error signal, it returns to step 2 to re-transmit the erroneous data. 14.3.4 Register Settings
Table 14.3 shows the bit map of the registers that the smart card interface uses. Bits shown as 1 or 0 must be set to the indicated value. The settings for the other bits are described below. Table 14.3 Register Settings for the Smart Card Interface
Registe r SCSMR SCBRR SCSCR SCTDR SCSSR SCRDR SCSCMR Address H'FFFFFE80 H'FFFFFE82 H'FFFFFE84 H'FFFFFE86 H'FFFFFE88 H'FFFFFE8A H'FFFFFE8C Bit 7 C/A BRR7 TIE TDR7 TDRE RDR7 -- Bit 6 0 BRR6 RIE TDR6 RDRF RDR6 -- Bit 5 1 BRR5 TE TDR5 ORER RDR5 -- Bit 4 O/E BRR4 RE TDR4 FER/ ERS RDR4 -- Bit 3 1 BRR3 0 TDR3 PER RDR3 SDIR Bit 2 0 BRR2 0 TDR2 TEND RDR2 SINV Bit 1 CKS1 BRR1 CKE1 TDR1 0 RDR1 -- Bit 0 CKS0 BRR0 CKE0 TDR0 0 RDR0 SMIF
Note: Dashes indicate unused bits.
401
1. Setting the serial mode register (SCSMR): Set the O/E bit to 0 when the IC card uses the direct convention or to 1 when it uses the inverse convention. Select the on-chip baud rate generator clock source with the CKS1 and CKS0 bits (see section 14.3.5, Clock). When bit 7 (C/A) of the serial mode register (SCSMR) is set to 1 (default value : 1), bit 2 (TEND) of the serial status register (SCSSR) is simply set to 1 (TXI interrupt request) 1 etu (default value : 2.5 etu) after transmission of a 1-byte character, and 11 etu continuous transmission (block transfer protocol) cannot be performed. 2. Setting the bit rate register (SCBRR): Set the bit rate. See section 14.3.5, Clock, to see how to calculate the set value. 3. Setting the serial control register (SCSCR): The TIE, RIE, TE and RE bits function as they do for the ordinary SCI. See section 13, Serial Communication Interface, for more information. The CKE0 bit specifies the clock output. When no clock is output, set 0; when a clock is output, set 1. 4. Setting the smart card mode register (SCSCMR): The SDIR and SINV bits are both set to 0 for IC cards that use the direct convention and both to 1 when the inverse convention is used. The SMIF bit is set to 1 for the smart card interface. Figure 14.4 shows sample waveforms for register settings of the two types of IC cards (direct convention and inverse convention) and their start characters. In the direct convention type, the logical 1 level is state Z, the logical 0 level is state A, and communication is LSB first. The start character data is H'3B. The parity bit is even (from the smart card standards), and thus a 1. In the inverse convention type, the logical 1 level is state A, the logical 0 level is state Z, and communication is MSB first. The start character data is H'3F. The parity bit is even (from the smart card standards), and thus a 0, which corresponds to state Z. Only data bits D7-D0 are inverted by the SINV bit. To invert the parity bit, set the O/E bit in SCSMR to odd parity mode. This applies to both transmission and reception.
402
(Z)
A Ds
Z D0
Z D1
A D2
Z D3
Z D4
Z D5
A D6
A D7
Z Dp
(Z)
State
a. Direct convention (SDIR, SINV, and O/E are all 0)
(Z)
A Ds
Z D7
Z D6
A D5
A D4
A D3
A D2
A D1
A D0
Z Dp
(Z)
State
b. Inverse convention (SDIR, SINV, and O/E are all 1)
Figure 14.4 14.3.5 Clock
Waveform of Start Character
Only the internal clock generated by the on-chip baud rate generator can be used as the communication clock in the smart card interface. The bit rate for the clock is set by the bit rate register (SCBRR) and the CKS1 and CKS0 bits in the serial mode register (SCSMR), and is calculated using the equation below. Table 14.5 shows sample bit rates. If clock output is then selected by setting CKE0 to 1, a clock with a frequency 372 times the bit rate is output from the SCK0 pin.
B= P 1488 x 22n-1 x (N + 1) x 106
Where: N = Value set in SCBRR (0 N 255) B = Bit rate (bit/s) P = Peripheral module operating frequency (MHz)* n = 0-3 (table 14.4)
403
Table 14.4 Relationship of n to CKS1 and CKS0
n 0 1 2 3 CKS1 0 0 1 1 CKS0 0 1 0 1
Table 14.5 Examples of Bit Rate B (Bit/s) for SCBRR Settings (n = 0)
P (MHz) N 0 1 2 7.1424 9600.0 4800.0 3200.0 10.00 13440.9 6720.4 4480.3 10.7136 13.00 14400.0 7200.0 4800.0 17473.1 8736.6 5824.4 14.2848 16.00 19200.0 9600.0 6400.0 21505.4 10752.7 7168.5 18.00 24193.5 12096.8 8064.5
Note: The bit rate is rounded to two decimal places.
Calculate the value to be set in the bit rate register (SCBRR) from the operating frequency and the bit rate. N is an integer in the range 0 N 255, specifying a smallish error.
N= P x 106 - 1 1488 x 22n-1 x B
Table 14.6 Examples of SCBRR Settings for Bit Rate B (Bit/s) (n = 0) (MHz) (9600 Bits/s)
7.1424 N 0 Error 0.00 N 1 10.00 Error 30.00 10.7136 N 1 Error 25.00 N 1 13.00 Error 8.99 14.2848 N 1 Error 0.00 N 1 16.00 Error 12.01 N 2 18.00 Error 15.99
404
Table 14.7 Maximum Bit Rates for Frequencies (Smart Card Interface Mode)
P (MHz) 7.1424 10.00 10.7136 13.00 14.2848 16.00 18.00 Maximum Bit Rate (Bit/s) 9600 13441 14400 17473 19200 21505 24194 N 0 0 0 0 0 0 0 n 0 0 0 0 0 0 0
The bit rate error is found as follows:
Error(%) = ( P x 106 - 1) x 100 1488 x 22n-1 x B x (N + 1)
Table 14.8 shows the relationship between transmit/receive clock register set values and output states on the smart card interface. Table 14.8 Register Set Values and SCK Pin
Register Value Setting 1*1 SMIF 1 C/A 0 CKE1 0 CKE0 0 Output Port SCK Pin State Determined by setting of port register SPB1IO and SPB1DT bits SCK (serial clock) output state Low output Low output state SCK (serial clock) output state High output High output state SCK (serial clock) output state
1 2*2 3*2 1 1 1 1
0 1 1 1 1
0 0 0 1 1
1 0 1 0 1
Notes: 1. The SCK output state changes as soon as the CKE0 bit is modified. The CKE1 bit should be cleared to 0. 2. The clock duty remains constant despite stopping and starting of the clock by modification of the CKE0 bit.
405
14.3.6
Data Transmission and Reception
Initialization: Initialize the SCI using the following procedure before sending or receiving data. Initialization is also required for switching from transmit mode to receive mode or from receive mode to transmit mode. Figure 14.5 shows a flowchart of the initialization process. 1. Clear TE and RE in the serial control register (SCSCR) to 0. 2. Clear error flags FER/ERS, PER, and ORER to 0 in the serial status register (SCSSR). 3. Set the C/A bit, parity bit (O/E bit), and baud rate generator select bits (CKS1 and CKS0 bits) in the serial mode register (SCSMR). At this time also clear the CHR and MP bits to 0 and set the STOP and PE bits to 1. 4. Set the SMIF, SDIR, and SINV bits in the smart card mode register (SCSCMR). When the SMIF bit is set to 1, the TxD and RxD pins both switch from ports to SCI pins and become high impedance. 5. Set the value corresponding to the bit rate in the bit rate register (SCBRR). 6. Set the clock source select bits (CKE1 and CKE0 bits) in the serial control register (SCSCR). Clear the TIE, RIE, TE, RE, MPIE, and TEIE bits to 0. When the CKE0 bit is set to 1, a clock is output from the SCK0 pin. 7. After waiting at least 1 bit, set the TIE, RIE, TE, and RE bits in SCSCR. Do not set the TE and RE bits simultaneously unless performing auto-diagnosis.
406
Initialize Clear TE and RE bits in SCSCR to 0 Clear SCSSR's FER/ERS, PER and ORER flags to 0 Set SCSCMR's O/E bit to parity and set CKS1 and CKS0 bits to the clock Set SCSCMR's SMIF, SDIR, and SINV bits Set value in SCBRR Set SCSCR's CKE1 and CKE0 bits to the clock and clear TIE, RIE, TE, RE, MPIE, and TEIE bits to 0 Wait Has a 1-bit interval elapsed? Yes Set SCSCR's TIE, RIE, TE, and RE bits (7) No (1)
(2)
(3)
(4)
(5)
(6)
End
Figure 14.5
Initialization Flowchart (Example)
407
Serial Data Transmission: The handling procedures in the smart card mode differ from ordinary SCI processing because data is retransmitted when an error signal is sampled during a data transmission. This results in the transmission processing flowchart shown in figure 14.6. 1. 2. 3. 4. Initialize the smart card interface mode as described in initialization above. Check that the FER/ERS bit in SCSSR is cleared to 0. Repeat steps 2 and 3 until the TEND flag in SCSSR is set to 1. Write the transmit data into SCTDR, clear the TDRE flag to 0 and start transmitting. The TEND flag will be cleared to 0. 5. To transmit more data, return to step 2. 6. To end transmission, clear the TE bit to 0. This processing can be interrupted. When the TIE bit is set to 1 and interrupt requests are enabled, a transmit-data-empty interrupt (TXI) will be requested when the TEND flag is set to 1 at the end of the transmission. When the RIE bit is set to 1 and interrupt requests are enabled, a communication error interrupt (ERI) will be requested when the ERS flag is set to 1 when an error occurs in transmission. See Interrupt Operation below for more information.
408
Start
Initialize
(1)
Start transmission (2) No
FER/ERS = 0? Yes
Error handling No TEND = 1? Yes Write transmit data in SCTDR and clear TDRE flag in SCSSR to 0 No All data transmitted? Yes No (5) (4) (3)
FER/ERS = 0? Yes
Error handling No TEND = 1? Yes Clear TE bit in SCSCR to 0 (6)
End transmission
Figure 14.6
Transmission Flowchart
409
Serial Data Reception: The handling procedures in the smart card mode are the same as in ordinary SCI processing. The reception processing flowchart is shown in figure 14.7. 1. Initialize the smart card interface mode as described above in Initialization and in figure 14.5. 2. Check that the ORER and PER flags in SCSSR are cleared to 0. If either flag is set, clear both to 0 after performing the appropriate error handling procedures. 3. Repeat steps 2 and 3 until the RDRF flag is set to 1. 4. Read the receive data from SCRDR. 5. To receive more data, clear the RDRF flag to 0 and return to step 2. 6. To end reception, clear the RE bit to 0. This processing can be interrupted. When the RIE bit is set to 1 and interrupt requests are enabled, a receive-data-full interrupt (RXI) will be requested when the RDRF flag is set to 1 at the end of the reception. When an error occurs during reception and either the ORER or PER flag is set to 1, a communication error interrupt (ERI) will be requested. See Interrupt Operation, below, for more information. The received data will be transferred to SCRDR even when a parity error occurs during reception and PER is set to 1, so this data can still be read.
410
Start
Initialize
(1)
Start reception (2) No
ORER = 0 and PER = 0? Yes
Error handling No RDRF = 1? Yes Write receive data from SCRDR and clear RDRF flag in SCSSR to 0 No All data received? Yes Clear RE bit in SCSCR to 0 (6) (5) (4) (3)
End reception
Figure 14.7
Reception Flowchart (Example)
411
Switching Modes: When switching from receive mode to transmit mode, check that the receive operation is completed before starting initialization and setting RE to 0 and TE to 1. The RDRF, PER, and ORER flags can be used to check if reception is completed. When switching from transmit mode to receive mode, check that the transmit operation is completed before starting initialization and setting TE to 0 and RE to 1. The TEND flag can be used to check if transmission is completed. Interrupt Operation: In the smart card interface mode, there are three types of interrupts: transmit-data-empty (TXI), communication error (ERI) and receive-data-full (RXI). In this mode, the transmit-end interrupt (TEI) cannot be requested. Set the TEND flag in SCSSR to 1 to request a TXI interrupt. Set the RDRF flag in SCSSR to 1 to request an RXI interrupt. Set the ORER, PER, or FER/ERS flag in SCSSR to 1 to request an ERI interrupt (table 14.9). Table 14.9 Smart Card Mode Operating Status and Interrupt Sources
Mode Transmit mode Status Normal Error Receive mode Normal Error Flag TEND FER/ERS RDRF PER, ORER Mask Bit TIE RIE RIE RIE Interrupt S our ce TXI ERI RXI ERI
14.4
Usage Notes
When the SCI is used as a smart card interface, be sure that all criteria in sections 14.4.1 and 14.4.2 are applied. 14.4.1 Receive Data Timing and Receive Margin in Asynchronous Mode
In asynchronous mode, the SCI runs on a basic clock with a frequency of 372 times the transfer rate. During reception, the SCI samples the fall of the start bit using the base clock to achieve internal synchronization. Receive data is latched internally on the rising edge of the 186th basic clock cycle (figure 14.8).
412
372 clock cycles 186 clock cycles
0 185 371 0 185 371 0
Base clock Receive data (RxD) Synchronization sampling timing Data sampling timing Start bit
D0
D1
Figure 14.8
Receive Data Sampling Timing in Smart Card Mode
The receive margin is found from the following equation: For smart card mode:
M = (0.5 - 1 D - 0.5 (1 + F) x 100% ) - (L - 0.5)F - 2N N
Where: M = Receive margin (%) N = Ratio of bit rate to clock (N = 372) D = Clock duty (D = 0 to 1.0) L = Frame length (L = 10) F = Absolute value of clock frequency deviation Using this equation, the receive margin when F = 0 and D = 0.5 is as follows:
M = (0.5 - 1/2 x 372) x 100% = 49.866%
413
14.4.2
Retransmission (Receive and Transmit Modes)
Retransmission by the SCI in Receive Mode: Figure 14.9 shows the retransmission operation in the SCI receive mode. 1. When the received parity bit is checked and an error is found, the PER bit in SCSSR is automatically set to 1. If the RIE bit in SCSCR is enabled at this time, an ERI interrupt is requested. Be sure to clear the PER bit before the next parity bit is sampled. 2. The RDRF bit in SCSSR is not set in the frame that caused the error. 3. When the received parity bit is checked and no error is found, the PER bit in SCSSR is not set. 4. When the received parity bit is checked and no error is found, reception is considered to have been completed normally and the RDRF bit in SCSSR is automatically set to 1. If the RIE bit in SCSCR is enabled at this time, an RXI interrupt is requested. 5. When a normal frame is received, the pin maintains a three-state status when it transmits the error signal.
nth transfer frame
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE
Retransmitted frame
(DE) Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
Transfer frame n + 1
Ds D0 D1 D2 D3 D4
5
RDRF 2 PER 1 3 4
Figure 14.9
Retransmission in SCI Receive Mode
414
Retransmission by the SCI in Transmit Mode: Figure 14.10 shows the retransmission operation in the SCI transmit mode. 1. After transmission of one frame is completed, the FER/ERS bit in SCSSR is set to 1 when a error signal is returned from the receiving side. If the RIE bit in SCSCR is enabled at this time, an ERI interrupt is requested. Be sure to clear the FER/ERS bit before the next parity bit is sampled. 2. The TEND bit in SCSSR is not set in the frame that received the error signal that indicated the error. 3. The FER/ERS bit in SCSR is not set when no error signal is returned from the receiving side. 4. When no error signal is returned from the receiving side, the TEND bit in SCSSR is set to 1 when the transmission of the frame that includes the retransmission is considered completed. If the TIE bit in SCSCR is enabled at this time, a TXI interrupt will be requested.
nth transfer frame
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE
Retransmitted frame
(DE) Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
Transfer frame n + 1
Ds D0 D1 D2 D3 D4
TDRE Transfer from TDR to TRS TEND 2 FER/ERS 1
Transfer from TDR to TRS
Transfer from TDR to TRS 4
3
Figure 14.10
Retransmission in SCI Transmit Mode
415
416
Section 15 I/O Ports
15.1 Overview
The has an on-chip 8-bit general-purpose I/O port and an on-chip I/O port for the serial communication interface (SCI). 15.1.1 Features
The general-purpose I/O port has the following features: * Direction of each bit of the 8-bit I/O port can be set independently * When each bit is set for input mode, it is possible to set each bit for independent pull-up * Ports can be used as I/O ports or as data bus lines, for a maximum data bus width of 32 bits, by setting the PORTEN bit in bus control register 2 (BCR2) The SCI I/O port has the following features: * When the I/O port is set to output and the SCI is not enabled, data can be output. This allows transmission of the break status. SCK pin control is also possible. * The value of the RxD pin can be read at any time. This enables break detection. 15.1.2 Block Diagram
Figure 15.1 shows a block diagram of the 8-bit general-purpose I/O port.
PORT7 (I/O)/D23 (I/O) PORT6 (I/O)/D22 (I/O) PORT5 (I/O)/D21 (I/O) 8-bit port PORT4 (I/O)/D20 (I/O) PORT3 (I/O)/D19 (I/O) PORT2 (I/O)/D18 (I/O) PORT1 (I/O)/D17 (I/O) PORT0 (I/O)/D16 (I/O)
Figure 15.1 8-Bit I/O Port
417
Figures 15.2 to 15.4 show block diagrams of the SCI I/O port.
Reset R Q D Internal data bus SPB1IO C SPTRW Reset MD0/SCK R Q D SPB1DT C SPTRW
SCI
Clock output enable Serial clock output * Serial clock input Clock input enable
SPTRR SPTRW: SPTR write SPTRR: SPTR read Note: Signals that set the SCK pin function to internal clock output or external clock input as specified by the CKE0 and CKE1 bits in SCSCR, and the C/A bit in SCSMR.
Figure 15.2 SCI I/O Port: MD0/SCK Pin
418
Reset R Q D SPB0IO C SPTRW Reset MD1/TxD R Q D SPB0DT C SPTRW Internal data bus
SCI Transmit enable
Serial transmit data SPTRW: SPTR write
Figure 15.3 SCI I/O Port: MD1/TxD Pin
SCI MD2/RxD
Serial receive data
Internal data bus SPTRR SPTRR: SPTR read
Figure 15.4 SCI I/O Port: MD2/RxD Pin
419
15.1.3
Pin Configuration
Table 15.1 shows the pin configuration of the 8-bit general-purpose I/O port. Table 15.1 Pin Configuration
Pin Port 7 Port 6 Port 5 Port 4 Port 3 Port 2 Port 1 Port 0 Signal PORT7 PORT6 PORT5 PORT4 PORT3 PORT2 PORT1 PORT0 I/O I/O I/O I/O I/O I/O I/O I/O I/O Function I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port
Table 15.2 shows the pin configuration of the SCI I/O port. Table 15.2 Pin Configuration
Pin Serial transmission Serial reception Serial clock Signal TxD RxD SCK I/O O I I/O Function Serial data transmission and break status transmission Serial data reception and break status detection Serial clock input/output and I/O port
Note: These pins function as mode input pins MD0-MD2 after a power-on reset. They are made to function as serial pins by performing SCI operation settings with the TE, RE, CKEI, and CKE0 bits in SCSCR and the C/A bit in SCSMR. Break status transmission and detection can be performed by means of the SCI's SCSPTR register.
420
15.1.4
Register Configuration
Table 15.3 shows the configuration of the two registers of the 8-bit general-purpose I/O port (PCTR and PDTR) and the one register of the SCI I/O port (SCSPTR). Table 15.3 Register Configuration
Register Port control register Port data register Serial port register Symbol PCTR PDTR SCSPTR R/W R/W R/W R/W Initial Value* 1 H'0000 Undefined *
2
Address H'FFFFFF76 H'FFFFFF78 H'FFFFFF7C
Access Size 16 8 8
Notes: 1. Initialized by a power-on reset. 2. Bits other than 2 and 0 are initialized to H'00. Bits 2 and 0 are undefined.
15.2
15.2.1
Register Descriptions
Port Control Register (PCTR)
Bit: Bit name: 15 PB7 PUP Initial value: R/W: Bit: Bit name: 0 R/W 7 PB3 PUP Initial value: R/W: 0 R/W 14 PB7 IO 0 R/W 6 PB3 IO 0 R/W 13 PB6 PUP 0 R/W 5 PB2 PUP 0 R/W 12 PB6 IO 0 R/W 4 PB2 IO 0 R/W 11 PB5 PUP 0 R/W 3 PB1 PUP 0 R/W 10 PB5 IO 0 R/W 2 PB1 IO 0 R/W 9 PB4 PUP 0 R/W 1 PB0 PUP 0 R/W 8 PB4 IO 0 R/W 0 PB0 IO 0 R/W
The port control register (PCTR) is a 16-bit read/write register that controls the input/output direction and pull-up for each bit in the 8-bit port. As the initial value of the port data register (PDR) is undefined, all the bits in the 8-bit port should be set to output with PCTR after writing a value to the PDTR register. PCTR is initialized to H'0000 by a power-on reset. It is not initialized by a manual reset or in standby mode, and retains its contents.
421
Bit 2n + 1 (n = 0-7): Port Pull-Up Control (PBnPUP): Controls the pull-up of each bit in the 8-bit port by means of built-in resistors. This setting is valid even if the port pin is set to output by the PBnIO bit. Therefore, to avoid unnecessary power consumption and ensure the reliability of the chip, a pull-up setting should not be made when the corresponding port pin has been set to output.
Bit 2n + 1: P Bn P U P 0 1 Description Bit n (n = 0-7) of the 8-bit port is pulled up. (Initial value) Bit n (n = 0-7) of the 8-bit port is not pulled up.
Bit 2n (n = 0-7)--Port I/O Control (PBnDIR): Controls whether each bit of 8-bit port is an input or an output.
Bit 2n: PBnIO 0 1 Description Bit n (n = 0-7) of the 8-bit port is an input. (Initial value) Bit n (n = 0-7) of the 8-bit port is an output.
15.2.2
Port Data Register (PDTR)
The port data register (PDTR) is an 8-bit read/write register used as data latches for each bit of the 8-bit port. When a bit is set to be used as an output, the value written into PDTR is output from the external pin. When a value is read from PDTR, the external pin value sampled on the external bus clock is returned. PDTR is not initialized by a power-on reset or manual reset, or in standby mode, and it retains its contents. However, if PDTR is read when a bus release request is issued (when BREQ is asserted), its value may not be read correctly. Therefore, BREQ should not be asserted when reading PDTR.
Bit: Bit name: Initial value: R/W: 7 PB7DT -- R/W 6 PB6DT -- R/W 5 PB5DT -- R/W 4 PB4DT -- R/W 3 PB3DT -- R/W 2 PB2DT -- R/W 1 PB1DT -- R/W 0 PB0DT -- R/W
422
15.2.3
Serial Port Register (SCSPTR)
The serial port register (SCSPTR) is an 8-bit register that the CPU can always read and write. It controls I/O and data of the port multiplexed with the serial communication interface (SCI) pins. Input data can be read from the RxD pin and output data can be transmitted to the TxD pin; this controls breaks for serial transmission and reception. In addition, SCK pin data reading and output data writing can be performed by means of bits 3 and 2. All SCSPTR bits except bits 2 and 0 are initialized to 0 by a power-on reset; the value of bits 2 and 0 is undefined. SCSPTR is not initialized by a manual reset or in standby mode, and it retains its contents.
Bit: Bit name: Initial value: R/W: 7 -- 0 R 6 -- 0 R 5 -- 0 R 4 -- 0 R 3 2 1 0
SPB1IO SPB1DT SPB0IO SPB0DT 0 R/W -- R/W 0 R/W -- R/W
Bits 7 to 4--Reserved: These bits always read 0. The write value should always be 0. Bit 3--Serial Port Clock Port I/O (SPB1IO): Specifies serial port SCK pin input/output. When the SCK pin is actually set as a port output pin and outputs the value set by the SPB1DT bit, the C/A bit in SCSMR and the CKE1 and CKE0 bits in SCSCR should be cleared to 0.
Bit 3: SPB1IO 0 1 Description The SPB1DT value is not output to the SCK pin. (Initial value) The SPB1DT bit value is output to the SCK pin.
Bit 2--Serial Port Clock Port Data (SPB1DT): Specifies the serial port SCK pin input/output data. Input or output is specified by the SPB1IO bit (see the description of SPB1IO for details). When output is specified, the value of the SPB1DT bit is output to the SCK pin. The SCK pin value is read from the SPB1DT bit regardless of the value of the SPB1IO bit. The initial value of this bit after a power-on reset is undefined.
Bit 2: SPB1DT 0 1 Description I/O data level is low. (Initial value) I/O data level is high.
423
Bit 1--Serial Port Break I/O (SPB0IO): Specifies the serial port TxD pin output condition. When the TxD pin is actually set as a port output pin and outputs the value set by the SPB0DT bit, the TE bit in SCSCR should be cleared to 0.
Bit 1: SPB0IO 0 1 Description The SPB0DT bit value is not output to the TxD pin. (Initial value) The SPB0DT bit value is output to the TxD pin.
Bit 0-Serial Port Break Data (SPB0DT): Specifies serial port RxD pin input data and TxD pin output data. The TxD pin output condition is set with the SPB0IO bit (see the description of SPB0IO above). When the TxD pin is set as an output, the value of the SPB0DT bit is output to the TxD pin. The RxD pin value is always read from the SPB0DT bit, regardless of the value of the SPB0IO bit. The initial value of this bit after a power-on reset is undefined.
Bit 0 : SPB0DT 0 1 Description I/O data level is low. (Initial value) I/O data level is high.
424
Section 16 Electrical Characteristics (-SH7708, SH7708S-)
16.1 Absolute Maximum Ratings
Table 16.1 Absolute Maximum Ratings
Item Power supply voltage Input voltage Operating temperature Storage temperature Symbol VCC Vin Topr Tstr Ratings -0.3 to 4.6 -0.3 to VCC + 0.3 -20 to 75 -55 to 125 Units V V C C
Note: Operating the SH7708 Series above maximum ratings can damage or destroy it.
425
16.2
DC Characteristics
Table 16.2 DC Characteristics (Ta = -20 to 75C)
Item Power supply voltage SymbolMin VCC 3.0 2.0 Current Normal operation ICC -- -- -- In sleep mode -- -- -- In standby mode -- -- -- -- Input voltage RESET, NMI BREQ, IRL3-IRL0, MD5-MD0 EXTAL, CKIO Other input pins RESET, NMI BREQ, IRL3-IRL0, MD5-MD0 Other input pins Input leak All input pins current |lin| VIL VIH Type Max 3.3 3.3 -- -- -- 75*1 40*2 20*3 15 -- 5 -- 3.6 3.6 195*1 100*2 50*3 95*1 50*2 25*3 30 400 15 300 VCC + 0.3 V VCC + 0.3 VCC + 0.3 VCC + 0.3 VCC + 0.3 VCC x 0.1 0.5 VCC x 0.2 VCC x 0.2 1.0 1.0 A Vin = 0.5 to VCC - 0.5 V A Vin = 0.5 to VCC - 0.5 V Standby mode Normal operation Standby mode Normal operation A Ta = 25C (RTC on) Ta > 50C (RTC on) Ta = 25C (RTC off) Ta > 50C (RTC off) UnitRemarks V In normal operation, sleep mode, and standby mode RTC operating voltage in standby mode mA VCC = 3.3 V *1: 60 MHz (Po = 30 MHz) *2: 30 MHz *3: 15 MHz
VCC x 0.9 -- VCC - 0.5 -- VCC - 0.7 -- VCC - 0.7 -- 2.0 -0.3 -0.3 -0.3 -0.3 -- -- -- -- -- -- -- -- --
ThreeI/O, output, all pins |lsti| state leak (off condition) current
426
Table 16.2 DC Characteristics (Ta = -20 to 75C) (cont)
Item Output voltage All output pins SymbolMin VOH 2.4 2.0 VOL Pull-up Port pins resistance Terminal capacitance All pins Rpull C -- 30 -- Type Max -- -- -- 60 -- -- -- 0.55 120 20 k pF Unit V Remarks VCC = 3.0 V, IOH = -200 A VCC = 3.0 V, IOH = -2 mA VCC = 3.6 V, IOL = 1.6 mA
Notes: 1. Regardless of whether PLL or RTC is used, connect PLLVCC, RTCVCC to VCC, and PLLGND, RTCGND to GND. 2. With VIH min = VCC - 0.5 V, VIL max = 0.5 V, and all output pins unloaded.
Table 16.3 Permissible Output Current Values (VCC = 3.3 0.3 V, Ta = -20 to 75C)
Item Permissible output low current (per pin) Permissible output low current (total) Permissible output high current (per pin) Permissible output high current (total) Symbol IOL IOL -IOH (-IOH) Min -- -- -- -- Typ -- -- -- -- Max 2.0 120 2.0 40 Unit mA
Note: To ensure reliability, output current must not exceed the maximum values listed.
16.3
AC Characteristics
Input for the SH7708 Series should, as a rule, be clock synchronous. Keep to the setup and hold times for each input signal unless otherwise directed. Table 16.4 LSI Clock Values (Ta = -20 to 75C)
Item Operating frequency CPU, cache, TLB External bus Peripheral modules Symbol f Min 1 1 0.25 Typ -- -- -- Max 60 60 30 Unit MHz
427
16.3.1
Clock Timing
Table 16.5 Clock Timing (VCC = 3.3 0.3 V, Ta = -20 to +75C, Maximum External Bus Operating Frequency: 15 MHz)
Item EXTAL clock input frequency EXTAL clock input cycle time EXTAL clock input low level pulse width EXTAL clock input high level pulse width EXTAL clock input rise time EXTAL clock input fall time CKIO clock frequency (input) CKIO clock cycle time (input) CKIO clock low-level pulse width (input) CKIO clock high-level pulse width (input) CKIO clock rise time (input) CKIO clock fall time (input) CKIO clock output frequency (output) CKIO clock cycle time (output) CKIO clock low-level pulse width (output) CKIO clock high-level pulse width (output) CKIO clock rise time (output) CKIO clock fall time (output) Power-on oscillation settling time Power-on oscillation settling time/mode setting BREQ reset hold time RESET set-up time BREQ set-up time MD reset hold time Reset assert time Symbol fEX tEXcyc tEXL tEXH tEXR tEXF fCKI tCKIcyc tCKIL tCKIH tCKIR tCKIF fOP tcyc tCKOL tCKOH tCKOR tCKOF tOSC1 tOSCMD tBREQRH tRESS tBREQS tMDRH tRESW Min 2 33.3 8*1 or 12*2 8*1 or 12*2 -- -- 8 66.7 8 8 -- -- 1 66.7 20 20 -- -- 10 10 0 20 20 20 20 Max 30 500 -- -- 4 4 15 125 -- -- 4 4 15 1000 -- -- 7 7 -- -- -- -- -- -- -- Unit MHz ns ns ns ns ns MHz ns ns ns ns ns MHz ns ns ns ns ns ms ms ns ns ns ns tcyc 16.4, 16.5, 16.11 16.5 16.4 16.3 16.2 Figure 16.1
Standby return oscillation settling time 1
tOSC2
10
--
ms
428
Table 16.5 Clock Timing (VCC = 3.3 0.3 V, Ta = -20 to +75C, Maximum External Bus Operating Frequency: 15 MHz) (cont)
Item Standby return oscillation settling time 2 Standby return oscillation settling time 3 PLL synchronization settling time Symbol tOSC3 tOSC4 tPLL Min 10 11 100 Max -- -- -- Unit ms ms Figure 16.6 16.7 16.8, 16.9, 16.10 16.10
s s
IRL interrupt decision time (using RTC and in standby mode) Notes: 1. PLL circuit 2 in operation. 2. PLL circuit 2 not in operation.
tIRLSTB
100
--
429
Table 16.6 Clock Timing (VCC = 3.3 0.3 V, Ta = -20 to 75C, Maximum External Bus Operating Frequency: 30 MHz)
Item EXTAL clock input frequency EXTAL clock input cycle time EXTAL clock input low level pulse width EXTAL clock input high level pulse width EXTAL clock input rise time EXTAL clock input fall time CKIO clock frequency (input) CKIO clock cycle time (input) CKIO clock low-level pulse width (input) CKIO clock high-level pulse width (input) CKIO clock rise time (input) CKIO clock fall time (input) CKIO clock output frequency (output) CKIO clock cycle time (output) CKIO clock low-level pulse width (output) Symbol fEX tEXcyc tEXL tEXH tEXR tEXF fCKI tCKIcyc tCKIL tCKIH tCKIR tCKIF fOP tcyc tCKOL tCKOR tCKOF tOSC1 tOSCMD tBREQRH tRESS tBREQS tMDRH tRESW Min 2 33.3 7*1 7*1 -- -- 8 33.3 7 7 -- -- 1 33.3 8 8 -- -- 10 10 0 20 20 20 20 or or 10*2 10*2 Max 30 500 -- -- 4 4 30 125 -- -- 3 3 130 1000 -- -- 6 6 -- -- -- -- -- -- -- Unit MHz ns ns ns ns ns MHz ns ns ns ns ns MHz ns ns ns ns ns ms ms ns ns ns ns tcyc 16.4, 16.5, 16.11 16.5 16.6 16.7 16.4 16.3 16.2 Figure 16.1
CKIO clock high-level pulse width (output) tCKOH CKIO clock rise time (output) CKIO clock fall time (output) Power-on oscillation settling time Power-on oscillation settling time/mode setting BREQ reset hold time RESET set-up time BREQ set-up time MD reset hold time Reset assert time
Standby return oscillation settling time 1 Standby return oscillation settling time 2 Standby return oscillation settling time 3
tOSC2 tOSC3 tOSC4
10 10 11
-- -- --
ms ms ms
430
Table 16.6 Clock Timing (VCC = 3.3 0.3 V, Ta = -20 to 75C, Maximum External Bus Operating Frequency: 30 MHz) (cont)
Item PLL synchronization settling time Symbol tPLL Min 100 Max -- Unit Figure 16.8, 16.9, 16.10 16.10
s s
IRL interrupt decision time (using RTC and tIRLSTB in standby mode) Notes: 1. PLL circuit 2 in operation. 2. PLL circuit 1 not in operation.
100
--
431
Table 16.7 Clock Timing (VCC = 3.3 0.3 V, Ta = -20 to 75C, Maximum External Bus Operating Frequency: 60 MHz)
Item EXTAL clock input frequency EXTAL clock input cycle time EXTAL clock input low-level pulse width EXTAL clock input high-level pulse width EXTAL clock input rise time EXTAL clock input fall time CKIO clock frequency (input) CKIO clock cycle time (input) CKIO clock low-level pulse width (input) CKIO clock high-level pulse width (input) CKIO clock rise time (input) CKIO clock fall time (input) CKIO clock output frequency (output) CKIO clock cycle time (output) CKIO clock low-level pulse width (output) Symbol fEX tEXcyc tEXL tEXH tEXR tEXF fCKI tCKIcyc tCKIL tCKIH tCKIR tCKIF fOP tcyc tCKOL tCKOR tCKOF tOSC1 tOSCMD tBREQRH tRESS tBREQS tMDRH tRESW Min 2 16.7 4*1 4*1 -- -- 8 16.7 4 4 -- -- 1 16.7 3 3 -- -- 10 10 0 20 20 20 20 or or 10*2 10*2 Max 60 500 -- -- 2 2 60 125 -- -- 2 2 60 1000 -- -- 5 5 -- -- -- -- -- -- -- Unit MHz ns ns ns ns ns MHz ns ns ns ns ns MHz ns ns ns ns ns ms ms ns ns ns ns tcyc 16.4, 16.5, 16.11 16.5 16.6 16.7 16.4 16.3 16.2 Figure 16.1
CKIO clock high-level pulse width (output) tCKOH CKIO clock rise time (output) CKIO clock fall time (output) Power-on oscillation settling time Power-on oscillation settling time/mode setting BREQ reset hold time RESET set-up time BREQ set-up time MD reset hold time Reset assert time
Standby return oscillation settling time 1 Standby return oscillation settling time 2 Standby return oscillation settling time 3
tOSC2 tOSC3 tOSC4
10 10 11
-- -- --
ms ms ms
432
Table 16.7 Clock Timing (VCC = 3.3 0.3 V, Ta = -20 to 75C, Maximum External Bus Operating Frequency: 60 MHz) (cont)
Item PLL synchronization settling time Symbol tPLL Min 100 Max -- Unit Figure 16.8, 16.9, 16.10 16.10
s s
IRL interrupt decision time (using RTC and tIRLSTB in standby mode) Notes: 1. PLL circuit 2 in operation. 2. IPLL circuit 2 not in operation.
100
--
tEXcyc EXTAL* (input) 1/2 VCC tEXH tEXL VIH 1/2 VCC tEXR
VIH
VIH VIL tEXF VIL
Note: The clock input from the EXTAL pin.
Figure 16.1
EXTAL Clock Input Timing
tCKIcyc tCKIH tCKIL VIH VIL tCKIF VIH VIL
CKIO (input) 1/2 VCC
VIH
1/2 VCC tCKIR
Figure 16.2
CKIO Clock Input Timing
433
tcyc tCKOH CKIO (output) tCKOL
1/2VCC
VIH
VOH VOL tCKOF
VOH VOL
1/2VCC tCKOR
CKIO, internal clock VCC
,,, ,,,
Figure 16.3
VCC min
CKIO Clock Output Timing
Stable oscillation
tRESW tOSC1
tRESS
RESET
tBREQS tBREQRH
BREQ tOSCMD tMDRH MD0-MD2
Note: Oscillation settling time when built-in oscillator is used
Figure 16.4
Power-On Oscillation Settling Time
434
Standby CKIO, internal clock
RES
,, ,, ,,
Stable oscillation
tOSC2
tRESW
Note: Oscillation settling time when built-in oscillator is used
Figure 16.5
Standby Return Oscillation Settling Time (Return by RESET)
Stable oscillation
Standby CKIO, internal clock
tOSC3
NMI
Note: Oscillation settling time when built-in oscillator is used
Figure 16.6
Standby Return Oscillation Settling Time (Return by NMI)
435
Standby CKIO, internal clock
,, ,,
Stable oscillation
tOSC4
IRL3-IRL0
Note: Oscillation settling time when built-in oscillator is used
Figure 16.7
Standby Return Oscillation Settling Time (Return by IRL3-IRL0)
Reset or NMI interrupt request
Stable input clock EXTAL input or CKIO input PLL synchronization PLL output, CKIO output
Stable input clock
tPLL
PLL synchronization
Internal clock
STATUS 0 STATUS 1
Normal
Standby
Normal
Note: PLL oscillation settling time when clock is input from EXTAL pin or CKIO pin
Figure 16.8
PLL Synchronization Settling Time in Case of Reset or NMI Interrupt
436
IRL (3-0) interrupt request Stable input clock EXTAL input or CKIO input PLL synchronization PLL output, CKIO output tIRLSTB tPLL PLL synchronization Stable input clock
Internal clock
STATUS 0 STATUS 1
Normal
Standby
Normal
Note: PLL oscillation settling time when clock is input from EXTAL pin or CKIO pin
Figure 16.9
EXTAL input or on-chip oscillator output CKOEN
PLL Synchronization Settling Time in Case of IRL Interrupt
CKIO PLL synchronization PLL1 output tPLL PLL synchronization tPLL PLL synchronization
Internal clock
Note: PLL oscillation settling time when output clock is controlled by Clock Mode 0-2
Figure 16.10
PLL Synchronization Settling Time in Case of CKOEN Bit Manipulation
437
16.3.2
Control Signal Timing
Table 16.8 Control Signal Timing (VCC = 3.3 0.3 V, Ta = -20 to + 75C)
-60*2 Item RESET pulse width RESET setup time RESET hold time BREQ setup time BREQ hold time BREQ reset setup time BREQ reset hold time MD reset setup time MD reset hold time NMI setup time*1 time*1 Symbol tRESW tRESS tRESH tBREQS tBREQH tBREQRS tBREQRH tMDRS tMDRH tNMIS tIRLS tNMIH tIRLH tIRQOD tBACKD tSTD tBOFF1 tBOFF2 tBON1 tBON2 Min 20 23 2 12 3 17 16 20 16 15 10 4 4 -- -- -- 0 0 0 0 Max -- -- -- -- -- -- -- -- -- -- -- -- -- 12 12 16 16 16 16 16 Unit tcyc ns ns ns ns ns ns tcyc ns ns ns ns ns ns ns ns ns ns ns ns 16.15, 16.16 16.13, 16.14 16.12 Figure 16.11, 16.13, 16.15
IRL3 -IRL0 setup NMI hold time
IRL3 -IRL0 hold time IRQOUT delay time BACK delay time STATUS1, STATUS0 delay time Bus tri-state delay time 1 Bus tri-state delay time 2 Bus buffer on time 1 Bus buffer on time 2
Notes: 1. RESET, NMI, and IRL3 to IRL0 are asynchronous. Changes are detected at the clock fall when the setup shown is used. When the setup cannot be used, detection can be delayed until the next clock fall. 2. Upper limit of external bus clock is 60 MHz.
438
CKIO tRESS tRESW RESET tBREQRS tBREQS tBREQRH tRESS
BREQ
Figure 16.11
Manual Reset Input Timing
RESET tMDRS tMDRH
MD0-MD5
Figure 16.12
Mode Input Timing
439
CKIO tRESH RESET tNMIH NMI tIRLH IRL3-IRL0 tRESS VIH VIL tNMIS VIH VIL tIRLS VIH VIL
Figure 16.13
Interrupt Signal Input Timing
CKIO tIRQOD tIRQOD
IRQOUT
Figure 16.14 IRQOUT Timing
440
CKIO tBREQH tBREQS BREQ tBACKD BACK RD, RD/WR, RAS, CAS, CSn, WEn, BS A25-A0, D31-D0 tBOFF2 tBON2 tBACKD tBREQH tBREQS
tBOFF1
tBON1
Figure 16.15
Normal mode
Bus Release Timing
Normal mode
Standby mode
CKIO tSTD STATUS 0 STATUS 1 tBOFF2 RD, RD/WR, RAS, CAS, CSn, WEn, BS A25-A0, D31-D0 tBON2 tSTD
tBOFF1
tBON1
Figure 16.16
Pin Drive Timing for Standby Mode
441
16.3.3
AC Bus Timing Specifications
Table 16.9 Bus Timing (Conditions: Clock Mode 0/1/2/7, V CC = 3.3 0.3 V, Ta = -20 to 75C)
-60*1 Item Address delay time Address setup time Address hold time BS delay time CS delay time 1 CS delay time 2 Read write delay time Read write setup time Read write hold time Read strobe delay time Read data setup time 1 Read data setup time 2 Read data hold time 1 Read data hold time 2 Write enable delay time Write data delay time 1 Write data delay time 2 Write data setup time Write data hold time 1 Write data hold time 2 Write data hold time 3 Write data hold time 4 WAIT setup time* WAIT hold time*
2 2
Symbol tAD tAS tAH tBSD tCSD1
t CSD2
Min -- 0 0 -- -- -- -- 0 0 -- 12 8 0 3 -- -- -- 0 0 0 0 0 12 4
Max 13 -- -- 12 12 12 12 -- -- 12 -- -- -- -- 12 15 15 -- -- -- -- -- -- --
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Figure 16.17-16.58
tRWD tRWS tRWH tRSD tRDS1 tRDS2 tRDH1 tRDH2 tWED tWDD1 tWDD2 tWDS tWDH1 tWDH2 tWDH3 tWDH4 tWTS tWTH
442
Table 16.9 Bus Timing (Conditions: Clock Mode 0/1/2/7, V CC = 3.3 0.3 V, Ta = -20 to 75C) (cont)
-60*1 Item RAS delay time 1 RAS delay time 2 CAS delay time 1 CAS delay time 2 DQM delay time CKE delay time CE delay time OE, RFSH delay time ICIORD delay time ICIOWR delay time IOIS16 setup time IOIS16 hold time Symbol tRASD1 tRASD2 tCASD1 tCASD2 tDQMD tCKED tCED tOED tICRSD tICWSD tIO16S tIO16H Min -- -- -- -- -- -- -- -- -- -- 12 4 Max 13 13 13 13 12 12 13 13 12 12 -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns 16.56-16.58 16.45-16.51 Figure 16.23-16.44
Notes: 1. Upper limit of external bus clock is 60 MHz. 2. WAIT is a synchronous signal. Operation cannot be guaranteed if the setup and hold times shown here are not observed.
443
Table 16.10 Bus Timing (Conditions: Clock Mode 3/4/5/6, V CC = 3.3 0.3 V, Ta = -20 to 75C)
Item Address delay time Address setup time Address hold time BS delay time CS delay time 1 CS delay time 2 Read write delay time Read write setup time Read write hold time Read strobe delay time Read data setup time 1 Read data setup time 2 Read data hold time 1 Read data hold time 2 Write enable delay time Write data delay time 1 Write data delay time 2 Write data setup time Write data hold time 1 Write data hold time 2 Write data hold time 3 WAIT setup time WAIT hold time Symbol tAD tAS tAH tBSD tCSD1
t CSD2
Min -- 0 20 -- -- -- -- 0 0 -- 12 12 0 8 -- -- -- 0 0 0 0 12 8
Max 20 -- -- 19 19 20 19 -- -- 20 -- -- -- -- 20 25 19 -- -- -- -- -- --
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Figure 16.17-16.58
tRWD tRWS tRWH tRSD tRDS1 tRDS2 tRDH1 tRDH2 tWED tWDD1 tWDD2 tWDS tWDH1 tWDH2 tWDH3 tWTS tWTH
444
Table 16.10 Bus Timing (Conditions: Clock Mode 3/4/5/6, V CC = 3.3 0.3 V, Ta = -20 to 75C) (cont)
Item RAS delay time 1 RAS delay time 2 CAS delay time 1 CAS delay time 2 DQM delay time CKE delay time CE delay time OE, RFSH delay time ICIORD delay time ICIOWR delay time IOIS16 setup time IOIS16 hold time Symbol tRASD1 tRASD2 tCASD1 tCASD2 tDQMD tCKED tCED tOED tICRSD tICWSD tIO16S tIO16H Min -- -- -- -- -- -- -- -- -- -- 12 8 Max 20 19 20 19 19 19 20 20 20 20 -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns 16.56-16.58 16.45-16.51 Figure 16.23-16.44
445
16.3.4
Basic Timing
T1 CKIO tAD A25-A0
T2
tAD
tAH tCSD1 CSn tRWD RD/WR tAH tRSD RD (read) tRDS1 D31-D0 (read) tAH tWED WEn (write) tWED tRWH tWDH3 tWDH1 tRSD tRWH tRDH1 tRWD tCSD2 tRWH
tRDH1
D31-D0 (write)
BS
,, ,
tWDD1 tBSD
tBSD
Figure 16.17 Basic Bus Cycle (No Wait)
446
T1
Tw
T2
CKIO tAD A25-A0 tAH tCSD1 CSn tRWD RD/WR tAH tRSD1 RD (read) tRDS1 D31-D0 (read) tWED1 WEn (write) tWED tAH tRWH tWDH3 tRSD tRWH tRDH1 tRWD tCSD2 tRWH tAD
tRDH1
D31-D0 (write)
WAIT
,, ,,,,,,,,, ,,,,,,,,,
tWDD1 tWDH1 tBSD tBSD BS tWTS tWTH
Figure 16.18
Basic Bus Cycle (1 Wait)
447
T1
Tw
Tw
T2
CKIO tAD A25-A0 tAH tCSD1 CSn tRWD RD/WR tAH tRSD RD (read) tRDS1 D31-D0 (read) tAH tWED WEn (write) tWED tRWH tWDH3 tRSD tRWH tRDH1 tRWD tCSD2 tRWH tAD
tRDH1
D31-D0 (write)
BS
WAIT
,, ,,,,,,,,, ,,,,,,,,,
tWDD1 tWDH1 tBSD tBSD tWTS tWTH tWTS tWTH
Figure 16.19
Basic Bus Cycle (External Wait)
448
16.3.5
Burst ROM Timing
T1
TB2
TB1
TB2
TB1
TB2
TB1
T2
CKIO tAD A25-A4 tAD A3-A0 tAH tCSD1 CSn tRDH1 tRWD RD/WE tRSD RD tRSD tAH tRSD tRWD tAH tRSD tRWH tCSD2 tRWH tAD tAD
D31-D0
WAIT
Note: In the write cycle, the basic bus cycle is performed.
,,,,,, ,,,,,, ,,,, ,,, ,,, ,, ,,,, ,,, ,,, ,,
tRDH1 tRDH1 tRDS tRDS1 tBSD tBSD tBSD tBSD BS tWTS tWTH
Figure 16.20 Burst ROM Bus Cycle (No Wait)
449
T1
Tw
Tw
TB2
TB1
Tw
TB2
T2
T2
CKIO tAD A25-A4 tAD A3-A0 tAH tCSD1 CSn tRDH1 tRWD RD/WE tRSD RD tRDH1 tRDS1 D31-D0 tBSD BS tBSD tBSD tBSD tRDS1 tRDH1 tRDH1 tRSD tAH tRSD tRSD tRSD tRWD tCSD2 tRWH tAD
tAH tRWH
,,,,,,,,,, ,,
tWTS tWTH tWTS tWTH tWTS tWTH tWTS tWTH WAIT Note: In the write cycle, the basic bus cycle is performed.
Figure 16.21 Burst ROM Bus Cycle (2 Waits)
450
T1 CKIO tAD A25-A4
Tw
Tw
TB2
TB1
TBw
T2
tAD
tAD A3-A0 tAH tCSD1 CSn tRDH1 tRWD RD/WE tRSD tRSD1 tAH tRSD1 tAH tRSD tRWH tRWD tCSD2 tRWH
D31 to D0
WAIT
Note: In the write cycle, the basic bus cycle is performed.
,,, ,,, ,,,,,,,, ,, ,,
RD tRDH1 tRDH1 tRDS1 tRDS tBSD tBSD tBSD tBSD BS tWTS tWTH tWTS tWTH tWTS tWTH tWTS tWTH
Figure 16.22
Burst ROM Bus Cycle (External Wait Input)
451
16.3.6
DRAM Timing
Tr Tc1 Tc2 (Tpc)
CKIO tAD A25 to A16 tAD A15 to A0 tRWD RD/WR tAH tRASD1 RAS tCASD1 CASxx tWDS tRDS1 D31-D0 (read) tWDH3 tWDD2 D31-D0 (write) tBSD BS tBSD tWDH1 tRDH1 tCASD1 tRASD1 tRWH Row address tAS tAD tAS Column address tRWD tAD
Row address tAH
tAH tRWH
tCSD1
tCSD1
CS2 or CS3
452
Figure 16.23 DRAM Bus Cycle (RCD = 0, AnW = 1, TPC = 0)
Tr CKIO tAD A25 to A16 tAD tAS A15 to A0 tRWD RD/WR tAH tRASD1 RAS tAH tCASD1 CASxx tWDS tRDS1 D31-D0 (read) tWDD2 D31-D0 (write) tBSD BS tCSD1 tBSD tCSD1 tWDH3 tWDH1 tRDH1 tCASD1 tRWH tRASD1 tRWH Row address tAH Row address tAD tAS Column address tRWD tAD Trw Trw Tc1 Tcw Tc2 (Tpc) (Tpc)
CS2 or CS3
Figure 16.24 DRAM Bus Cycle (RCD = 2, AnW = 2, TPC = 1)
453
Tr CKIO tAD A25-A16
Tc1
Tc2
Tc1
Tc2
Tc1
Tc2
Tc1
Tc2
(Tpc)
tAD Row address
tAD tAS tAD tAS A15-A0 tRWD RD/WR
Row address
tAD
Column address Column address Column address Column address
tAH
tRWD
tAH tRASD1 RAS tAH tCASD1 CASxx tWDS tRDS1 D31-D0 (read) tWDH3 tWDD2 D31-D0 (write) tWDD2 tWDH3 tWDH1 tCASD1 tCASD1 tCASD1 tRWH tRASD1 tRWH
tRDH1
tRDS1
tRDH1
tBSD
tBSD
BS tCSD1 tCSD1
CS2 or CS3
Figure 16.25
DRAM Burst Bus Cycle (RCD = 0, AnW = 1, TPC = 0)
454
Tr
Trw
Trw
Tc1
Tcw
Tc2
Tc1
Tcw
Tc2
(Tpc)
CKIO tAD A25-A16 tAD Row address tAS tAD tAS tAD Column address tRWD RD/WR tAH tRASD1 RAS tCASD1 tCASD1 tCASD1 CASxx tWDS tRDH1 tRDS1 D31-D0 (read) tWDD2 D31-D0 (write) tBSD BS tCSD1 CS2 or CS3 tCSD1 tBSD tWDH3 tWDD2 tWDH3 tWDH1 tRDS1 tRDH1 tRASD1 tAH tRWH tRWH tAD
A15-A0
Row address tRWD tAH
Column address
Figure 16.26
DRAM Burst Bus Cycle (RCD = 2, AnW = 2, TPC = 0)
455
Tr
Tc1
Tc2
(Tpc)
CKIO tAD A25-A16 tAD A15-A0 tRWD RD/WR tRASD1 tRASD2 Row address tAS tAD tAS Column address tRWH tRWD tAH tAD
Row address tAH
RAS tCASD1 CASxx tWDS tRDS2 tRDH2 tCASD1
D31-D0 (read) tWDD2 D31-D0 (write) tBSD BS tCSD1 CS2 or CS3 tCSD1 tBSD tWDH3 tWDH1
Figure 16.27
DRAM Bus Cycle (EDO Mode, RCD = 0, AnW = 1, TPC = 0)
456
Tr
Trw
Trw
Tc1
Tcw
Tc2
(Tpc)
(Tpc)
CKIO tAD A25-A16 Row address tAD tAS A15-A0 tRWD RD/WR tRASD1 RAS tCASD1 CASxx tWDS D31-D0 (read) tWDD2 D31-D0 (write) tBSD BS tCSD1 CS2 or CS3 tCSD1 tBSD tWDH3 tWDH1 tRDS2 tRDH2 tCASD1 tRASD2 Row address tAH tAD tAS Column address tRWH tRWD tAH tAD
Figure 16.28
DRAM Bus Cycle (EDO Mode, RCD = 2, AnW = 2, TPC = 1)
457
Tr
Tc1
Tc2
Tc1
Tc2
Tc1
Tc2
Tc1
Tc2
(Tpc)
CKIO tAD A25-A16 tAD A15-A0 Row address tAS tAD tAS Row address tRWD tAH RD/WR tRASD1 RAS tCASD1 tCASD1 CASxx tWDS D31-D0 (read) tWDD2 D31-D0 (write) tBSD BS tCSD1 CS2 or CS3 tCSD1 tBSD tWDH3 tWDD2 tWDH3 tWDH1 tRDS2 tRDH2 tRDS2 tRDH2 tCASD1 tCASD1 tRASD2 Column address tAH tAD Column address Column address Column address tRWH tRWD tAD
tAH
Figure 16.29
DRAM Burst Bus Cycle (EDO Mode, RCD = 0, AnW = 1, TPC = 0)
458
Tr
Trw
Trw
Tc1
Tcw
Tc2
Tc1
Tcw
Tc2
(Tpc)
CKIO tAD A25-A16 Row address tAD tAS A15-A0 tRWD RD/WR tRASD1 RAS tCASD1 CASxx tWDS D31-D0 (read) tWDD2 D31-D0 (write) tBSD BS tCSD1 CS2 or CS3 tCSD1 tBSD tWDH3 tWDD2 tWDH3 tWDH1 tRDS2 tRDH2 tRDS2 tRDH2 tCASD1 tCASD1 tRASD2 Row address tAH tAD tAS Column address tAD tAH Column address tAH tRWH tRWD tAD
Figure 16.30
DRAM Burst Bus Cycle (EDO Mode, RCD = 2, AnW = 2, TPC = 0)
459
TRc
TRr1
TRrw
TRr2
(Tpc)
CKIO tRASD1 tRASD1
RAS tCASD1 tCASD1
CASxx tRWD RD/WR (High) CS2 or CS3
Figure 16.31
TRc
DRAM CAS-Before-RAS Refresh Cycle (TRAS = 0, TPC = 0)
TRr1 TRrw TRrw TRrw TRrw TRr2 (Tpc) (Tpc) (Tpc)
CKIO tRASD1 RAS tCASD1 tCASD1 tRASD1
CASxx tRWD RD/WR
CS2 or CS3
(High)
Figure 16.32
DRAM CAS-Before-RAS Refresh Cycle (TRAS = 3, TPC = 2)
460
TRc
TRr1
TRrw
TSR1
TSR1
TSR2
(Tpc)
(Tpc)
CKIO tRASD1 RAS tCASD1 tCASD1 tRASD1
CASxx tRWD RD/WR
CS2 or CS3
(High)
Figure 16.33
DRAM Self-Refresh Cycle (TPC = 0)
461
16.3.7
Synchronous DRAM Timing
Tr CKIO tAD A25-A16 tAD A12 or A10 tAD A15-A0 tCSD1 CSn tRWD RD/WR tRASD2 RAS
Tc1
Tc2
(Tpc)
Row address tAD
Row Read A address command tAD Row address
Column address
,,, ,,,
tAD tAD tCSD1 tRWD tCASD2 tDQMD tRDS2 tRDH2
tAD
tRASD2
tCASD2 CAS DQMxx tDQMD
D31-D0 tBSD BS tBSD
CKE
(High)
Figure 16.34
462
Synchronous DRAM Read Bus Cycle (RCD = 0, CAS Latency = 1, TPC = 0)
Tr CKIO tAD A25-A16 tAD A12 or A10 tAD A15-A0
Trw
Trw
Tc1
Tcw
Td1
(Tpc)
(Tpc)
Row address
tAD Row address
tAD Row address
,,,
tAD
Read A command
tAD
tAD
Column address
tCSD1 CSn tRWD RD/WR tRASD2 RAS tCASD2 CAS tDQMD DQMxx tCASD2 tRASD2
tCSD1
tRWD
tDQMD
tRDS2 tRDH2 D31-D0 tBSD BS CKE (High) tBSD
Figure 16.35
Synchronous DRAM Read Bus Cycle (RCD = 2, CAS Latency = 2, TPC = 1)
463
Tr CKIO tAD A25-A16 tAD A12 or A10 tAD A15-A0
Tc1
Tc2/Td1 Tc3/Td2 Tc4/Td3
Td4
(Tpc)
(Tpc)
tAD Row address tAD
Row address
Read command
tAD
Row address
Column address (1-4)
tCSD1 CSn tRWD RD/WR tRASD2 RAS tCASD2 CAS DQMxx tDQMD tRASD2
,, ,,,
tAD tAD
Read A command
tAD
tCSD1
tRWD
tCASD2 tDQMD
tRDS2 tRDH2 D31-D0 tBSD BS CKE (High)
tRDS2 tRDH2
tBSD
Figure 16.36
Synchronous DRAM Read Bus Cycle (Burst Read (Single Read x 4), RCD = 0, CAS Latency = 1, TPC = 1)
464
Tr CKIO
Trw
Tc1
Tc2
Tc3 Tc4/Td1 Td2
Td3
Td4
(Tpc)
A25-A16
A12 or A10
A15-A0
CSn
, ,, , ,,
tAD tAD tAD tAD
Row address
Row address
tAD Read command tAD
tAD
Row address
Column address (1-4)
tCSD1
tRWD
,,,, ,,,, ,,, ,,,
tAD tAD tAD tCSD1 tRWD tCASD2 tDQMD tRDS2 tRDH2
RD/WR tRASD2 tRASD2 RAS tCASD2 CAS tDQMD DQMxx tRDS2 tRDH2 D31-D0 tBSD BS CKE (High) tBSD
Figure 16.37
Synchronous DRAM Read Bus Cycle (Burst Read (Single Read x 4), RCD = 1, CAS Latency = 3, TPC = 0)
465
Tr CKIO tAD A25-A16 tAD A12 or A10 tAD A15-A0 tCSD1 CSn tRWD RD/WR tRASD2 RAS tRWD Row address tAD Row address tAD Row address
Tc1
(Trwl)
(Tpc)
tAD
tAD Write A command tAD Column address tCSD1
tRWD
tRASD2
CAS
DQMxx
D31-D0
,,, ,,,
tDQMD tWDD2 tBSD (High)
tCASD2
tCASD2
tDQMD
tWDH2
tBSD
BS CKE
Figure 16.38
Synchronous DRAM Write Bus Cycle (RCD = 0, TPC = 0, TRWL = 0)
466
Tr CKIO tAD A25-A16 tAD A12 or A10 tAD A15-A0
Trw
Trw
Tc1
(Trwl)
(Trwl)
(Tpc)
(Tpc)
tAD Row address tAD
Row address
Row address
tCSD1 CSn tRWD RD/WR tRASD2 RAS CAS
,,, ,,,
tAD tAD tAD tRWD tRASD2
tAD
Write A command
tAD
Column address
tCSD1
tRWD
DQMxx
D3-D0
,,,, ,,,,
tBSD (High)
tCASD2
tCASD2
tDQMD
tDQMD
tWDD2
tWDH2
tBSD
BS CKE
Figure 16.39
Synchronous DRAM Write Bus Cycle (RCD = 2, TPC = 1, TRWL = 1)
467
Tr CKIO tAD A25-A16 tAD A12 or A10 tAD A15-A0
Tc1
Tc2
Tc3
Tc4
(Trwl)
(Tpc)
(Tpc)
tAD Row address tAD
Row address
tAD Write command
tAD
Write A command
tAD
Row address
tAD Column address (1-4) tCSD1
tCSD1 CSn tRWD RD/WR tRASD2 RAS tRASD2 tRWD
tRWD
CAS
DQMxx
D31-D0
,, ,,
tCASD2 tDQMD tWDD2 tBSD (High)
tCASD2
tDQMD
tWDD2
tWDH2
tBSD
BS CKE
Figure 16.40
Synchronous DRAM Write Bus Cycle (Burst Mode (Single Write x 4), RCD = 0, TPC = 1, TRWL = 0)
468
Tr CKIO tAD A25-A16 tAD A12 or A10 tAD A15-A0
Trw
Tc1
Tc2
Tc3
Tc4
(Trwl)
(Tpc)
Row address
tAD
Row address
Row address
tCSD1 CSn tRWD RD/WR
,, ,, ,,
tAD tRWD tCASD2 tDQMD tWDD2
tAD
tAD
tAD
Write command
Write A command
tAD
Column address (1-4)
tCSD1
tRWD
tRASD2 tRASD2 RAS tCASD2
CAS
DQMxx
D31-D0
,,,
tBSD (High)
tDQMD
tWDD2
tWDH2
tBSD
BS CKE
Figure 16.41
Synchronous DRAM Write Bus Cycle (Burst Mode (Single Write x 4), RCD = 1, TPC = 0, TRWL = 0)
469
TRr CKIO
TRrw
TRrw
(Tpc)
(Tpc)
CKE tCSD1 CSn tRASD2 RAS tCASD2 CAS tRWD RD/WR tCASD2 tRASD2 tCSD1
(High)
Figure 16.42
Synchronous DRAM Auto-Refresh Cycle (TRAS = 1, TPC = 1)
470
TRs1 CKIO tCKED CKE tCSD1 CSn tRASD2 RAS tCASD2 CAS tRWD RD/WR
(TRs2)
(TRs2)
TRs3
(Tpc)
(Tpc)
tCKED
tCSD1
tRASD2
tCASD2
tRWD
Figure 16.43
Synchronous DRAM Self-Refresh Cycle (TPC = 0)
471
TRp1
TRp2
TRp3
TRp4
TMw1
TMw2
TMw3
TMw4
CKIO
A13 or A11
A12 or A10
A11-A2 or A9-A2
CSn
,,,,,,, ,,, ,,,,,, , ,,,,,
tAD tAD tAD tAD tAD tAD tAD tAD tAD tAD tAD tCSD1 tRWD tRWD tRASD2 tRASD2 tRASD2 tRASD2
tCSD1
tRWD
RD/WR
RAS
CASxx
D31-D0
CKE
,,,,,,,
(High)
tCASD2
tCASD2
Figure 16.44
Synchronous DRAM Mode Register Write Cycle
472
16.3.8
Pseudo-SRAM Timing
Tr CKIO tAD A25-A0 tRWD tRWS RD/WR tAH tCED CE tAH tOED tOED tRWH tRDH1 tRDS1 D31-D0 (read) tAH tWED WEn (write) tWED tRWH tCED tRWH tRWD tAS tAD Tc1 Tc2 (Tpc)
OE/RFSH (read)
tWDS tWDD2
tWDH3 tWDH1
D31-D0 (write) tBSD BS tBSD
Figure 16.45
Pseudo-SRAM Bus Cycle (RCD = 0, A3W = 1, TPC = 0)
473
Tr CKIO tAD tAS A25-A0 tRWD tRWS RD/WR
Trw
Tc1
Tc1w
Tc1w
Tc2
(Tpc)
tAD
tRWD
tAH tCED tCED tRWH
CE tAH tOED OE/RFSH (read) tRDS1 D31-D0 (read) tAH tWED WEn (write) tWED tRWH tOED tRWH
tRDH1
tWDS tWDD2
tWDH3 tWDH1
D31-D0 (write) tBSD BS tBSD
Figure 16.46
Pseudo-SRAM Read Cycle (RCD = 1, A3W = 3, TPC = 0)
474
Tr CKIO tAD tAS A25-A4
Tc1
Tc2
Tc1
Tc2
Tc1
Tc2
Tc1
Tc2
(Tpc)
tAD
tAD A3-A0 tRWD tRWS RD/WR tAH tCED CE tAH tOED OE/RFSH (read) tRDH1 tRDS1 D31-D0 (read) tAH tWED WEn (write) tWED tAS tWED tWED tRWH tRDS1 tRDH1 tOED tAS tOED tOED tRWH tCED tRWH tRWD
tWDS tWDD2
tWDH3 tWDD2
tWDH3 tWDH1
D31-D0 (write) tBSD BS tBSD tBSD tBSD
Figure 16.47
Pseudo-SRAM Bus Cycle (Static Column Mode, RCD = 0, A3W = 1, TPC = 0)
475
Tr CKIO tAD tAS A25-A4
Trw
Tc1
Tc1w
Tc2
Tc1
Tc1w
Tc2
(Tpc)
(Tpc)
tAD
tAD tAS A3-A0 tRWD tRWS RD/WR tAH tCED CE tAH tOED OE/RFSH (read) tRDH1 tRDS1 D31-D0 (read) tAH tRWH tWED WEn (write) tWDS tWDD2 D31-D0 (write) tBSD BS tBSD tBSD tBSD tWED tWED tWDH3 tWDD2 tWED tWDH3 tWDH1 tRDS1 tRDH1 tOED tOED tOED tRWH tCED tRWH tRWD
Figure 16.48
Pseudo-SRAM Bus Cycle (Static Column Mode, RCD = 1, A3W = 2, TPC = 1)
476
TRc CKIO
TRr1
TRr2
(Tpc)
CE tOED OE/RFSH
(High) tOED
Figure 16.49
TRc CKIO CE
Pseudo-SRAM Auto-Refresh Cycle (TRAS = 1, TPC = 1)
TRr1 TRrw TRrw TRr2 (Tpc) (Tpc)
(High) tOED tOED
OE/RFSH
Figure 16.50
Pseudo-SRAM Auto-Refresh Cycle (TRAS = 2, TPC = 1)
TRc TRr1 TSR TSR2 (Tpc) (Tpc)
CKIO CE OE/RFSH
tOED (High)
tOED
Figure 16.51
Pseudo-SRAM Self-Refresh Cycle (TPC = 0)
477
16.3.9
PCMCIA Timing
Tpcm1
Tpcm2
CKIO tAD A25-A0 tCSD1 CExx tRWD RD/WR tRSD RD (read) tRDS1 D15-D0 (read) tRSD tRWD tCSD1 tAD
tRDH1
WE1 (write)
D15-D0 (write)
tBSD BS
,, ,,
tWED tWDD1
tWED tWDH4 tWDH1
tBSD
Figure 16.52
PCMCIA Memory Bus Cycle (TED = 0, TEH = 0, No Wait)
478
Tpcm0 CKIO tAD A25-A0 tCSD1 CExx tRWD RD/WR
Tpcm0w
Tpcm1
Tpcm1w
Tpcm1w
Tpcm2
Tpcm2w
tAD
tCSD1
tRWD
tRSD RD (read) tRDS1 D15-D0 (read) WE1 (write) D15-D0 (write)
tRSD tRDH1
BS
WAIT
Figure 16.53
,, ,,,,,,,,,
tWED tWED1 tWDD1 tWDH4 tWDH1 tBSD tBSD tWTS tWTH tWTS tWTH
PCMCIA Memory Bus Cycle (TED = 2, TEH = 1, 1 Wait, External Wait)
479
Tpcm1 CKIO tAD A25-A4 tAD A3-A0 tCSD1 CExx tRWD RD/WR tRSD RD (read)
Tpcm2
Tpcm1
Tpcm2
Tpcm1
Tpcm2
Tpcm1
Tpcm2
tAD
tAD
tAD
tAD
tCSD1
tRWD
tRSD
tRSD
tRSD
tRDH1 tRDS1 tRDS1
tRDH1
D15-D0 (read) tBSD BS tBSD tBSD tBSD
Note: Even though burst mode is set, write cycle operation is the same as in normal mode.
Figure 16.54
PCMCIA Memory Bus Cycle (Burst Read, TED = 0, TEH = 0, No Wait)
480
Tpcm0 Tpcm1 Tpcm1w Tpcm1w Tpcm1w Tpcm2 Tpcm1 Tpcm1w Tpcm2 Tpcm2w CKIO tAD A25-A4 tAD A3-A0 tCSD1 CExx tRWD RD/WR tRSD RD (read) tRDS1 D15-D0 (read) tRSD tRSD tRSD tRWD tCSD1 tAD tAD tAD
tRDH1 tRDS1
tRDH1
BS
WAIT
Note: Even though burst mode is set, the write cycle operation is the same as in normal mode.
,,,,,,,,,, ,, ,,, ,,,,,,, ,,
tBSD tBSD tBSD tBSD tWTS tWTH tWTS tWTH tWTS tWTH
Figure 16.55
PCMCIA Memory Bus Cycle (Burst Read, TED = 1, TEH = 1, 2 Waits, Burst Pitch = 3)
481
Tpci1
Tpci2
CKIO tAD A25-A0 tCSD1 CExx tRWD RD/WR tICRSD ICIORD (read) tRDS1 D15-D0 (read) tICWSD ICIOWR (write) tICWSD tICRSD tRWD tCSD1 tAD
tRDH1
D15-D0 (write)
tBSD BS
,, ,,
tWDD1
tWDH4 tWDH1
tBSD
Figure 16.56 PCMCIA I/O Bus Cycle (TED = 0, TEH = 0, No Wait)
482
Tpci0 CKIO tAD A25-A0 tCSD1 CExx tRWD RD/WR
Tpci0w
Tpci1
Tpci1w
Tpci1w
Tpci2
Tpci2w
tAD
tCSD1
tRWD
tICRSD ICIORD (read)
tICRSD
tRDH1 tRDS1 D15-D0 (read) ICIOWR (write) D15-D0 (write)
WAIT
IOIS16
Figure 16.57
,, ,, ,,,,,,,,, ,,,,,, ,,,,,,,,, ,,,, ,,,,,, ,,,,
tICWSD tICWSD tWDH4 tWDD1 tWDH1 tBSD tBSD BS tWTS tWTH tWTS tWTH tIO16S tIO16H
PCMCIA I/O Bus Cycle (TED = 2, TEH = 1, 1 Wait, External Wait)
483
Tpci0 CKIO tAD A25-A4 tAD A0 tCSD1 CExx tRWD RD/WR
Tpci1
Tpci1w
Tpci2
Tpci1
Tpci1w
Tpci2
Tpci2w
tAD
tAD
tAD
tCSD1
tCSD1
tRWD
tICRSD ICIORD (read) tRDS1 D15-D0 (read) ICIOWR (write)
tICRSD
tICRSD
tICRSD
tRDH1 tRDS1
tRDH1
D15-D0 (write)
BS
WAIT
IOIS16
Figure 16.58
484
,, ,, ,,,,,, ,,,, ,,, ,,,,,, ,,,, ,,,,,, ,,,,,,,,,
tICWSD tICWSD tICWSD tICWSD tWDH3 tWDH4 tWDD1 tWDD2 tWDH1 tBSD tBSD tBSD tBSD tWTS tWTH tWTS tWTH tIO16S tIO16H
PCMCIA I/O Bus Cycle (TED = 1, TEH = 1, 1 Wait, Bus Sizing)
16.3.10 Peripheral Module Signal Timing Table 16.11 Peripheral Module Signal Timing (Conditions: VCC = 3.3 0.3 V, Ta = 0 to 75C)
-15 Module I t e m TMU, RTC Timer input setup time -30 -60
Symbol Min M a x Min M a x Min M a x Unit Figure tCLKS1 20 20 1.5 2.5 -- 4 6
t SCKr
-- -- -- -- 3 -- -- 1.5 1.5 0.6 100 -- -- -- 20 -- --
15 15 1.5 2.5 -- 4 6 -- -- 0.4 --
-- -- -- -- 3 -- -- 1.5 1.5 0.6
12 12
-- --
ns ns tcyc tcyc S
Timer clock input setup tCKS time Timer clock;Single edge tTCKWH pulse width;Both edges t TCKWL Oscillation settling time tROSC
16.54, 16.55
1.5 -- 2.5 -- -- 4 6 -- -- 3 -- -- 1.5 1.5
16.61
SCI
Input clock cycle; Asynchronous synchronous Input clock rise time Input clock fall time
tSCYC
tcyc 16.62- 16.64 tcyc tcyc tcyc tscy c
-- -- 0.4 -- 100 100 0 -- 20 10
tSCKf
Input clock pulse width tSCKw Transmit data delay time Receive data setup time (synchronous) tTXD tRXS
0.4 0.6
100 --
100 ns ns ns ns ns ns ns
100 -- 100 -- 0 -- 15 8 -- 17 -- --
100 -- 100 -- 0 -- 12 5 -- 15 -- --
Receive; Clock input tRXH data hold time (syntRXH chronous);Clock output Port Output data delay time tPORTD Input data setup time Input data hold time tPORTS tPORTH
485
CKIO tTCLKS TCLK (input)
Figure 16.59
TCLK Input Timing (1)
tTCKS
CKIO tTCKS TCLK (input) tTCKWL tTCKWH
Figure 16.60
TCLK Input Timing (2)
Stable oscillation
RTC crystal oscillator
VCC
VCCmin
tROSC
Figure 16.61
RTC Crystal Oscillator Power-On Oscillation Settling Time
tSCKW tSCKR tSCKF
SCK tScyc
Figure 16.62
SCK Input Clock Timing
486
tScyc SCK tTXD TxD (data transmission) RxD (data reception)
Figure 16.63
Synchronous Mode SCI Input/Output Timing
,,,
tRXS tRXH tPORTH tPORTD
PORT 7- PORT 0 (read) PORT 7- PORT 0 (write) tPORTS
Figure 16.64
I/O Port Input/Output Timing
16.3.11 AC Characteristics Test Conditions * Input/output signal reference level: 1.5 V (VCC = 3.3 0.3 V). * Input pulse level: VSS to 3.0 V (when RESET, BREQ , NMI, IRL3-IRL0, CKIO, MD5- MD0 are VSS to VCC). * Input rise/fall time: 1 ns
487
IOL
LSI output pin CL
DUT output VREF
IOH Notes: 1. CL is the total capacitance including the test jig probe, as shown below: 2. 30 pF: CKIO, RAS, CASxx, CSO-CS6, CE2A, CE2B, BACK 50 pF: All other pins IOL and IOH are the values shown in table 17.3
Figure 16.65
Output Load Circuit
488
Section 17 Electrical Characteristics (-SH7708R-)
17.1 Absolute Maximum Ratings
Table 17.1 Absolute Maximum Ratings
Item Power supply voltage Input voltage Operating temperature Storage temperature Symbol VCC Vin Topr Tstr Ratings -0.3 to 4.6 -0.3 to VCC + 0.3 -20 to 75 -55 to 125 Units V V C C
Note: Operating the SH7708 Series above maximum ratings can damage or destroy it.
489
17.2
DC Characteristics
Table 17.2 DC Characteristics (Ta = -20 to 75C)
Item Power supply voltage Current Normal operation SymbolMin VCC ICC 3.15 -- Typ 3.3 Max 3.6 UnitRemarks V In normal operation, sleep mode, and standby mode
120*1 200 *1
mA VCC = 3.3 V *1 Io = 100 MHz Bo = 50 MHz
In sleep mode
--
75*
2
100 *
2
*2 Bo = 60 MHz Po = 30 MHz
In standby mode Input voltage RESET, NMI BREQ, IRL3-IRL0, MD5-MD0 EXTAL, CKIO Other input pins RESET, NMI BREQ, IRL3-IRL0, MD5-MD0 Other input pins Input leak All input pins current |lin| VIL VIH
--
0.1*
3
1*
3
mA *3 VCC = 3.3 V/ Ta= 30 C
VCC x 0.9 -- VCC - 0.5 -- VCC - 0.7 -- VCC - 0.7 -- 2.0 -0.3 -0.3 -0.3 -0.3 -- -- -- -- -- -- -- -- --
VCC + 0.3 V VCC + 0.3 VCC + 0.3 VCC + 0.3 VCC + 0.3 VCC x 0.1 0.5 VCC x 0.2 VCC x 0.2 1.0 1.0 A Vin = 0.5 to VCC - 0.5 V A Vin = 0.5 to VCC - 0.5 V Standby mode Normal operation Standby mode Normal operation
ThreeI/O, output, all pins |lsti| state leak (off condition) current
490
Table 17.2 DC Characteristics (Ta = -20 to 75C) (cont)
Item Output voltage All output pins SymbolMin VOH 2.4 2.0 VOL Pull-up Port pins resistance Terminal capacitance All pins Rpull C -- 30 -- Typ -- -- -- 60 -- Max -- -- 0.55 120 20 k pF Unit V Remarks VCC = 3.15 V, IOH = -200 A VCC = 3.15 V, IOH = -2 mA VCC = 3.6 V, IOL = 1.6 mA
Notes: 1. Regardless of whether PLL or RTC is used, connect VCC(PLL), VCC(RTC) to VCC, and VSS(PLL), VSS(RTC) to VSS. 2. Current condition is VIH min = VCC - 0.5 V, VIL max = 0.5 V, and all output pins unloaded.
Table 17.3 Permissible Output Current Values (VCC = 3.3 0.3 V, Ta = -20 to 75C)
Item Permissible output low current (per pin) Permissible output low current (total) Permissible output high current (per pin) Permissible output high current (total) Symbol IOL IOL -IOH (-IOH) Min -- -- -- -- Typ -- -- -- -- Max 2.0 120 2.0 40 Unit mA
Note: To ensure reliability, output current must not exceed the maximum values listed.
17.3
AC Characteristics
Input for the LSI should, as a rule, be clock synchronous. Keep to the setup and hold times for each input signal unless otherwise directed. Table 17.4 LSI Clock Values (Ta = -20 to 75C)
Item Operating frequency CPU, cache, TLB External bus Peripheral modules Symbol f 100 60 33.3 Unit MHz
491
17.3.1
Clock Timing
Table 17.5 Clock Timing (VCC = 3.15A-3.6 V, Ta = -20 to 75C, Maximum External Bus Operating Frequency: 60 MHz)
Item EXTAL clock input frequency EXTAL clock input cycle time EXTAL clock input low-level pulse width EXTAL clock input high-level pulse width EXTAL clock input rise time EXTAL clock input fall time CKIO clock frequency (input) CKIO clock cycle time (input) CKIO clock low-level pulse width (input) CKIO clock high-level pulse width (input) CKIO clock rise time (input) CKIO clock fall time (input) CKIO clock output frequency (output) CKIO clock cycle time (output) CKIO clock low-level pulse width (output) CKIO clock high-level pulse width (output) CKIO clock rise time (output) CKIO clock fall time (output) Power-on oscillation settling time Power-on oscillation settling time/mode setting BREQ reset hold time RESET set-up time BREQ set-up time MD reset hold time Reset assert time Symbol f EX t EXcyc t EXL t EXH t EXR t EXF f CKI t CKIcyc t CKIL t CKIH t CKIR t CKIF f OP t cyc t CKOL t CKOH t CKOR t CKOF t OSC1 t OSCMD t BREQRH t RESS t BREQS t MDRH t RESW Min 5 16.7 4*1 or 10*2 4*1 or 10*2 -- -- 16 16.7 4 4 -- -- 16 16.7 3 3 -- -- 10 10 0 20 20 20 20 Max 60 200 -- -- 2 2 60 62.5 -- -- 2 2 60 62.5 -- -- 5 5 -- -- -- -- -- -- -- Unit MHz ns ns ns ns ns MHz ns ns ns ns ns MHz ns ns ns ns ns ms ms ns ns ns ns tcyc 17.4, 17.5, 17.11 17.5 17.6 17.7 17.8, 17.9, 17.10 17.10 17.4 17.3 17.2 Figure 17.1
Standby return oscillation settling time 1 Standby return oscillation settling time 2 Standby return oscillation settling time 3 PLL synchronization settling time
t OSC2 t OSC3 t OSC4 t PLL
10 10 11 100
-- -- -- --
ms ms ms s
IRL interrupt decision time (using RTC and in standby mode) Notes: 1. PLL circuit 2 in operation.
t IRLSTB
100
--
s
492
2. IPLL circuit 2 not in operation.
tEXcyc EXTAL* (input) 1/2 VCC tEXH tEXL VIH 1/2 VCC tEXR
VIH
VIH VIL tEXF VIL
Note: The clock input from the EXTAL pin.
Figure 17.1
EXTAL Clock Input Timing
tCKIcyc tCKIH tCKIL VIH VIL tCKIF VIH VIL
CKIO (input) 1/2 VCC
VIH
1/2 VCC tCKIR
Figure 17.2
CKIO Clock Input Timing
tcyc tCKOH tCKOL
CKIO (output)
1/2VCC
VIH
VOH VOL tCKOF
VOH VOL
1/2VCC tCKOR
Figure 17.3
CKIO Clock Output Timing
493
CKIO, internal clock VCC
,,, ,,,
VCC min
Stable oscillation
tRESW tOSC1
tRESS
RESET
tBREQS tBREQRH
BREQ tOSCMD tMDRH MD0-MD2
Note: Oscillation settling time when built-in oscillator is used
Figure 17.4
Standby CKIO, internal clock
RES
,, ,,
Power-On Oscillation Settling Time
Stable oscillation
tOSC2
tRESW
Note: Oscillation settling time when built-in oscillator is used
Figure 17.5
Standby Return Oscillation Settling Time (Return by RESET)
494
Standby CKIO, internal clock
,, ,, ,,
Stable oscillation
tOSC3
NMI
Note: Oscillation settling time when built-in oscillator is used
Figure 17.6
Standby CKIO, internal clock
Standby Return Oscillation Settling Time (Return by NMI)
Stable oscillation
tOSC4
IRL3-IRL0
Note: Oscillation settling time when built-in oscillator is used
Figure 17.7
Standby Return Oscillation Settling Time (Return by IRL3-IRL0)
495
Reset or NMI interrupt request Stable input clock EXTAL input or CKIO input PLL synchronization PLL output, CKIO output Stable input clock
tPLL
PLL synchronization
Internal clock
STATUS 0 STATUS 1
Normal
Standby
Normal
Note: PLL oscillation settling time when clock is input from EXTAL pin or CKIO pin
Figure 17.8
PLL Synchronization Settling Time in Case of Reset or NMI Interrupt
IRL (3-0) interrupt request Stable input clock Stable input clock
EXTAL input or CKIO input PLL synchronization PLL output, CKIO output tIRLSTB tPLL PLL synchronization
Internal clock
STATUS 0 STATUS 1
Normal
Standby
Normal
Note: PLL oscillation settling time when clock is input from EXTAL pin or CKIO pin
Figure 17.9
PLL Synchronization Settling Time in Case of IRL Interrupt
496
EXTAL input or on-chip oscillator output CKOEN
CKIO PLL synchronization PLL1 output tPLL PLL synchronization tPLL PLL synchronization
Internal clock
Note: PLL oscillation settling time when output clock is controlled by Clock Mode 0-2
Figure 17.10
PLL Synchronization Settling Time in Case of CKOEN Bit Manipulation
497
17.3.2
Control Signal Timing
Table 17.6 Control Signal Timing (VCC = 3.15-3.6 V, Ta = -20 to + 75C)
-60*2 Item RESET pulse width RESET setup time RESET hold time BREQ setup time BREQ hold time BREQ reset setup time BREQ reset hold time MD reset setup time MD reset hold time NMI setup time*1 time*1 Symbol tRESW tRESS tRESH tBREQS tBREQH tBREQRS tBREQRH tMDRS tMDRH tNMIS tIRLS tNMIH tIRLH tIRQOD tBACKD tSTD tBOFF1 tBOFF2 tBON1 tBON2 Min 20 23 2 12 3 17 16 20 16 15 10 4 4 -- -- -- 0 0 0 0 Max -- -- -- -- -- -- -- -- -- -- -- -- -- 12 12 16 16 16 16 16 Unit tcyc ns ns ns ns ns ns tcyc ns ns ns ns ns ns ns ns ns ns ns ns 17.15, 17.16 17.13, 17.14 17.12 Figure 17.11, 17.13, 17.15
IRL3 -IRL0 setup NMI hold time
IRL3 -IRL0 hold time IRQOUT delay time BACK delay time STATUS1, STATUS0 delay time Bus tri-state delay time 1 Bus tri-state delay time 2 Bus buffer on time 1 Bus buffer on time 2
Notes: 1. RESET, NMI, and IRL3 to IRL0 are asynchronous. Changes are detected at the clock fall when the setup shown is used. When the setup cannot be used, detection can be delayed until the next clock fall. 2. Upper limit of external bus clock is 60 MHz.
498
CKIO tRESS tRESW RESET tBREQRS tBREQS tBREQRH tRESS
BREQ
Figure 17.11
Manual Reset Input Timing
RESET tMDRS tMDRH
MD0-MD5
Figure 17.12
Mode Input Timing
499
CKIO tRESH RESET tNMIH NMI tIRLH IRL3-IRL0 tRESS VIH VIL tNMIS VIH VIL tIRLS VIH VIL
Figure 17.13
Interrupt Signal Input Timing
CKIO tIRQOD tIRQOD
IRQOUT
Figure 17.14 IRQOUT Timing
500
CKIO tBREQH tBREQS BREQ tBACKD BACK RD, RD/WR, RAS, CAS, CSn, WEn, BS A25-A0, D31-D0 tBOFF2 tBON2 tBACKD tBREQH tBREQS
tBOFF1
tBON1
Figure 17.15
Bus Release Timing
501
Normal mode
Standby mode
Normal mode
CKIO tSTD STATUS 0 STATUS 1 tBOFF2 RD, RD/WR, RAS, CAS, CSn, WEn, BS A25-A0, D31-D0 tBON2 tSTD
tBOFF1
tBON1
Figure 17.16
Pin Drive Timing for Standby Mode
502
17.3.3
AC Bus Timing Specifications
Table 17.7 Bus Timing (Conditions: Clock Mode 0/1/2/7, VCC = 3.15-3.6 V, Ta = -20 to 75C)
-60*1 Item Address delay time Address setup time Address hold time BS delay time CS delay time 1 CS delay time 2 Read write delay time Read write setup time Read write hold time Read strobe delay time Read data setup time 1 Read data setup time 2 Read data hold time 1 Read data hold time 2 Write enable delay time Write data delay time 1 Write data delay time 2 Write data setup time Write data hold time 1 Write data hold time 2 Write data hold time 3 Write data hold time 4 WAIT setup time* WAIT hold time*
2 2
Symbol tAD tAS tAH tBSD tCSD1
t CSD2
Min 1.5 0 0 -- 1.5 -- 1.5 0 0 -- 12 8 0 3 -- -- -- 0 0 1.5 0 0 12 4
Max 13 -- -- 12 12 12 12 -- -- 12 -- -- -- -- 12 15 13 -- -- -- -- -- -- --
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Figure 17.17-17.58
tRWD tRWS tRWH tRSD tRDS1 tRDS2 tRDH1 tRDH2 tWED tWDD1 tWDD2 tWDS tWDH1 tWDH2 tWDH3 tWDH4 tWTS tWTH
503
Table 17.7 Bus Timing (Conditions: Clock Mode 0/1/2/7, VCC = 3.15-3.6 V, Ta = -20 to 75C) (cont)
-60*1 Item RAS delay time 1 RAS delay time 2 CAS delay time 1 CAS delay time 2 DQM delay time CKE delay time CE delay time OE, RFSH delay time ICIORD delay time ICIOWR delay time IOIS16 setup time IOIS16 hold time Symbol tRASD1 tRASD2 tCASD1 tCASD2 tDQMD tCKED tCED tOED tICRSD tICWSD tIO16S tIO16H Min -- 1.5 -- 1.5 1.5 -- -- -- -- -- 12 4 Max 13 13 13 13 12 12 13 13 12 12 -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns 17.56-17.58 17.45-17.51 Figure 17.23-17.44
Notes 1. Upper limit of external bus clock is 60 MHz. 2. WAIT is a synchronous signal. Operation cannot be guaranteed if the setup and hold times shown here are not observed.
504
Table 17.8 Bus Timing (Conditions: Clock Mode 3/4, VCC = 3.15-3.6 V, Ta = -20 to 75C)
Item Address delay time Address setup time Address hold time BS delay time CS delay time 1 CS delay time 2 Read write delay time Read write setup time Read write hold time Read strobe delay time Read data setup time 1 Read data setup time 2 Read data hold time 1 Read data hold time 2 Write enable delay time Write data delay time 1 Write data delay time 2 Write data setup time Write data hold time 1 Write data hold time 2 Write data hold time 3 Write data hold time 4 WAIT setup time WAIT hold time Symbol tAD tAS tAH tBSD tCSD1
t CSD2
Min 1.5 0 20 -- 1.5 -- 1.5 0 0 -- 12 12 0 8 -- -- -- 0 0 1.5 0 0 12 8
Max 20 -- -- 19 19 20 19 -- -- 20 -- -- -- -- 20 25 19 -- -- -- -- -- -- --
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Figure 17.17-17.58
tRWD tRWS tRWH tRSD tRDS1 tRDS2 tRDH1 tRDH2 tWED tWDD1 tWDD2 tWDS tWDH1 tWDH2 tWDH3 tWDH4 tWTS tWTH
505
Table 17.8 Bus Timing (Conditions: Clock Mode 3/4, VCC = 3.15-3.6 V, Ta = -20 to 75C) (cont)
Item RAS delay time 1 RAS delay time 2 CAS delay time 1 CAS delay time 2 DQM delay time CKE delay time CE delay time OE, RFSH delay time ICIORD delay time ICIOWR delay time IOIS16 setup time IOIS16 hold time Symbol tRASD1 tRASD2 tCASD1 tCASD2 tDQMD tCKED tCED tOED tICRSD tICWSD tIO16S tIO16H Min -- 1.5 -- 1.5 1.5 -- -- -- -- -- 12 8 Max 20 19 20 19 19 19 20 20 20 20 -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns 17.56-17.58 17.45-17.51 Figure 17.23-17.44
506
17.3.4
Basic Timing
T1 CKIO tAD A25-A0
T2
tAD
tAH tCSD1 CSn tRWD RD/WR tAH tRSD RD (read) tRDS1 D31-D0 (read) tAH tWED WEn (write) tWED tRWH tWDH3 tWDH1 tRSD tRWH tRDH1 tRWD tCSD2 tRWH
tRDH1
D31-D0 (write)
BS
,, ,
tWDD1 tBSD
tBSD
Figure 17.17 Basic Bus Cycle (No Wait)
507
T1
Tw
T2
CKIO tAD A25-A0 tAH tCSD1 CSn tRWD RD/WR tAH tRSD1 RD (read) tRDS1 D31-D0 (read) tWED1 WEn (write) tWED tAH tRWH tWDH3 tRSD tRWH tRDH1 tRWD tCSD2 tRWH tAD
tRDH1
D31-D0 (write)
WAIT
508
,, ,,,,,,,,, ,,,,,,,,,
tWDD1 tWDH1 tBSD tBSD BS tWTS tWTH
Figure 17.18
Basic Bus Cycle (1 Wait)
T1
Tw
Tw
T2
CKIO tAD A25-A0 tAH tCSD1 CSn tRWD RD/WR tAH tRSD RD (read) tRDS1 D31-D0 (read) tAH tWED WEn (write) tWED tRWH tWDH3 tRSD tRWH tRDH1 tRWD tCSD2 tRWH tAD
tRDH1
D31-D0 (write)
BS
WAIT
,, ,,,,,,,,, ,,,,,,,,,
tWDD1 tWDH1 tBSD tBSD tWTS tWTH tWTS tWTH
Figure 17.19
Basic Bus Cycle (External Wait)
509
17.3.5
Burst ROM Timing
T1
TB2
TB1
TB2
TB1
TB2
TB1
T2
CKIO tAD A25-A4 tAD A3-A0 tAH tCSD1 CSn tRDH1 tRWD RD/WE tRSD RD tRSD tAH tRSD tRWD tAH tRSD tRWH tCSD2 tRWH tAD tAD
D31-D0
WAIT
Note: In the write cycle, the basic bus cycle is performed.
,,,,,, ,,,,,, ,,,, ,,, ,,, ,, ,,,, ,,, ,,, ,,
tRDH1 tRDH1 tRDS tRDS1 tBSD tBSD tBSD tBSD BS tWTS tWTH
Figure 17.20 Burst ROM Bus Cycle (No Wait)
510
T1
Tw
Tw
TB2
TB1
Tw
TB2
T2
T2
CKIO tAD A25-A4 tAD A3-A0 tAH tCSD1 CSn tRDH1 tRWD RD/WE tRSD RD tRDH1 tRDS1 D31-D0 tBSD BS tBSD tBSD tBSD tRDS1 tRDH1 tRDH1 tRSD tAH tRSD tRSD tRSD tRWD tCSD2 tRWH tAD
tAH tRWH
,,,,,,,,,, ,,
tWTS tWTH tWTS tWTH tWTS tWTH tWTS tWTH WAIT Note: In the write cycle, the basic bus cycle is performed.
Figure 17.21 Burst ROM Bus Cycle (2 Waits)
511
T1 CKIO tAD A25-A4
Tw
Tw
TB2
TB1
TBw
T2
tAD
tAD A3-A0 tAH tCSD1 CSn tRDH1 tRWD RD/WE tRSD tRSD1 tAH tRSD1 tAH tRSD tRWH tRWD tCSD2 tRWH
D31 to D0
WAIT
Note: In the write cycle, the basic bus cycle is performed.
,,, ,,, ,,,,,,,, ,, ,,
RD tRDH1 tRDH1 tRDS1 tRDS tBSD tBSD tBSD tBSD BS tWTS tWTH tWTS tWTH tWTS tWTH tWTS tWTH
Figure 17.22
Burst ROM Bus Cycle (External Wait Input)
512
17.3.6
DRAM Timing
Tr Tc1 Tc2 (Tpc)
CKIO tAD A25 to A16 tAD A15 to A0 tRWD RD/WR tAH tRASD1 RAS tCASD1 CASxx tWDS tRDS1 D31-D0 (read) tWDH3 tWDD2 D31-D0 (write) tBSD BS tBSD tWDH1 tRDH1 tCASD1 tRASD1 tRWH Row address tAS tAD tAS Column address tRWD tAD
Row address tAH
tAH tRWH
tCSD1
tCSD1
CS2 or CS3
Figure 17.23 DRAM Bus Cycle (RCD = 0, AnW = 1, TPC = 0)
513
Tr CKIO tAD A25 to A16 tAD tAS A15 to A0 tRWD RD/WR
Trw
Trw
Tc1
Tcw
Tc2
(Tpc)
(Tpc)
tAD Row address tAD tAS Row address tAH Column address tRWD
tAH tRASD1 RAS tAH tCASD1 CASxx tWDS tRDS1 D31-D0 (read) tWDD2 D31-D0 (write) tBSD BS tCSD1 tBSD tCSD1 tWDH3 tWDH1 tRDH1 tCASD1 tRWH tRASD1 tRWH
CS2 or CS3
Figure 17.24 DRAM Bus Cycle (RCD = 2, AnW = 2, TPC = 1)
514
Tr CKIO tAD A25-A16
Tc1
Tc2
Tc1
Tc2
Tc1
Tc2
Tc1
Tc2
(Tpc)
tAD Row address
tAD tAS tAD tAS A15-A0 tRWD RD/WR
Row address
tAD
Column address Column address Column address Column address
tAH
tRWD
tAH tRASD1 RAS tAH tCASD1 CASxx tWDS tRDS1 D31-D0 (read) tWDH3 tWDD2 D31-D0 (write) tWDD2 tWDH3 tWDH1 tCASD1 tCASD1 tCASD1 tRWH tRASD1 tRWH
tRDH1
tRDS1
tRDH1
tBSD
tBSD
BS tCSD1 tCSD1
CS2 or CS3
Figure 17.25 DRAM Burst Bus Cycle (RCD = 0, AnW = 1, TPC = 0)
515
Tr
Trw
Trw
Tc1
Tcw
Tc2
Tc1
Tcw
Tc2
(Tpc)
CKIO tAD A25-A16 tAD Row address tAS tAD tAS tAD Column address tRWD RD/WR tAH tRASD1 RAS tCASD1 tCASD1 tCASD1 CASxx tWDS tRDH1 tRDS1 D31-D0 (read) tWDD2 D31-D0 (write) tBSD BS tCSD1 CS2 or CS3 tCSD1 tBSD tWDH3 tWDD2 tWDH3 tWDH1 tRDS1 tRDH1 tRASD1 tAH tRWH tRWH tAD
A15-A0
Row address tRWD tAH
Column address
Figure 17.26 DRAM Burst Bus Cycle (RCD = 2, AnW = 2, TPC = 0)
516
Tr
Tc1
Tc2
(Tpc)
CKIO tAD A25-A16 tAD A15-A0 tRWD RD/WR tRASD1 tRASD2 Row address tAS tAD tAS Column address tRWH tRWD tAH tAD
Row address tAH
RAS tCASD1 CASxx tWDS tRDS2 tRDH2 tCASD1
D31-D0 (read) tWDD2 D31-D0 (write) tBSD BS tCSD1 CS2 or CS3 tCSD1 tBSD tWDH3 tWDH1
Figure 17.27 DRAM Bus Cycle (EDO Mode, RCD = 0, AnW = 1, TPC = 0)
517
Tr
Trw
Trw
Tc1
Tcw
Tc2
(Tpc)
(Tpc)
CKIO tAD A25-A16 Row address tAD tAS A15-A0 tRWD RD/WR tRASD1 RAS tCASD1 CASxx tWDS D31-D0 (read) tWDD2 D31-D0 (write) tBSD BS tCSD1 CS2 or CS3 tCSD1 tBSD tWDH3 tWDH1 tRDS2 tRDH2 tCASD1 tRASD2 Row address tAH tAD tAS Column address tRWH tRWD tAH tAD
Figure 17.28 DRAM Bus Cycle (EDO Mode, RCD = 2, AnW = 2, TPC = 1)
518
Tr
Tc1
Tc2
Tc1
Tc2
Tc1
Tc2
Tc1
Tc2
(Tpc)
CKIO tAD A25-A16 tAD A15-A0 Row address tAS tAD tAS Row address tRWD tAH RD/WR tRASD1 RAS tCASD1 tCASD1 CASxx tWDS D31-D0 (read) tWDD2 D31-D0 (write) tBSD BS tCSD1 CS2 or CS3 tCSD1 tBSD tWDH3 tWDD2 tWDH3 tWDH1 tRDS2 tRDH2 tRDS2 tRDH2 tCASD1 tCASD1 tRASD2 Column address tAH tAD Column address Column address Column address tRWH tRWD tAD
tAH
Figure 17.29 DRAM Burst Bus Cycle (EDO Mode, RCD = 0, AnW = 1, TPC = 0)
519
Tr
Trw
Trw
Tc1
Tcw
Tc2
Tc1
Tcw
Tc2
(Tpc)
CKIO tAD A25-A16 Row address tAD tAS A15-A0 tRWD RD/WR tRASD1 RAS tCASD1 CASxx tWDS D31-D0 (read) tWDD2 D31-D0 (write) tBSD BS tCSD1 CS2 or CS3 tCSD1 tBSD tWDH3 tWDD2 tWDH3 tWDH1 tRDS2 tRDH2 tRDS2 tRDH2 tCASD1 tCASD1 tRASD2 Row address tAH tAD tAS Column address tAD tAH Column address tAH tRWH tRWD tAD
Figure 17.30 DRAM Burst Bus Cycle (EDO Mode, RCD = 2, AnW = 2, TPC = 0)
520
TRc
TRr1
TRrw
TRr2
(Tpc)
CKIO tRASD1 tRASD1
RAS tCASD1 tCASD1
CASxx tRWD RD/WR (High) CS2 or CS3
Figure 17.31 DRAM CAS-Before-RAS Refresh Cycle (TRAS = 0, TPC = 0)
TRc TRr1 TRrw TRrw TRrw TRrw TRr2 (Tpc) (Tpc) (Tpc)
CKIO tRASD1 RAS tCASD1 tCASD1 tRASD1
CASxx tRWD RD/WR
CS2 or CS3
(High)
Figure 17.32 DRAM CAS-Before-RAS Refresh Cycle (TRAS = 3, TPC = 2)
521
TRc
TRr1
TRrw
TSR1
TSR1
TSR2
(Tpc)
(Tpc)
CKIO tRASD1 RAS tCASD1 tCASD1 tRASD1
CASxx tRWD RD/WR
CS2 or CS3
(High)
Figure 17.33 DRAM Self-Refresh Cycle (TPC = 0)
522
17.3.7
Synchronous DRAM Timing
Tr CKIO tAD A25-A16 tAD A12 or A10 tAD A15-A0 tCSD1 CSn tRWD RD/WR tRASD2 RAS
Tc1
Tc2
(Tpc)
Row address tAD
Row Read A address command tAD Row address
Column address
,,, ,,,
tAD tAD tCSD1 tRWD tCASD2 tDQMD tRDS2 tRDH2
tAD
tRASD2
tCASD2 CAS DQMxx tDQMD
D31-D0 tBSD BS tBSD
CKE
(High)
Figure 17.34
Synchronous DRAM Read Bus Cycle (RCD = 0, CAS Latency = 1, TPC = 0)
523
Tr CKIO tAD A25-A16 tAD A12 or A10 tAD A15-A0
Trw
Trw
Tc1
Tcw
Td1
(Tpc)
(Tpc)
Row address
tAD Row address
tAD Row address
,,,
tAD
Read A command
tAD
tAD
Column address
tCSD1 CSn tRWD RD/WR tRASD2 RAS tCASD2 CAS tDQMD DQMxx tCASD2 tRASD2
tCSD1
tRWD
tDQMD
tRDS2 tRDH2 D31-D0 tBSD BS CKE (High) tBSD
Figure 17.35
Synchronous DRAM Read Bus Cycle (RCD = 2, CAS Latency = 2, TPC = 1)
524
Tr CKIO tAD A25-A16 tAD A12 or A10 tAD A15-A0
Tc1
Tc2/Td1 Tc3/Td2 Tc4/Td3
Td4
(Tpc)
(Tpc)
tAD Row address tAD
Row address
Read command
tAD
Row address
Column address (1-4)
tCSD1 CSn tRWD RD/WR tRASD2 RAS tCASD2 CAS DQMxx tDQMD tRASD2
,, ,,,
tAD tAD
Read A command
tAD
tCSD1
tRWD
tCASD2 tDQMD
tRDS2 tRDH2 D31-D0 tBSD BS CKE (High)
tRDS2 tRDH2
tBSD
Figure 17.36
Synchronous DRAM Read Bus Cycle (Burst Read (Single Read x 4), RCD = 0, CAS Latency = 1, TPC = 1)
525
Tr CKIO
Trw
Tc1
Tc2
Tc3 Tc4/Td1 Td2
Td3
Td4
(Tpc)
A25-A16
A12 or A10
A15-A0
CSn
, ,, , ,,
tAD tAD tAD tAD
Row address
Row address
tAD Read command tAD
tAD
Row address
Column address (1-4)
tCSD1
tRWD
,,,, ,,,, ,,, ,,,
tAD tAD tAD tCSD1 tRWD tCASD2 tDQMD tRDS2 tRDH2
RD/WR tRASD2 tRASD2 RAS tCASD2 CAS tDQMD DQMxx tRDS2 tRDH2 D31-D0 tBSD BS CKE (High) tBSD
Figure 17.37
Synchronous DRAM Read Bus Cycle (Burst Read (Single Read x 4), RCD = 1, CAS Latency = 3, TPC = 0)
526
Tr CKIO tAD A25-A16 tAD A12 or A10 tAD A15-A0 tCSD1 CSn tRWD RD/WR tRASD2 RAS tRWD Row address tAD Row address tAD Row address
Tc1
(Trwl)
(Tpc)
tAD
tAD Write A command tAD Column address tCSD1
tRWD
tRASD2
CAS
DQMxx
D31-D0
,,, ,,,
tDQMD tWDD2 tBSD (High)
tCASD2
tCASD2
tDQMD
tWDH2
tBSD
BS CKE
Figure 17.38
Synchronous DRAM Write Bus Cycle (RCD = 0, TPC = 0, TRWL = 0)
527
Tr CKIO tAD A25-A16 tAD A12 or A10 tAD A15-A0
Trw
Trw
Tc1
(Trwl)
(Trwl)
(Tpc)
(Tpc)
tAD Row address tAD
Row address
Row address
tCSD1 CSn tRWD RD/WR tRASD2 RAS CAS
,,, ,,,
tAD tAD tAD tRWD tRASD2
tAD
Write A command
tAD
Column address
tCSD1
tRWD
DQMxx
D3-D0
,,,, ,,,,
tBSD (High)
tCASD2
tCASD2
tDQMD
tDQMD
tWDD2
tWDH2
tBSD
BS CKE
Figure 17.39
Synchronous DRAM Write Bus Cycle (RCD = 2, TPC = 1, TRWL = 1)
528
Tr CKIO tAD A25-A16 tAD A12 or A10 tAD A15-A0
Tc1
Tc2
Tc3
Tc4
(Trwl)
(Tpc)
(Tpc)
tAD Row address tAD
Row address
tAD Write command
tAD
Write A command
tAD
Row address
tAD Column address (1-4) tCSD1
tCSD1 CSn tRWD RD/WR tRASD2 RAS tRASD2 tRWD
tRWD
CAS
DQMxx
D31-D0
,, ,,
tCASD2 tDQMD tWDD2 tBSD (High)
tCASD2
tDQMD
tWDD2
tWDH2
tBSD
BS CKE
Figure 17.40
Synchronous DRAM Write Bus Cycle (Burst Mode (Single Write x 4), RCD = 0, TPC = 1, TRWL = 0)
529
Tr CKIO tAD A25-A16 tAD A12 or A10 tAD A15-A0
Trw
Tc1
Tc2
Tc3
Tc4
(Trwl)
(Tpc)
Row address
tAD
Row address
Row address
tCSD1 CSn tRWD RD/WR
,, ,, ,,
tAD tRWD tCASD2 tDQMD tWDD2
tAD
tAD
tAD
Write command
Write A command
tAD
Column address (1-4)
tCSD1
tRWD
tRASD2 tRASD2 RAS tCASD2
CAS
DQMxx
D31-D0
,,,
tBSD (High)
tDQMD
tWDD2
tWDH2
tBSD
BS CKE
Figure 17.41
Synchronous DRAM Write Bus Cycle (Burst Mode (Single Write x 4), RCD = 1, TPC = 0, TRWL = 0)
530
TRr CKIO
TRrw
TRrw
(Tpc)
(Tpc)
CKE tCSD1 CSn tRASD2 RAS tCASD2 CAS tRWD RD/WR tCASD2 tRASD2 tCSD1
(High)
Figure 17.42
Synchronous DRAM Auto-Refresh Cycle (TRAS = 1, TPC = 1)
531
TRs1 CKIO tCKED CKE tCSD1 CSn tRASD2 RAS tCASD2 CAS tRWD RD/WR
(TRs2)
(TRs2)
TRs3
(Tpc)
(Tpc)
tCKED
tCSD1
tRASD2
tCASD2
tRWD
Figure 17.43
Synchronous DRAM Self-Refresh Cycle (TPC = 0)
532
TRp1
TRp2
TRp3
TRp4
TMw1
TMw2
TMw3
TMw4
CKIO
A13 or A11
A12 or A10
A11-A2 or A9-A2
CSn
,,,,,,, ,,, ,,,,,, , ,,,,,
tAD tAD tAD tAD tAD tAD tAD tAD tAD tAD tAD tCSD1 tRWD tRWD tRASD2 tRASD2 tRASD2 tRASD2
tCSD1
tRWD
RD/WR
RAS
CASxx
D31-D0
CKE
,,,,,,,
(High)
tCASD2
tCASD2
Figure 17.44
Synchronous DRAM Mode Register Write Cycle
533
17.3.8
Pseudo-SRAM Timing
Tr CKIO tAD A25-A0 tRWD tRWS RD/WR tAH tCED CE tAH tOED tOED tRWH tRDH1 tRDS1 D31-D0 (read) tAH tWED WEn (write) tWED tRWH tCED tRWH tRWD tAS tAD Tc1 Tc2 (Tpc)
OE/RFSH (read)
tWDS tWDD2
tWDH3 tWDH1
D31-D0 (write) tBSD BS tBSD
Figure 17.45 Pseudo-SRAM Bus Cycle (RCD = 0, A3W = 1, TPC = 0)
534
Tr CKIO tAD tAS A25-A0 tRWD tRWS RD/WR
Trw
Tc1
Tc1w
Tc1w
Tc2
(Tpc)
tAD
tRWD
tAH tCED tCED tRWH
CE tAH tOED OE/RFSH (read) tRDS1 D31-D0 (read) tAH tWED WEn (write) tWED tRWH tOED tRWH
tRDH1
tWDS tWDD2
tWDH3 tWDH1
D31-D0 (write) tBSD BS tBSD
Figure 17.46 Pseudo-SRAM Read Cycle (RCD = 1, A3W = 3, TPC = 0)
535
Tr CKIO tAD tAS A25-A4
Tc1
Tc2
Tc1
Tc2
Tc1
Tc2
Tc1
Tc2
(Tpc)
tAD
tAD A3-A0 tRWD tRWS RD/WR tAH tCED CE tAH tOED OE/RFSH (read) tRDH1 tRDS1 D31-D0 (read) tAH tWED WEn (write) tWED tAS tWED tWED tRWH tRDS1 tRDH1 tOED tAS tOED tOED tRWH tCED tRWH tRWD
tWDS tWDD2
tWDH3 tWDD2
tWDH3 tWDH1
D31-D0 (write) tBSD BS tBSD tBSD tBSD
Figure 17.47
Pseudo-SRAM Bus Cycle (Static Column Mode, RCD = 0, A3W = 1, TPC = 0)
536
Tr CKIO tAD tAS A25-A4
Trw
Tc1
Tc1w
Tc2
Tc1
Tc1w
Tc2
(Tpc)
(Tpc)
tAD
tAD tAS A3-A0 tRWD tRWS RD/WR tAH tCED CE tAH tOED OE/RFSH (read) tRDH1 tRDS1 D31-D0 (read) tAH tRWH tWED WEn (write) tWDS tWDD2 D31-D0 (write) tBSD BS tBSD tBSD tBSD tWED tWED tWDH3 tWDD2 tWED tWDH3 tWDH1 tRDS1 tRDH1 tOED tOED tOED tRWH tCED tRWH tRWD
Figure 17.48
Pseudo-SRAM Bus Cycle (Static Column Mode, RCD = 1, A3W = 2, TPC = 1)
537
TRc CKIO
TRr1
TRr2
(Tpc)
CE tOED OE/RFSH
(High) tOED
Figure 17.49 Pseudo-SRAM Auto-Refresh Cycle (TRAS = 1, TPC = 1)
TRc CKIO CE tOED OE/RFSH TRr1 TRrw TRrw TRr2 (Tpc) (Tpc)
(High) tOED
Figure 17.50
Pseudo-SRAM Auto-Refresh Cycle (TRAS = 2, TPC = 1)
TRc TRr1 TSR TSR2 (Tpc) (Tpc)
CKIO CE OE/RFSH
tOED (High)
tOED
Figure 17.51
Pseudo-SRAM Self-Refresh Cycle (TPC = 0)
538
17.3.9
PCMCIA Timing
Tpcm1
Tpcm2
CKIO tAD A25-A0 tCSD1 CExx tRWD RD/WR tRSD RD (read) tRDS1 D15-D0 (read) tRSD tRWD tCSD1 tAD
tRDH1
WE1 (write)
D15-D0 (write)
tBSD BS
,, ,,
tWED tWDD1
tWED tWDH4 tWDH1
tBSD
Figure 17.52
PCMCIA Memory Bus Cycle (TED = 0, TEH = 0, No Wait)
539
Tpcm0 CKIO tAD A25-A0 tCSD1 CExx tRWD RD/WR
Tpcm0w
Tpcm1
Tpcm1w
Tpcm1w
Tpcm2
Tpcm2w
tAD
tCSD1
tRWD
tRSD RD (read) tRDS1 D15-D0 (read) WE1 (write) D15-D0 (write)
tRSD tRDH1
BS
WAIT
Figure 17.53
,, ,,,,,,,,,
tWED tWED1 tWDD1 tWDH4 tWDH1 tBSD tBSD tWTS tWTH tWTS tWTH
PCMCIA Memory Bus Cycle (TED = 2, TEH = 1, 1 Wait, External Wait)
540
Tpcm1 CKIO tAD A25-A4 tAD A3-A0 tCSD1 CExx tRWD RD/WR tRSD RD (read)
Tpcm2
Tpcm1
Tpcm2
Tpcm1
Tpcm2
Tpcm1
Tpcm2
tAD
tAD
tAD
tAD
tCSD1
tRWD
tRSD
tRSD
tRSD
tRDH1 tRDS1 tRDS1
tRDH1
D15-D0 (read) tBSD BS tBSD tBSD tBSD
Note: Even though burst mode is set, write cycle operation is the same as in normal mode.
Figure 17.54
PCMCIA Memory Bus Cycle (Burst Read, TED = 0, TEH = 0, No Wait)
541
Tpcm0 Tpcm1 Tpcm1w Tpcm1w Tpcm1w Tpcm2 Tpcm1 Tpcm1w Tpcm2 Tpcm2w CKIO tAD A25-A4 tAD A3-A0 tCSD1 CExx tRWD RD/WR tRSD RD (read) tRDS1 D15-D0 (read) tRSD tRSD tRSD tRWD tCSD1 tAD tAD tAD
tRDH1 tRDS1
tRDH1
BS
WAIT
Note: Even though burst mode is set, the write cycle operation is the same as in normal mode.
,,,,,,,,,, ,, ,,, ,,,,,,, ,,
tBSD tBSD tBSD tBSD tWTS tWTH tWTS tWTH tWTS tWTH
Figure 17.55
PCMCIA Memory Bus Cycle (Burst Read, TED = 1, TEH = 1, 2 Waits, Burst Pitch = 3)
542
Tpci1
Tpci2
CKIO tAD A25-A0 tCSD1 CExx tRWD RD/WR tICRSD ICIORD (read) tRDS1 D15-D0 (read) tICWSD ICIOWR (write) tICWSD tICRSD tRWD tCSD1 tAD
tRDH1
D15-D0 (write)
tBSD BS
,, ,,
tWDD1
tWDH4 tWDH1
tBSD
Figure 17.56 PCMCIA I/O Bus Cycle (TED = 0, TEH = 0, No Wait)
543
Tpci0 CKIO tAD A25-A0 tCSD1 CExx tRWD RD/WR
Tpci0w
Tpci1
Tpci1w
Tpci1w
Tpci2
Tpci2w
tAD
tCSD1
tRWD
tICRSD ICIORD (read)
tICRSD
tRDH1 tRDS1 D15-D0 (read) ICIOWR (write) D15-D0 (write)
WAIT
IOIS16
Figure 17.57 PCMCIA I/O Bus Cycle (TED = 2, TEH = 1, 1 Wait, External Wait)
,, ,, ,,,,,,,,, ,,,,,, ,,,,,,,,, ,,,, ,,,,,, ,,,,
tICWSD tICWSD tWDH4 tWDD1 tWDH1 tBSD tBSD BS tWTS tWTH tWTS tWTH tIO16S tIO16H
544
Tpci0 CKIO tAD A25-A4 tAD A0 tCSD1 CExx tRWD RD/WR
Tpci1
Tpci1w
Tpci2
Tpci1
Tpci1w
Tpci2
Tpci2w
tAD
tAD
tAD
tCSD1
tCSD1
tRWD
tICRSD ICIORD (read) tRDS1 D15-D0 (read) ICIOWR (write)
tICRSD
tICRSD
tICRSD
tRDH1 tRDS1
tRDH1
D15-D0 (write)
BS
WAIT
IOIS16
Figure 17.58
,, ,, ,,,,,, ,,,, ,,, ,,,,,, ,,,, ,,,,,, ,,,,,,,,,
tICWSD tICWSD tICWSD tICWSD tWDH3 tWDH4 tWDD1 tWDD2 tWDH1 tBSD tBSD tBSD tBSD tWTS tWTH tWTS tWTH tIO16S tIO16H
PCMCIA I/O Bus Cycle (TED = 1, TEH = 1, 1 Wait, Bus Sizing)
545
17.3.10 Peripheral Module Signal Timing Table 17.9 Peripheral Module Signal Timing (Conditions: V CC = 3.15-3.6 V, Ta = -20 to 75C)
-60 Module I t e m TMU, RTC Timer input setup time Symbol tCLKS tTCKWH tTCKWL tROSC Min 12 12 1.5 2.5 -- 4 6
t SCKr
M a x Unit Figure -- -- -- -- 3 -- -- 1.5 1.5 0.6 100 -- -- 15 -- -- ns ns tcyc tcyc S tcyc tcyc tcyc tcyc tscyc ns ns ns ns ns ns 17.64 17.63 17.62 17.61 17.62-17.63 17.59 17.60
Timer clock input setup time tCKS Timer clock pulse width Single edge Both edges
Oscillation settling time SCI Input clock cycle
Asynchronous tSCYC synchronous
Input clock rise time Input clock fall time Input clock pulse width Transmit data delay time Receive data setup time (synchronous) Receive data hold time (synchronous) Port Output data delay time Input data setup time Input data hold time
-- -- 0.4 -- 100 100 -- 12 5
tSCKf tSCKw tTXD tRXS tRXH tPORTD tPORTS tPORTH
546
CKIO tTCLKS TCLK (input)
Figure 17.59
TCLK Input Timing (1)
tTCKS
CKIO tTCKS TCLK (input) tTCKWL tTCKWH
Figure 17.60
TCLK Input Timing (2)
Stable oscillation
RTC crystal oscillator
VCC
VCCmin
tROSC
Figure 17.61
RTC Crystal Oscillator Power-On Oscillation Settling Time
tSCKW tSCKR tSCKF
SCK tScyc
Figure 17.62
SCK Input Clock Timing
547
tScyc SCK tTXD TxD (data transmission) RxD (data reception)
Figure 17.63
Synchronous Mode SCI Input/Output Timing
,,,
tRXS tRXH tPORTH tPORTD
PORT 7- PORT 0 (read) PORT 7- PORT 0 (write) tPORTS
Figure 17.64
I/O Port Input/Output Timing
548
17.3.11 AC Characteristics Test Conditions * Input/output signal reference level: 1.5 V (VCC = 3.3-3.6V). * Input pulse level: VSS to 3.0 V (when RESET, BREQ , NMI, IRL3-IRL0, CKIO, MD5- MD0 are VSS to VCC). * Input rise/fall time: 1 ns
IOL
LSI output pin CL
DUT output VREF
IOH Notes: 1. CL is the total capacitance including the test jig probe, as shown below: 2. 30 pF: CKIO, RAS, CASxx, CSO-CS6, CE2A, CE2B, BACK 50 pF: All other pins IOL and IOH are the values shown in table 17.3
Figure 17.65
Output Load Circui
549
550
Appendix A Pin Functions
A.1 Pin States
Table A.1 shows pin states during resets, power-down states, and the bus-released state. Table A.1 Pin States during Resets, Power-Down States, and Bus-Released State
BusReleased State IO*1 I*1 O*1 I O I I L I O IO*2 IO*3 I IZ*4 IZ*4 IZO*6 I I O
Category Clock
Pin CKIO EXTAL XTAL EXTAL2 XTAL2 RESET BREQ BACK CA STATUS0, STATUS1 MD0/SCK MD1/TXD MD2/RXD MD3/CE2A MD4/CE2B MD5/RAS2
Power-On Manual Reset Reset IO*1 I*1 O*1 I O I I O I O I I I I I I I I O IO*1 I*1 O*1 I O I I O I O I I I IH*4 IH*4 IO*5 I I O
Power-Down State Standby IO*1 I*1 O*1 I O I I O I O I I I IZH*7 IZH*7 IZO*6 I I O Sleep IO*1 I*1 O*1 I O I I O I O IO*2 IO*3 I IH*4 IH*4 IO*5 I I O
System control
Interrupt
NMI IRL3 to IRL0 IRQOUT
551
Table A.1 Pin States during Resets, Power-Down States, and Bus-Released State (cont)
BusReleased State Z ZO*8 Z ZK*10 Z Z Z Z Z ZO*11 ZO*11 ZO*11 ZO*11 ZO*11 Z Z Z Z Z Z O Z Z IO*12 IO
Category Address Bus Data Bus
Pin A25 to A0 D31 to D30 D29 to D24
Power-On Manual Reset Reset O Z Z O ZO*8 Z ZK*10 I O O O O O O O O O O O O O O O O I I Z IO
Power-Down State Standby Z ZO*8 Z ZK*10 Z ZH*13 ZH*13 ZH*13 ZH*13 ZO*11 ZO*11 ZO*11 ZO*11 ZO*11 ZH*13 ZH*13 ZH*13 ZH*13 ZH*13 ZH*13 O Z Z IO*14 IO Sleep O ZO*8 Z ZK*10 I H H H H O O O O O H H H H H H O I I IO*12 IO
D23 to D16/ Z PORT7 to PORT0 D15 to D0 Bus Control CS0 to CS4 CS5/CE1A CS6/CE1B BS RAS/CE CASLH CASHL /CAS2L Z H H H H H
CASLL/CAS/OE H H H
CASHH/CAS2H H DQMLL/WE0 DQMLU/WE1 DQMUL/WE2 / ICIORD DQMUU/WE3 / ICIOWR RD/WR RD CKE WAIT IOIS16 TMU/RTC PLL TCLK CAP1, CAP2 H H H H H H H Z Z Z IO
I: Input O: Output H: High-level output 552
L: Low-level output Z: High impedance K: Input pin is high impedance, output pin holds its state Notes: 1. Dependent on the clock mode (MD2-MD0 setting). 2. When SCI and port are not used, I. When used, I or O depending on register setting. 3. When SCI and port are not used, I. When used, O. 4. When PCMCIA is not used, I. When used, H or Z. 5. When area 2 DRAM is not used, I. When used, O. 6. When area 2 DRAM is not used, I. When used, Z or O depending on register setting. 7. When PCMCIA is not used, I. When used, Z or H depending on register setting. 8. O when the port function is used. 9. Z when the port function is used. 10. When the port function is used, K depending on register setting. 11. Z or O depending on register setting. 12. I or O depending on register setting. 13. Z or H depending on register setting. 14. In standby mode, I or O depending on register setting. In hardware standby mode, I or L depending on register setting.
553
A.2
Pin Specifications
Table A.2 shows the pin specifications. Table A.2 Pin
Pin MD5/RAS2
Specifications
Pin No. 130 I/O I/O Function Operating mode pin (endian switching)/RAS (for DRAM). MD signal is fetched in at power-on reset. Switched to RAS2 on area 2 DRAM enabling by register. Operating mode pin (area 0 bus width)/PCMCIA CE pin. MD signal is fetched in at power-on reset. Switched to CE2B on area 6 PCMCIA enabling by register.
MD4/CE2B
103
I/O
MD3/CE2A
104
I/O
Operating mode pin (area 0 bus width)/PCMCIA CE pin. MD signal is fetched in at power-on reset. Switched to CE2A on area 5 PCMCIA enabling by register.
MD2/RXD
84
I
Operating mode pin/serial data input. MD signal is fetched in at power-on reset. Switched to RXD on SCI enabling by register.
MD1/TXD
85
I/O
Operating mode pin/serial data output. MD signal is fetched in at power-on reset. Switched to TXD on SCI enabling by register.
MD0/SCK
86
I/O
Operating mode pin/serial clock. MD signal is fetched in at power-on reset. Switched to SCK on SCI enabling by register.
STATUS1 STATUS0 A25 to A0
97 98 72 to 70, 67 to 61, 58 to 56, 53 to 51, 48 to 43, 40 to 37 140 to 143, 1 to 4 5, 8 to 14
O O O
Processor status Processor status Address bus
D31 to D24 D23 to D16/ Port 7 to Port 0
I/O I/O
Data bus Data bus / I/O port
554
Table A.2 Pin Specifications (cont)
Pin D15 to D0 Pin No. 15 to 16, 21 to 29, 32 to 36 108 109 110 to 114 105 129 I/O I/O Function Data bus
CS6/CE1B CS5/CE1A CS4 to CS0 BS RAS/CE
O O O O O O O O O O
Chip select 6/PCMCIA CE Chip select 5/PCMCIA CE Chip select 4--chip select 0 Bus cycle start DRAM, synchronous DRAM RAS/pseudo-SRAM CE D31-D24 (DRAM CAS)/D15-D8 (area 2 DRAM CAS) select signal D23-D16 (DRAM CAS)/D7-D0 (area 2 DRAM CAS) select signal D15-D8 select signal (DRAM CAS) D7-D0 select (DRAM CAS)/memory select signal (synchronous DRAM CAS/pseudo-SRAM OE) D31-D24 select signal (normal memory, pseudo-SRAM WE /synchronous DRAM DQM)/IO write (PCMCIA, PCMCIB) D23-D16 select signal (normal memory, pseudo-SRAM WE /synchronous DRAM DQM)/IO write (PCMCIA, PCMCIB) D15-D8 select signal (normal memory, pseudo-SRAM WE/synchronous DRAM DQM) D7-D0 select signal (normal memory, pseudo-SRAM WE/synchronous DRAM DQM) Read/write (synchronous DRAM/DRAM/PCMCIA) Read pulse (PCMCIA/normal memory) Hardware wait request IO16 bit indication (PCMCIA IO area) Bus request Bus acknowledge Interrupt request notification Reset Chip active Causes a transition to hardware standby mode when low. Drive high in a power-on reset. 555
CASHH/CAS2H 119 CASHL /CAS2L 120 CASLH 125
CASLL/CAS/OE 126 WE3 /DQMUU/ ICIOWR WE2/DQMUL/ ICIORD WE1 /DQMLU WE0 /DQMLL RD/WR RD WAIT IOIS16 BREQ BACK IRQOUT RESET CA 117
118
O
123 124 106 107 132 94 87 96 95 88 81
O O O O I I I O O I I
Table A.2 Pin Specifications (cont)
Pin NMI IRL3 to IRL0 TCLK EXTAL XTAL CAP1 CAP2 CKIO CKE XTAL2 EXTAL2 NC VCC Pin No. 89 90 to 93 134 79 80 74 77 101 131 136 137 99 I/O I I I/O I O O O I/O O O I O Function Nonmaskable interrupt request External interrupt source input Timer external clock input/RTC clock output External clock/crystal resonator pin Crystal resonator pin External capacitance pin (for PLL1) External capacitance pin (for PLL1) System clock input/output Clock enable control (for synchronous DRAM) Crystal resonator pin (for on-chip RTC) Crystal resonator pin (for on-chip RTC) Leave unconnected
Power Power supply (3.3 V) 7, 18, 20, 31, 42, 50, 55, 60, supply 69, 81, 83, 102, 116, 122, 128, 139 135 75, 78 6, 17, 19, 30, 41, 49, 54, 59, 68, 82, 100, 115, 121, 127, 133, 144 138 73, 76 Power RTC oscillator power supply (3.3 V) supply Power PLL power supply (3.3 V) supply Power Power supply (0 V) supply
VCC (RTC) VCC (PLL) VSS
VSS (RTC) VSS (PLL)
Power RTC oscillator power supply (0 V) supply Power PLL power supply (0 V) supply
Note: Except in hardware standby mode, power must be supplied constantly to all power supply pins. In hardware standby mode, power should be supplied at least to the RTC power supply pins.
556
A.3
Handling of Unused Pins
* When RTC is not used EXTAL2: Pull up XTAL2: Leave unconnected VCC (RTC): Power supply (3.3 V) VSS (RTC): Power supply (0 V) * When PLL1 is not used CAP1: Leave unconnected VCC (PLL): Power supply (3.3 V) VSS (PLL): Power supply (0 V) * When PLL2 is not used CAP2: Leave unconnected VCC (PLL): Power supply (3.3 V) VSS (PLL): Power supply (0 V) * When on-chip crystal oscillator is not used XTAL: Leave unconnected
557
A.4
Pin States in Access to Each Address Space
Table A.3 Pin States (Normal Memory/Little-Endian)
8-Bit Bus Width Pin CS6 to CS0 RD R W RD/WR R W BS RAS/CE CAS/CASLL /OE CASLH CASHL/CAS2L CASHH /CAS2H DQMLL/WE0 R W DQMLU/WE1 R W DQMUL/WE2/ICIORD R W DQMUU/WE3/ICIOWR R W MD3/CE2A MD4/CE2B MD5/RAS2 CKE WAIT IOIS16 A25 to A0 D7 to D0 D15 to D8 D23 to D16/ PORT7 to PORT0 D31 to D24 Byte/Word/Longword Access Enabled Low High High Low Enabled High High High High High High Low High High High High High High High-Z or high*1 High-Z or high*2 High-Z or high*3 Disabled Enabled*4 Disabled Address Valid data High-Z High-Z*5 High-Z*6 Byte Access (Address 2n) Enabled Low High High Low Enabled High High High High High High Low High High High High High High High-Z or high*1 High-Z or high*2 High-Z or high*3 Disabled Enabled*4 Disabled Address Valid data Invalid data High-Z*5 High-Z*6 16-Bit Bus Width Byte Access (Address 2n + 1) Enabled Low High High Low Enabled High High High High High High High High Low High High High High High-Z or high*1 High-Z or high*2 High-Z or high*3 Disabled Enabled*4 Disabled Address Invalid data Valid data High-Z*5 High-Z*6 Word/Longword Access Enabled Low High High Low Enabled High High High High High High Low High Low High High High High High-Z or high*1 High-Z or high*2 High-Z or high*3 Disabled Enabled*4 Disabled Address Valid data Valid data High-Z*5 High-Z*6
558
Table A.3 Pin States (Normal Memory/Little-Endian) (cont)
32-Bit Bus Width Byte Access (Address 4n) Enabled R W RD/WR R W BS RAS/CE CAS/CASLL /OE CASLH CASHL/CAS2L CASHH /CAS2H DQMLL/WE0 R W DQMLU/WE1 R W DQMUL/WE2/ICIORD R W DQMUU/WE3/ICIOWR R W MD3/CE2A MD4/CE2B MD5/RAS2 CKE WAIT IOIS16 A25 to A0 D7 to D0 Low High High Low Enabled High High High High High High Low High High High High High High Byte Access (Address 4n + 1) Enabled Low High High Low Enabled High High High High High High High High Low High High High High Byte Access (Address 4n + 2) Enabled Low High High Low Enabled High High High High High High High High High High Low High High Byte Access (Address 4n + 3) Enabled Low High High Low Enabled High High High High High High High High High High High High Low Word Access (Address 4n) Enabled Low High High Low Enabled High High High High High High Low High Low High High High High Word Access (Address Longword 4n + 2) Access Enabled Low High High Low Enabled High High High High High High High High High High Low High Low Enabled Low High High Low Enabled High High High High High High Low High Low High Low High Low
Pin CS6 to CS0 RD
High-Z or High-Z or High-Z or High-Z or High-Z or High-Z or High-Z or high*1 high*1 high*1 high*1 high*1 high*1 high*1 High-Z or High-Z or High-Z or High-Z or High-Z or High-Z or High-Z or high*2 high*2 high*2 high*2 high*2 high*2 high*2 High-Z or High-Z or High-Z or High-Z or High-Z or High-Z or High-Z or high*3 high*3 high*3 high*3 high*3 high*3 high*3 Disabled Enabled*4 Disabled Address Valid data Disabled Enabled*4 Disabled Address Invalid data Disabled Enabled*4 Disabled Address Invalid data Disabled Enabled*4 Disabled Address Invalid data Disabled Enabled*4 Disabled Address Valid data Disabled Enabled*4 Disabled Address Invalid data Disabled Enabled*4 Disabled Address Valid data
559
Table A.3 Pin States (Normal Memory/Little-Endian) (cont)
32-Bit Bus Width Byte Access (Address 4n) Invalid data Invalid data Invalid data Byte Access (Address 4n + 1) Valid data Invalid data Invalid data Byte Access (Address 4n + 2) Invalid data Valid data Invalid data Byte Access (Address 4n + 3) Invalid data Invalid data Valid data Word Access (Address 4n) Valid data Invalid data Invalid data Word Access (Address Longword 4n + 2) Access Invalid data Valid data Valid data Valid data Valid data Valid data
Pin D15 to D8 D23 to D16/ PORT7 to PORT0 D31 to D24
Notes: 1. 2. 3. 4. 5.
When BCR1.A5PCM = 0, high-Z. When BCR1.A6PCM = 0, high-Z. When BCR1.DRAMTP (2-0) 101, high-Z. When WCR2 register wait setting is 0, disabled. When BCR2.PORTEN = 0, high-Z. When BCR2.PORTEN = 1, dependent on PCTR register. 6. When BCR2.PORTEN = 0, high-Z. When BCR2.PORTEN = 1, D31 and D30 only data output.
560
Table A.4 Pin States (Normal Memory/Big-Endian)
8-Bit Bus Width Pin CS6 to CS0 RD R W RD/WR R W BS RAS/CE CAS/CASLL /OE CASLH CASHL/CAS2L CASHH /CAS2H DQMLL/WE0 R W DQMLU/WE1 R W DQMUL/WE2/ICIORD R W DQMUU/WE3/ICIOWR R W MD3/CE2A MD4/CE2B MD5/RAS2 CKE WAIT IOIS16 A25 to A0 D7 to D0 D15 to D8 D23 to D16/ PORT7 to PORT0 D31 to D24 Byte/Word/Longword Access Enabled Low High High Low Enabled High High High High High High Low High High High High High High High-Z or high*1 Byte Access (Address 2n) Enabled Low High High Low Enabled High High High High High High High High Low High High High High High-Z or high*1 16-Bit Bus Width Byte Access (Address 2n + 1) High Low High High Low Enabled High High High High High High Low High High High High High High High-Z or high*1 Word/Longword Access Enabled Low High High Low Enabled High High High High High High Low High Low High High High High High-Z or high*1 High-Z or high*2 High-Z or high*3 Disabled Enabled*4 Disabled Address Valid data Valid data High-Z*5 High-Z*6
High-Z or high*2 High-Z or high*3 Disabled Enabled*4 Disabled Address Valid data High-Z High-Z*5 High-Z*6
High-Z or high*2 High-Z or high*3 Disabled Enabled*4 Disabled Address Invalid data Valid data High-Z*5 High-Z*6
High-Z or high*2 High-Z or high*3 Disabled Enabled*4 Disabled Address Valid data Invalid data High-Z*5 High-Z*6
561
Table A.4 Pin States (Normal Memory/Big-Endian) (cont)
32-Bit Bus Width Byte Access (Address 4n) Enabled R W RD/WR R W BS RAS/CE CAS/CASLL /OE CASLH CASHL/CAS2L CASHH /CAS2H DQMLL/WE0 R W DQMLU/WE1 R W DQMUL/WE2/ICIORD R W DQMUU/WE3/ICIOWR R W MD3/CE2A MD4/CE2B MD5/RAS2 CKE WAIT IOIS16 A25 to A0 D7 to D0 Low High High Low Enabled High High High High High High High High High High High High Low Byte Access (Address 4n + 1) Enabled Low High High Low Enabled High High High High High High High High High High Low High High Byte Access (Address 4n + 2) Enabled Low High High Low Enabled High High High High High High High High Low High High High High Byte Access (Address 4n + 3) Enabled Low High High Low Enabled High High High High High High Low High High High High High High Word Access (Address 4n) Enabled Low High High Low Enabled High High High High High High High High High High Low High Low Word Access (Address Longword 4n + 2) Access Enabled Low High High Low Enabled High High High High High High Low High Low High High High High Enabled Low High High Low Enabled High High High High High High Low High Low High Low High Low
Pin CS6 to CS0 RD
High-Z or High-Z or High-Z or High-Z or High-Z or High-Z or High-Z or high*1 high*1 high*1 high*1 high*1 high*1 high*1 High-Z or High-Z or High-Z or High-Z or High-Z or High-Z or High-Z or high*2 high*2 high*2 high*2 high*2 high*2 high*2 High-Z or High-Z or High-Z or High-Z or High-Z or High-Z or High-Z or high*3 high*3 high*3 high*3 high*3 high*3 high*3 Disabled Enabled*4 Disabled Address Invalid data Disabled Enabled*4 Disabled Address Invalid data Disabled Enabled*4 Disabled Address Invalid data Disabled Enabled*4 Disabled Address Valid data Disabled Enabled*4 Disabled Address Invalid data Disabled Enabled*4 Disabled Address Valid data Disabled Enabled*4 Disabled Address Valid data
562
Table A.4 Pin States (Normal Memory/Big-Endian) (cont)
32-Bit Bus Width Byte Access (Address 4n) Invalid data Invalid data Valid data Byte Access (Address 4n + 1) Invalid data Valid data Invalid data Byte Access (Address 4n + 2) Valid data Invalid data Invalid data Byte Access (Address 4n + 3) Invalid data Invalid data Invalid data Word Access (Address 4n) Invalid data Valid data Valid data Word Access (Address Longword 4n + 2) Access Valid data Invalid data Invalid data Valid data Valid data Valid data
Pin D15 to D8 D23 to D16/ PORT7 to PORT0 D31 to D24
Notes: 1. 2. 3. 4. 5.
When BCR1.A5PCM = 0, high-Z. When BCR1.A6PCM = 0, high-Z. When BCR1.DRAMTP (2-0) 101, high-Z. When WCR2 register wait setting is 0, disabled. When BCR2.PORTEN = 0, high-Z. When BCR2.PORTEN = 1, dependent on PCTR register . 6. When BCR2.PORTEN = 0, high-Z. When BCR2.PORTEN = 1, D31 and D30 only data output.
563
Table A.5 Pin States (Burst ROM/Little-Endian)
8-Bit Bus Width Pin CS6 to CS0 RD R W RD/WR R W BS RAS/CE CAS/CASLL /OE CASLH CASHL/CAS2L CASHH /CAS2H DQMLL/WE0 R W DQMLU/WE1 R W DQMUL/WE2/ICIORD R W DQMUU/WE3/ICIOWR R W MD3/CE2A MD4/CE2B MD5/RAS2 CKE WAIT IOIS16 A25 to A0 D7 to D0 D15 to D8 D23 to D16/ PORT7 to PORT0 D31 to D24 Byte/Word/Longword Access Enabled Low -- High -- Enabled High High High High High High -- High -- High -- High -- High-Z or high*1 High-Z or high*2 High-Z or high*3 Disabled Enabled*4 Disabled Address Valid data High-Z High-Z*5 High-Z*6 Byte Access (Address 2n) Enabled Low -- High -- Enabled High High High High High High -- High -- High -- High -- High-Z or high*1 High-Z or high*2 High-Z or high*3 Disabled Enabled*4 Disabled Address Valid data Invalid data High-Z*5 High-Z*6 16-Bit Bus Width Byte Access (Address 2n + 1) Enabled Low -- High -- Enabled High High High High High High -- High -- High -- High -- High-Z or high*1 High-Z or high*2 High-Z or high*3 Disabled Enabled*4 Disabled Address Invalid data Valid data High-Z*5 High-Z*6 Word/Longword Access Enabled Low -- High -- Enabled High High High High High High -- High -- High -- High -- High-Z or high*1 High-Z or high*2 High-Z or high*3 Disabled Enabled*4 Disabled Address Valid data Valid data High-Z*5 High-Z*6
564
Table A.5 Pin States (Burst ROM/Little-Endian) (cont)
32-Bit Bus Width Byte Access (Address 4n) Enabled R W RD/WR R W BS RAS/CE CAS/CASLL /OE CASLH CASHL/CAS2L CASHH /CAS2H DQMLL/WE0 R W DQMLU/WE1 R W DQMUL/WE2/ICIORD R W DQMUU/WE3/ICIOWR R W MD3/CE2A MD4/CE2B MD5/RAS2 CKE WAIT IOIS16 A25 to A0 D7 to D0 Low -- High -- Enabled High High High High High High -- High -- High -- High -- Byte Access (Address 4n + 1) Enabled Low -- High -- Enabled High High High High High High -- High -- High -- High -- Byte Access (Address 4n + 2) Enabled Low -- High -- Enabled High High High High High High -- High -- High -- High -- Byte Access (Address 4n + 3) Enabled Low -- High -- Enabled High High High High High High -- High -- High -- High -- Word Access (Address 4n) Enabled Low -- High -- Enabled High High High High High High -- High -- High -- High -- Word Access (Address Longword 4n + 2) Access Enabled Low -- High -- Enabled High High High High High High -- High -- High -- High -- Enabled Low -- High -- Enabled High High High High High High -- High -- High -- High --
Pin CS6 to CS0 RD
High-Z or High-Z or High-Z or High-Z or High-Z or High-Z or High-Z or high*1 high*1 high*1 high*1 high*1 high*1 high*1 High-Z or High-Z or High-Z or High-Z or High-Z or High-Z or High-Z or high*2 high*2 high*2 high*2 high*2 high*2 high*2 High-Z or High-Z or High-Z or High-Z or High-Z or High-Z or High-Z or high*3 high*3 high*3 high*3 high*3 high*3 high*3 Disabled Enabled*4 Disabled Address Valid data Disabled Enabled*4 Disabled Address Invalid data Disabled Enabled*4 Disabled Address Invalid data Disabled Enabled*4 Disabled Address Invalid data Disabled Enabled*4 Disabled Address Valid data Disabled Enabled*4 Disabled Address Invalid data Disabled Enabled*4 Disabled Address Valid data
565
Table A.5 Pin States (Burst ROM/Little-Endian) (cont)
32-Bit Bus Width Byte Access (Address 4n) Invalid data Invalid data Invalid data Byte Access (Address 4n + 1) Valid data Invalid data Invalid data Byte Access (Address 4n + 2) Invalid data Valid data Invalid data Byte Access (Address 4n + 3) Invalid data Invalid data Valid data Word Access (Address 4n) Valid data Invalid data Invalid data Word Access (Address Longword 4n + 2) Access Invalid data Valid data Valid data Valid data Valid data Valid data
Pin D15 to D8 D23 to D16/ PORT7 to PORT0 D31 to D24
Notes: 1. 2. 3. 4. 5.
When BCR1.A5PCM = 0, high-Z. When BCR1.A6PCM = 0, high-Z. When BCR1.DRAMTP (2-0) 101, high-Z. When WCR2 register wait setting is 0, disabled. When BCR2.PORTEN = 0, high-Z. When BCR2.PORTEN = 1, dependent on PCTR register. 6. When BCR2.PORTEN = 0, high-Z. When BCR2.PORTEN = 1, D31 and D30 only data output.
566
Table A.6 Pin States (Burst ROM/Big-Endian)
8-Bit Bus Width Pin CS6 to CS0 RD R W RD/WR R W BS RAS/CE CAS/CASLL /OE CASLH CASHL/CAS2L CASHH /CAS2H DQMLL/WE0 R W DQMLU/WE1 R W DQMUL/WE2/ICIORD R W DQMUU/WE3/ICIOWR R W MD3/CE2A MD4/CE2B MD5/RAS2 CKE WAIT IOIS16 A25 to A0 D7 to D0 D15 to D8 D23 to D16/ PORT7 to PORT0 D31 to D24 Byte/Word/Longword Access Enabled Low -- High -- Enabled High High High High High High -- High -- High -- High -- High-Z or high*1 High-Z or high*2 High-Z or high*3 Disabled Enabled*4 Disabled Address Valid data High-Z High-Z*5 High-Z*6 Byte Access (Address 2n) Enabled Low -- High -- Enabled High High High High High High -- High -- High -- High -- High-Z or high*1 High-Z or high*2 High-Z or high*3 Disabled Enabled*4 Disabled Address Invalid data Valid data High-Z*5 High-Z*6 16-Bit Bus Width Byte Access (Address 2n + 1) Enabled Low -- High -- Enabled High High High High High High -- High -- High -- High -- High-Z or high*1 High-Z or high*2 High-Z or high*3 Disabled Enabled*4 Disabled Address Valid data Invalid data High-Z*5 High-Z*6 Word/Longword Access Enabled Low -- High -- Enabled High High High High High High -- High -- High -- High -- High-Z or high*1 High-Z or high*2 High-Z or high*3 Disabled Enabled*4 Disabled Address Valid data Valid data High-Z*5 High-Z*6
567
Table A.6 Pin States (Burst ROM/Big-Endian) (cont)
32-Bit Bus Width Byte Access (Address 4n) Enabled R W RD/WR R W BS RAS/CE CAS/CASLL /OE CASLH CASHL/CAS2L CASHH /CAS2H DQMLL/WE0 R W DQMLU/WE1 R W DQMUL/WE2/ICIORD R W DQMUU/WE3/ICIOWR R W MD3/CE2A MD4/CE2B MD5/RAS2 CKE WAIT IOIS16 A25 to A0 D7 to D0 Low -- High -- Enabled High High High High High High -- High -- High -- High -- Byte Access (Address 4n + 1) Enabled Low -- High -- Enabled High High High High High High -- High -- High -- High -- Byte Access (Address 4n + 2) Enabled Low -- High -- Enabled High High High High High High -- High -- High -- High -- Byte Access (Address 4n + 3) Enabled Low -- High -- Enabled High High High High High High -- High -- High -- High -- Word Access (Address 4n) Enabled Low -- High -- Enabled High High High High High High -- High -- High -- High -- Word Access (Address Longword 4n + 2) Access Enabled Low -- High -- Enabled High High High High High High -- High -- High -- High -- Enabled Low -- High -- Enabled High High High High High High -- High -- High -- High --
Pin CS6 to CS0 RD
High-Z or High-Z or High-Z or High-Z or High-Z or High-Z or High-Z or high*1 high*1 high*1 high*1 high*1 high*1 high*1 High-Z or High-Z or High-Z or High-Z or High-Z or High-Z or High-Z or high*2 high*2 high*2 high*2 high*2 high*2 high*2 High-Z or High-Z or High-Z or High-Z or High-Z or High-Z or High-Z or high*3 high*3 high*3 high*3 high*3 high*3 high*3 Disabled Enabled*4 Disabled Address Invalid data Disabled Enabled*4 Disabled Address Invalid data Disabled Enabled*4 Disabled Address Invalid data Disabled Enabled*4 Disabled Address Valid data Disabled Enabled*4 Disabled Address Invalid data Disabled Enabled*4 Disabled Address Valid data Disabled Enabled*4 Disabled Address Valid data
568
Table A.6 Pin States (Burst ROM/Big-Endian) (cont)
32-Bit Bus Width Byte Access (Address 4n) Invalid data Invalid data Valid data Byte Access (Address 4n + 1) Invalid data Valid data Invalid data Byte Access (Address 4n + 2) Valid data Invalid data Invalid data Byte Access (Address 4n + 3) Invalid data Invalid data Invalid data Word Access (Address 4n) Invalid data Valid data Valid data Word Access (Address Longword 4n + 2) Access Valid data Invalid data Invalid data Valid data Valid data Valid data
Pin D15 to D8 D23 to D16/ PORT7 to PORT0 D31 to D24
Notes: 1. 2. 3. 4. 5.
When BCR1.A5PCM = 0, high-Z. When BCR1.A6PCM = 0, high-Z. When BCR1.DRAMTP (2-0) 101, high-Z. When WCR2 register wait setting is 0, disabled. When BCR2.PORTEN = 0, high-Z. When BCR2.PORTEN = 1, dependent on PCTR register . 6. When BCR2.PORTEN = 0, high-Z. When BCR2.PORTEN = 1, D31 and D30 only data output.
569
Table A.7 Pin States (DRAM/Little-Endian)
16-Bit Bus Width (Area 3) Byte Access Byte Access Word/ (Address 2n) (Address Longword 2n + 1) Access Enabled R W RD/WR R W BS RAS/CE CAS/CASLL /OE CASLH CASHL/CAS2L CASHH /CAS2H DQMLL/WE0 R W DQMLU/WE1 R W DQMUL/WE2/ICIORD R W DQMUU/WE3/ICIOWR R W MD3/CE2A MD4/CE2B MD5/RAS2 CKE WAIT IOIS16 A25 to A0 D7 to D0 D15 to D8 High High High Low Enabled Low Low High High High High High High High High High High High High-Z or high*1 High-Z or high*2 High-Z or high*3 Disabled Disabled Disabled Address Valid data Invalid data Enabled High High High Low Enabled Low High Low High High High High High High High High High High High-Z or high*1 High-Z or high*2 High-Z or high*3 Disabled Disabled Disabled Address Invalid data Valid data Enabled High High High Low Enabled Low Low Low High High High High High High High High High High High-Z or high*1 High-Z or high*2 High-Z or high*3 Disabled Disabled Disabled Address Valid data Valid data 16-Bit Bus Width (Area 2) Byte Access Byte Access Word/ (Address 2n) (Address Longword 2n + 1) Access Enabled High High High Low Enabled High High High Low High High High High High High High High High High-Z or high*1 High-Z or high*2 Low Disabled Disabled Disabled Address Valid data Invalid data Enabled High High High Low Enabled High High High High Low High High High High High High High High High-Z or high*1 High-Z or high*2 Low Disabled Disabled Disabled Address Invalid data Valid data Enabled High High High Low Enabled High High High Low Low High High High High High High High High High-Z or high*1 High-Z or high*2 Low Disabled Disabled Disabled Address Valid data Valid data
Pin CS6 to CS0 RD
570
Table A.7 Pin States (DRAM/Little-Endian) (cont)
16-Bit Bus Width (Area 3) Byte Access Byte Access Word/ (Address 2n) (Address Longword 2n + 1) Access High-Z*4 High-Z*5 High-Z*4 High-Z*5 High-Z*4 High-Z*5 16-Bit Bus Width (Area 2) Byte Access Byte Access Word/ (Address 2n) (Address Longword 2n + 1) Access High-Z*4 High-Z*5 High-Z*4 High-Z*5 High-Z*4 High-Z*5
Pin D23 to D16/ PORT7 to PORT0 D31 to D24
571
Table A.7 Pin States (DRAM/Little-Endian) (cont)
32-Bit Bus Width Byte Access (Address 4n) Enabled R W RD/WR R W BS RAS/CE CAS/CASLL /OE CASLH CASHL/CAS2L CASHH /CAS2H DQMLL/WE0 R W DQMLU/WE1 R W DQMUL/WE2/ICIORD R W DQMUU/WE3/ICIOWR R W MD3/CE2A MD4/CE2B MD5/RAS2 CKE WAIT IOIS16 A25 to A0 D7 to D0 High High High Low Enabled Low Low High High High High High High High High High High High Byte Access (Address 4n + 1) Enabled High High High Low Enabled Low High Low High High High High High High High High High High Byte Access (Address 4n + 2) Enabled High High High Low Enabled Low High High Low High High High High High High High High High Byte Access (Address 4n + 3) Enabled High High High Low Enabled Low High High High Low High High High High High High High High Word Access (Address 4n) Enabled High High High Low Enabled Low Low Low High High High High High High High High High High Word Access (Address Longword 4n + 2) Access Enabled High High High Low Enabled Low High High Low Low High High High High High High High High Enabled High High High Low Enabled Low Low Low Low Low High High High High High High High High
Pin CS6 to CS0 RD
High-Z or High-Z or High-Z or High-Z or High-Z or High-Z or High-Z or high*1 high*1 high*1 high*1 high*1 high*1 high*1 High-Z or High-Z or High-Z or High-Z or High-Z or High-Z or High-Z or high*2 high*2 high*2 high*2 high*2 high*2 high*2 High-Z Disabled Disabled Disabled Address Valid data High-Z Disabled Disabled Disabled Address Invalid data High-Z Disabled Disabled Disabled Address Invalid data High-Z Disabled Disabled Disabled Address Invalid data High-Z Disabled Disabled Disabled Address Valid data High-Z Disabled Disabled Disabled Address Invalid data High-Z Disabled Disabled Disabled Address Valid data
572
Table A.7 Pin States (DRAM/Little-Endian) (cont)
32-Bit Bus Width Byte Access (Address 4n) Invalid data Invalid data Invalid data Byte Access (Address 4n + 1) Valid data Invalid data Invalid data Byte Access (Address 4n + 2) Invalid data Valid data Invalid data Byte Access (Address 4n + 3) Invalid data Invalid data Valid data Word Access (Address 4n) Valid data Invalid data Invalid data Word Access (Address Longword 4n + 2) Access Invalid data Valid data Valid data Valid data Valid data Valid data
Pin D15 to D8 D23 to D16/ PORT7 to PORT0 D31 to D24
Notes: 1. 2. 3. 4.
When BCR1.A5PCM = 0, high-Z. When BCR1.A6PCM = 0, high-Z. When BCR1.DRAMTP (2-0) 101, high-Z. When BCR2.PORTEN = 0, high-Z. When BCR2.PORTEN = 1, dependent on PCTR register. 5. When BCR2.PORTEN = 0, high-Z. When BCR2.PORTEN = 1, D31 and D30 only data output.
573
Table A.8 Pin States (DRAM/Big-Endian)
16-Bit Bus Width (Area 3) Byte Access Byte Access Word/ (Address 2n) (Address Longword 2n + 1) Access Enabled R W RD/WR R W BS RAS/CE CAS/CASLL /OE CASLH CASHL/CAS2L CASHH /CAS2H DQMLL/WE0 R W DQMLU/WE1 R W DQMUL/WE2/ICIORD R W DQMUU/WE3/ICIOWR R W MD3/CE2A MD4/CE2B MD5/RAS2 CKE WAIT IOIS16 A25 to A0 D7 to D0 D15 to D8 High High High Low Enabled Low High Low High High High High High High High High High High High-Z or high*1 High-Z or high*2 High-Z or high*3 Disabled Disabled Disabled Address Invalid data Valid data Enabled High High High Low Enabled Low Low High High High High High High High High High High High High-Z or high*1 High-Z or high*2 High-Z or high*3 Disabled Disabled Disabled Address Valid data Invalid data Enabled High High High Low Enabled Low Low Low High High High High High High High High High High High-Z or high*1 High-Z or high*2 High-Z or high*3 Disabled Disabled Disabled Address Valid data Valid data 16-Bit Bus Width (Area 2) Byte Access Byte Access Word/ (Address 2n) (Address Longword 2n + 1) Access Enabled High High High Low Enabled High High High High Low High High High High High High High High High-Z or high*1 High-Z or high*2 Low Disabled Disabled Disabled Address Invalid data Valid data Enabled High High High Low Enabled High High High Low High High High High High High High High High High-Z or high*1 High-Z or high*2 Low Disabled Disabled Disabled Address Valid data Invalid data Enabled High High High Low Enabled High High High Low Low High High High High High High High High High-Z or high*1 High-Z or high*2 Low Disabled Disabled Disabled Address Valid data Valid data
Pin CS6 to CS0 RD
574
Table A.8 Pin States (DRAM/Big-Endian) (cont)
16-Bit Bus Width (Area 3) Byte Access Byte Access Word/ (Address 2n) (Address Longword 2n + 1) Access High-Z*4 High-Z*5 High-Z*4 High-Z*5 High-Z*4 High-Z*5 16-Bit Bus Width (Area 2) Byte Access Byte Access Word/ (Address 2n) (Address Longword 2n + 1) Access High-Z*4 High-Z*5 High-Z*4 High-Z*5 High-Z*4 High-Z*5
Pin D23 to D16/ PORT7 to PORT0 D31 to D24
575
Table A.8 Pin States (DRAM/Big-Endian) (cont)
32-Bit Bus Width Byte Access (Address 4n) Enabled R W RD/WR R W BS RAS/CE CAS/CASLL /OE CASLH CASHL/CAS2L CASHH /CAS2H DQMLL/WE0 R W DQMLU/WE1 R W DQMUL/WE2/ICIORD R W DQMUU/WE3/ICIOWR R W MD3/CE2A MD4/CE2B MD5/RAS2 CKE WAIT IOIS16 A25 to A0 D7 to D0 High High High Low Enabled Low High High High Low High High High High High High High High Byte Access (Address 4n + 1) Enabled High High High Low Enabled Low High High Low High High High High High High High High High Byte Access (Address 4n + 2) Enabled High High High Low Enabled Low High Low High High High High High High High High High High Byte Access (Address 4n + 3) Enabled High High High Low Enabled Low Low High High High High High High High High High High High Word Access (Address 4n) Enabled High High High Low Enabled Low High High Low Low High High High High High High High High Word Access (Address Longword 4n + 2) Access Enabled High High High Low Enabled Low Low Low High High High High High High High High High High Enabled High High High Low Enabled Low Low Low Low Low High High High High High High High High
Pin CS6 to CS0 RD
High-Z or High-Z or High-Z or High-Z or High-Z or High-Z or High-Z or high*1 high*1 high*1 high*1 high*1 high*1 high*1 High-Z or High-Z or High-Z or High-Z or High-Z or High-Z or High-Z or high*2 high*2 high*2 high*2 high*2 high*2 high*2 High-Z Disabled Disabled Disabled Address Invalid data High-Z Disabled Disabled Disabled Address Invalid data High-Z Disabled Disabled Disabled Address Invalid data High-Z Disabled Disabled Disabled Address Valid data High-Z Disabled Disabled Disabled Address Invalid data High-Z Disabled Disabled Disabled Address Valid data High-Z Disabled Disabled Disabled Address Valid data
576
Table A.8 Pin States (DRAM/Big-Endian) (cont)
32-Bit Bus Width Byte Access (Address 4n) Invalid data Invalid data Valid data Byte Access (Address 4n + 1) Invalid data Valid data Invalid data Byte Access (Address 4n + 2) Valid data Invalid data Invalid data Byte Access (Address 4n + 3) Invalid data Invalid data Invalid data Word Access (Address 4n) Invalid data Valid data Valid data Word Access (Address Longword 4n + 2) Access Valid data Invalid data Invalid data Valid data Valid data Valid data
Pin D15 to D8 D23 to D16/ PORT7 to PORT0 D31 to D24
Notes: 1. 2. 3. 4.
When BCR1.A5PCM = 0, high-Z. When BCR1.A6PCM = 0, high-Z. When BCR1.DRAMTP (2-0) 101, high-Z. When BCR2.PORTEN = 0, high-Z. When BCR2.PORTEN = 1, dependent on PCTR register. 5. When BCR2.PORTEN = 0, high-Z. When BCR2.PORTEN = 1, D31 and D30 only data output.
577
Table A.9 Pin States (Synchronous DRAM/Little-Endian)
32-Bit Bus Width Byte Access (Address 4n) Enabled R W RD/WR R W BS RAS/CE CAS/CASLL /OE CASLH CASHL/CAS2L CASHH /CAS2H DQMLL/WE0 R W DQMLU/WE1 R W DQMUL/WE2/ICIORD R W DQMUU/WE3/ICIOWR R W MD3/CE2A MD4/CE2B MD5/RAS2 CKE WAIT IOIS16 A25 to A0 D7 to D0 High High High Low Enabled Low Low High High High Low Low High High High High High High Byte Access (Address 4n + 1) Enabled High High High Low Enabled Low Low High High High High High Low Low High High High High Byte Access (Address 4n + 2) Enabled High High High Low Enabled Low Low High High High High High High High Low Low High High Byte Access (Address 4n + 3) Enabled High High High Low Enabled Low Low High High High High High High High High High Low Low Word Access (Address 4n) Enabled High High High Low Enabled Low Low High High High Low Low Low Low High High High High Word Access (Address Longword 4n + 2) Access Enabled High High High Low Enabled Low Low High High High High High High High Low Low Low Low Enabled High High High Low Enabled Low Low High High High Low Low Low Low Low Low Low Low
Pin CS6 to CS0 RD
High-Z or High-Z or High-Z or High-Z or High-Z or High-Z or High-Z or high*1 high*1 high*1 high*1 high*1 high*1 high*1 High-Z or High-Z or High-Z or High-Z or High-Z or High-Z or High-Z or high*2 high*2 high*2 high*2 high*2 high*2 high*2 High-Z High*3 Disabled Disabled High-Z High*3 Disabled Disabled High-Z High*3 Disabled Disabled High-Z High*3 Disabled Disabled High-Z High*3 Disabled Disabled High-Z High*3 Disabled Disabled High-Z High*3 Disabled Disabled
Address, Address, Address, Address, Address, Address, Address, command command command command command command command Valid data Invalid data Invalid data Invalid data Valid data Invalid data Valid data
578
Table A.9 Pin States (Synchronous DRAM/Little-Endian) (cont)
32-Bit Bus Width Byte Access (Address 4n) Invalid data Invalid data Invalid data Byte Access (Address 4n + 1) Valid data Invalid data Invalid data Byte Access (Address 4n + 2) Invalid data Valid data Invalid data Byte Access (Address 4n + 3) Invalid data Invalid data Valid data Word Access (Address 4n) Valid data Invalid data Invalid data Word Access (Address Longword 4n + 2) Access Invalid data Valid data Valid data Valid data Valid data Valid data
Pin D15 to D8 D23 to D16/ PORT7 to PORT0 D31 to D24
Notes: 1. When BCR1.A5PCM = 0, high-Z. 2. When BCR1.A6PCM = 0, high-Z. 3. Normally high. Low in self-refreshing.
579
Table A.10
Pin States (Synchronous DRAM/Big-Endian)
32-Bit Bus Width Byte Access (Address 4n) Enabled R W High High High Low Enabled Low Low High High High R W High High High High High High Low Low Byte Access (Address 4n + 1) Enabled High High High Low Enabled Low Low High High High High High High High Low Low High High Byte Access (Address 4n + 2) Enabled High High High Low Enabled Low Low High High High High High Low Low High High High High Byte Access (Address 4n + 3) Enabled High High High Low Enabled Low Low High High High Low Low High High High High High High Word Access (Address 4n) Enabled High High High Low Enabled Low Low High High High High High High High Low Low Low Low Word Access (Address Longword 4n + 2) Access Enabled High High High Low Enabled Low Low High High High Low Low Low Low High High High High Enabled High High High Low Enabled Low Low High High High Low Low Low Low Low Low Low Low
Pin CS6 to CS0 RD
RD/WR
R W
BS RAS/CE CAS/CASLL /OE CASLH CASHL/CAS2L CASHH /CAS2H DQMLL/WE0
DQMLU/WE1
R W
DQMUL/WE2/ICIORD
R W
DQMUU/WE3/ICIOWR
R W
MD3/CE2A MD4/CE2B MD5/RAS2 CKE WAIT IOIS16 A25 to A0 D7 to D0
High-Z or High-Z or High-Z or High-Z or High-Z or High-Z or High-Z or high*1 high*1 high*1 high*1 high*1 high*1 high*1 High-Z or High-Z or High-Z or High-Z or High-Z or High-Z or High-Z or high*2 high*2 high*2 high*2 high*2 high*2 high*2 High-Z High*3 Disabled Disabled High-Z High*3 Disabled Disabled High-Z High*3 Disabled Disabled High-Z High*3 Disabled Disabled High-Z High*3 Disabled Disabled High-Z High*3 Disabled Disabled High-Z High*3 Disabled Disabled
Address, Address, Address, Address, Address, Address, Address, command command command command command command command Invalid data Invalid data Invalid data Valid data Invalid data Valid data Valid data
580
Table A.10
Pin States (Synchronous DRAM/Big-Endian) (cont)
32-Bit Bus Width Byte Access (Address 4n) Invalid data Invalid data Valid data Byte Access (Address 4n + 1) Invalid data Valid data Invalid data Byte Access (Address 4n + 2) Valid data Invalid data Invalid data Byte Access (Address 4n + 3) Invalid data Invalid data Invalid data Word Access (Address 4n) Invalid data Valid data Valid data Word Access (Address Longword 4n + 2) Access Valid data Invalid data Invalid data Valid data Valid data Valid data
Pin D15 to D8 D23 to D16/ PORT7 to PORT0 D31 to D24
Notes: 1. When BCR1.A5PCM = 0, high-Z. 2. When BCR1.A6PCM = 0, high-Z. 3. Normally high. Low in self-refreshing.
581
Table A.11
Pin States (Pseudo-SRAM/Little-Endian)
16-Bit Bus Width
Pin CS6 to CS0 RD R W RD/WR R W BS RAS/CE CAS/CASLL /OE CASLH CASHL/CAS2L CASHH /CAS2H DQMLL/WE0 R W DQMLU/WE1 R W DQMUL/WE2/ICIORD R W DQMUU/WE3/ICIOWR R W MD3/CE2A MD4/CE2B MD5/RAS2 CKE WAIT IOIS16 A25 to A0 D7 to D0 D15 to D8 D23 to D16/ PORT7 to PORT0 D31 to D24
Byte Access (Address 2n) Enabled High High High Low Enabled Low Low High High High High Low High High High High High High High-Z or high*1
Byte Access (Address 2n + 1) Enabled High High High Low Enabled Low Low High High High High High High Low High High High High High-Z or high*1
Word/Longword Access Enabled High High High Low Enabled Low Low High High High High Low High Low High High High High High-Z or high*1 High-Z or high*2 High-Z Disabled Disabled Disabled Address Valid data Valid data High-Z*3 High-Z*4
High-Z or high*2 High-Z Disabled Disabled Disabled Address Valid data Invalid data High-Z*3 High-Z*4
High-Z or high*2 High-Z Disabled Disabled Disabled Address Invalid data Valid data High-Z*3 High-Z*4
582
Table A.11
Pin States (Pseudo-SRAM/Little-Endian) (cont)
32-Bit Bus Width Byte Access (Address 4n) Enabled R W High High High Low Enabled Low Low High High High R W High Low High High High High High High Byte Access (Address 4n + 1) Enabled High High High Low Enabled Low Low High High High High High High Low High High High High Byte Access (Address 4n + 2) Enabled High High High Low Enabled Low Low High High High High High High High High Low High High Byte Access (Address 4n + 3) Enabled High High High Low Enabled Low Low High High High High High High High High High High Low Word Access (Address 4n) Enabled High High High Low Enabled Low Low High High High High Low High Low High High High High Word Access (Address Longword 4n + 2) Access Enabled High High High Low Enabled Low Low High High High High High High High High Low High Low Enabled High High High Low Enabled Low Low High High High High Low High Low High Low High Low
Pin CS6 to CS0 RD
RD/WR
R W
BS RAS/CE CAS/CASLL /OE CASLH CASHL/CAS2L CASHH /CAS2H DQMLL/WE0
DQMLU/WE1
R W
DQMUL/WE2/ICIORD
R W
DQMUU/WE3/ICIOWR
R W
MD3/CE2A MD4/CE2B MD5/RAS2 CKE WAIT IOIS16 A25 to A0 D7 to D0
High-Z or High-Z or High-Z or High-Z or High-Z or High-Z or High-Z or high*1 high*1 high*1 high*1 high*1 high*1 high*1 High-Z or High-Z or High-Z or High-Z or High-Z or High-Z or High-Z or high*2 high*2 high*2 high*2 high*2 high*2 high*2 High-Z Disabled Disabled Disabled Address Valid data High-Z Disabled Disabled Disabled Address Invalid data High-Z Disabled Disabled Disabled Address Invalid data High-Z Disabled Disabled Disabled Address Invalid data High-Z Disabled Disabled Disabled Address Valid data High-Z Disabled Disabled Disabled Address Invalid data High-Z Disabled Disabled Disabled Address Valid data
583
Table A.11
Pin States (Pseudo-SRAM/Little-Endian) (cont)
32-Bit Bus Width Byte Access (Address 4n) Invalid data Invalid data Invalid data Byte Access (Address 4n + 1) Valid data Invalid data Invalid data Byte Access (Address 4n + 2) Invalid data Valid data Invalid data Byte Access (Address 4n + 3) Invalid data Invalid data Valid data Word Access (Address 4n) Valid data Invalid data Invalid data Word Access (Address Longword 4n + 2) Access Invalid data Valid data Valid data Valid data Valid data Valid data
Pin D15 to D8 D23 to D16/ PORT7 to PORT0 D31 to D24
Notes: 1. When BCR1.A5PCM = 0, high-Z. 2. When BCR1.A6PCM = 0, high-Z. 3. When BCR2.PORTEN = 0, high-Z. When BCR2.PORTEN = 1, dependent on PCTR register. 4. When BCR2.PORTEN = 0, high-Z. When BCR2.PORTEN = 1, D31 and D30 only data output.
584
Table A.12
Pin States (Pseudo-SRAM/Big-Endian)
16-Bit Bus Width
Pin CS6 to CS0 RD R W RD/WR R W BS RAS/CE CAS/CASLL /OE CASLH CASHL/CAS2L CASHH /CAS2H DQMLL/WE0 R W DQMLU/WE1 R W DQMUL/WE2/ICIORD R W DQMUU/WE3/ICIOWR R W MD3/CE2A MD4/CE2B MD5/RAS2 CKE WAIT IOIS16 A25 to A0 D7 to D0 D15 to D8 D23 to D16/ PORT7 to PORT0 D31 to D24
Byte Access (Address 2n) Enabled High High High Low Enabled Low Low High High High High High High Low High High High High High-Z or high*1
Byte Access (Address 2n + 1) Enabled High High High Low Enabled Low Low High High High High Low High High High High High High High-Z or high*1
Word/Longword Access Enabled High High High Low Enabled Low Low High High High High Low High Low High High High High High-Z or high*1 High-Z or high*2 High-Z Disabled Disabled Disabled Address Valid data Valid data High-Z*3 High-Z*4
High-Z or high*2 High-Z Disabled Disabled Disabled Address Invalid data Valid data High-Z*3 High-Z*4
High-Z or high*2 High-Z Disabled Disabled Disabled Address Valid data Invalid data High-Z*3 High-Z*4
585
Table A.12
Pin States (Pseudo-SRAM/Big-Endian) (cont)
32-Bit Bus Width Byte Access (Address 4n) Enabled R W High High High Low Enabled Low Low High High High R W High High High High High High High Low Byte Access (Address 4n + 1) Enabled High High High Low Enabled Low Low High High High High High High High High Low High High Byte Access (Address 4n + 2) Enabled High High High Low Enabled Low Low High High High High High High Low High High High High Byte Access (Address 4n + 3) Enabled High High High Low Enabled Low Low High High High High Low High High High High High High Word Access (Address 4n) Enabled High High High Low Enabled Low Low High High High High High High High High Low High Low Word Access (Address Longword 4n + 2) Access Enabled High High High Low Enabled Low Low High High High High Low High Low High High High High Enabled High High High Low Enabled Low Low High High High High Low High Low High Low High Low
Pin CS6 to CS0 RD
RD/WR
R W
BS RAS/CE CAS/CASLL /OE CASLH CASHL/CAS2L CASHH /CAS2H DQMLL/WE0
DQMLU/WE1
R W
DQMUL/WE2/ICIORD
R W
DQMUU/WE3/ICIOWR
R W
MD3/CE2A MD4/CE2B MD5/RAS2 CKE WAIT IOIS16 A25 to A0 D7 to D0
High-Z or High-Z or High-Z or High-Z or High-Z or High-Z or High-Z or high*1 high*1 high*1 high*1 high*1 high*1 high*1 High-Z or High-Z or High-Z or High-Z or High-Z or High-Z or High-Z or high*2 high*2 high*2 high*2 high*2 high*2 high*2 High-Z Disabled Disabled Disabled Address Invalid data High-Z Disabled Disabled Disabled Address Invalid data High-Z Disabled Disabled Disabled Address Invalid data High-Z Disabled Disabled Disabled Address Valid data High-Z Disabled Disabled Disabled Address Invalid data High-Z Disabled Disabled Disabled Address Valid data High-Z Disabled Disabled Disabled Address Valid data
586
Table A.12
Pin States (Pseudo-SRAM/Big-Endian) (cont)
32-Bit Bus Width Byte Access (Address 4n) Invalid data Invalid data Valid data Byte Access (Address 4n + 1) Invalid data Valid data Invalid data Byte Access (Address 4n + 2) Valid data Invalid data Invalid data Byte Access (Address 4n + 3) Invalid data Invalid data Invalid data Word Access (Address 4n) Invalid data Valid data Valid data Word Access (Address Longword 4n + 2) Access Valid data Invalid data Invalid data Valid data Valid data Valid data
Pin D15 to D8 D23 to D16/ PORT7 to PORT0 D31 to D24
Notes: 1. When BCR1.A5PCM = 0, high-Z. 2. When BCR1.A6PCM = 0, high-Z. 3. When BCR2.PORTEN = 0, high-Z. When BCR2.PORTEN = 1, dependent on PCTR register. 4. When BCR2.PORTEN = 0, high-Z. When BCR2.PORTEN = 1, D31 and D30 only data output.
587
Table A.13
Pin States (PCMCIA/Little-Endian)
PCMCIA Memory Interface (Area 5) 8-Bit Bus Width 16-Bit Bus Width Byte Access (Address 2n) Enabled Low High High Low Enabled High High High High High High High High Low High High High High High high*2 High-Z or high*2 Byte Access (Address 2n + 1) High Low High High Low Enabled High High High High High High High High Low High High High High Low High-Z or high*2 Word/Longword Access Enabled Low High High Low Enabled High High High High High High High High Low High High High High Low High-Z or high*2 High-Z or high*3 Disabled Enabled*4 Disabled Address Valid data Valid data High-Z*5 High-Z*6
Pin CS6 to CS0 RD R W RD/WR R W BS RAS/CE CAS/CASLL /OE CASLH CASHL/CAS2L CASHH /CAS2H DQMLL/WE0 R W DQMLU/WE1 R W DQMUL/WE2/ICIORD R W DQMUU/WE3/ICIOWR R W MD3/CE2A MD4/CE2B MD5/RAS2 CKE WAIT IOIS16 A25 to A0 D7 to D0 D15 to D8 D23 to D16/ PORT7 to PORT0 D31 to D24
Byte/Word/Longword Access Enabled Low High High Low Enabled High High High High High High High High Low High High High High High High-Z or
High-Z or high*3 Disabled Enabled*4 Disabled Address Valid data High-Z High-Z*5 High-Z*6
High-Z or high*3 Disabled Enabled*4 Disabled Address Valid data Invalid data High-Z*5 High-Z*6
High-Z or high*3 Disabled Enabled*4 Disabled Address Invalid data Valid data High-Z*5 High-Z*6
588
Table A.13
Pin States (PCMCIA/Little-Endian) (cont)
PCMCIA Memory Interface (Area 6) 8-Bit Bus Width Byte/ Word/ Longword Access Enabled R W Low High High Low Enabled High High High High High R W High High High Low High High High High 8-Bit Bus Width Byte/ Word/ Longword Access Enabled High High High Low Enabled High High High High High High High High High Low High High Low PCMCIA/IO Interface (Area 6)
16-Bit Bus Width Byte Byte Access Access (Ad(Address dress 2n) 2n + 1) Enabled Low High High Low Enabled High High High High High High High High Low High High High High High Low High High Low Enabled High High High High High High High High Low High High High High Word/ Longword Access Enabled Low High High Low Enabled High High High High High High High High Low High High High High
16-Bit Bus Width Byte Byte Access Word/ Access (Ad-dressLong(Ad2n + 1) word dress 2n) Access Enabled High High High Low Enabled High High High High High High High High High Low High High Low High High High High Low Enabled High High High High High High High High High Low High High Low Enabled High High High Low Enabled High High High High High High High High High Low High High Low High-Z or high*1 Low High-Z or high*3
Pin CS6 to CS0 RD
RD/WR
R W
BS RAS/CE CAS/CASLL /OE CASLH CASHL/CAS2L CASHH /CAS2H DQMLL/WE0
DQMLU/WE1
R W
DQMUL/WE2/ICIORD
R W
DQMUU/WE3/ICIOWR
R W
MD3/CE2A MD4/CE2B MD5/RAS2 CKE WAIT IOIS16 A25 to A0
High-Z High-Z High-Z High-Z High-Z High-Z High-Z or high*1 or high*1 or high*1 or high*1 or high*1 or high*1 or high*1 High High Low Low High High Low
High-Z High-Z High-Z High-Z High-Z High-Z High-Z or high*3 or high*3 or high*3 or high*3 or high*3 or high*3 or high*3
Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled Enabled*4 Enabled*4 Enabled*4 Enabled*4 Enabled*4 Enabled*4 Enabled*4 Enabled*4 Disabled Disabled Disabled Disabled Disabled Disabled Enabled Address Address Address Address Address Address Address Enabled Address
589
Table A.13
Pin States (PCMCIA/Little-Endian) (cont)
PCMCIA Memory Interface (Area 6) 8-Bit Bus Width Byte/ Word/ Longword Access Valid data High-Z 8-Bit Bus Width Byte/ Word/ Longword Access Valid data High-Z PCMCIA/IO Interface (Area 6)
16-Bit Bus Width Byte Byte Access Access (Ad(Address 2n) dress 2n + 1) Valid data Invalid data Invalid data Valid data Word/ Longword Access Valid data Valid data
16-Bit Bus Width Byte Byte Access Access Word/ (Ad(Ad-dressLongdress 2n) 2n + 1) word Access Valid data Invalid data Invalid data Valid data Valid data Valid data
Pin D7 to D0 D15 to D8 D23 to D16/ PORT7 to PORT0 D31 to D24
High-Z*5 High-Z*5 High-Z*5 High-Z*5 High-Z*5 High-Z*5 High-Z*5 High-Z*5 High-Z*6 High-Z*6 High-Z*6 High-Z*6 High-Z*6 High-Z*6 High-Z*6 High-Z*6
Notes: 1. 2. 3. 4. 5.
When BCR1.A5PCM = 0, high-Z. When BCR1.A6PCM = 0, high-Z. When BCR1.DRAMTP (2-0) 101, high-Z. When WCR2 register wait setting is 0, disabled. When BCR2.PORTEN = 0, high-Z. When BCR2.PORTEN = 1, dependent on PCTR register. 6. When BCR2.PORTEN = 0, high-Z. When BCR2.PORTEN = 1, D31 and D30 only data output.
590
Table A.14
Pin States (PCMCIA/BIG-Endian)
PCMCIA Memory Interface (Area 5) 8-Bit Bus Width 16-Bit Bus Width Byte Access (Address 2n) Enabled Low High High Low Enabled High High High High High High High High Low High High High High High high*2 High-Z or high*2 Byte Access (Address 2n + 1) High Low High High Low Enabled High High High High High High High High Low High High High High Low High-Z or high*2 Word/Longword Access Enabled Low High High Low Enabled High High High High High High High High Low High High High High Low High-Z or high*2 High-Z or high*3 Disabled Enabled*4 Disabled Address Valid data Valid data High-Z*5 High-Z*6
Pin CS6 to CS0 RD R W RD/WR R W BS RAS/CE CAS/CASLL /OE CASLH CASHL/CAS2L CASHH /CAS2H DQMLL/WE0 R W DQMLU/WE1 R W DQMUL/WE2/ICIORD R W DQMUU/WE3/ICIOWR R W MD3/CE2A MD4/CE2B MD5/RAS2 CKE WAIT IOIS16 A25 to A0 D7 to D0 D15 to D8 D23 to D16/ PORT7 to PORT0 D31 to D24
Byte/Word/Longword Access Enabled Low High High Low Enabled High High High High High High High High Low High High High High High High-Z or
High-Z or high*3 Disabled Enabled*4 Disabled Address Valid data High-Z High-Z*5 High-Z*6
High-Z or high*3 Disabled Enabled*4 Disabled Address Invalid data Valid data High-Z*5
High-Z or high*3 Disabled Enabled*4 Disabled Address Valid data Invalid data High-Z*5 High-Z*6
High-Z*6
591
Table A.14
Pin States (PCMCIA/BIG-Endian) (cont)
PCMCIA Memory Interface (Area 6) 8-Bit Bus Width Byte/ Word/ Longword Access Enabled R W Low High High Low Enabled High High High High High R W High High High Low High High High High 8-Bit Bus Width Byte/ Word/ Longword Access Enabled High High High Low Enabled High High High High High High High High High Low High High Low PCMCIA/IO Interface (Area 6)
16-Bit Bus Width Byte Byte Access Access (Ad(Address dress 2n) 2n + 1) Enabled Low High High Low Enabled High High High High High High High High Low High High High High High Low High High Low Enabled High High High High High High High High Low High High High High Word/ Longword Access Enabled Low High High Low Enabled High High High High High High High High Low High High High High
16-Bit Bus Width Byte Byte Access Access (Ad(Address dress 2n) 2n + 1) Enabled High High High Low Enabled High High High High High High High High High Low High High Low High High High High Low Enabled High High High High High High High High High Low High High Low Word/ Longword Access Enabled High High High Low Enabled High High High High High High High High High Low High High Low
Pin CS6 to CS0 RD
RD/WR
R W
BS RAS/CE CAS/CASLL /OE CASLH CASHL/CAS2L CASHH /CAS2H DQMLL/WE0
DQMLU/WE1
R W
DQMUL/WE2/ICIORD
R W
DQMUU/WE3/ICIOWR
R W
MD3/CE2A MD4/CE2B MD5/RAS2 CKE WAIT IOIS16 A25 to A0
High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z or high*1 or high*1 or high*1 or high*1 or high*1 or high*1 or high*1 or high*1 High High Low Low High High Low Low
High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z or high*3 or high*3 or high*3 or high*3 or high*3 or high*3 or high*3 or high*3 Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled Enabled*4 Enabled*4 Enabled*4 Enabled*4 Enabled*4 Enabled*4 Enabled*4 Enabled*4 Disabled Disabled Disabled Disabled Disabled Disabled Enabled Address Address Address Address Address Address Address Enabled Address
592
Table A.14
Pin States (PCMCIA/BIG-Endian) (cont)
PCMCIA Memory Interface (Area 6) 8-Bit Bus Width Byte/ Word/ Longword Access Valid data High-Z 8-Bit Bus Width Byte/ Word/ Longword Access Valid data High-Z PCMCIA/IO Interface (Area 6)
16-Bit Bus Width Byte Byte Access Access (Ad(Address dress 2n) 2n + 1) Invalid data Valid data Valid data Invalid data Word/ Longword Access Valid data Valid data
16-Bit Bus Width Byte Byte Access Access (Ad(Address dress 2n) 2n + 1) Invalid data Valid data Valid data Invalid data Word/ Longword Access Valid data Valid data
Pin D7 to D0 D15 to D8 D23 to D16/ PORT7 to PORT0 D31 to D24
High-Z*5 High-Z*5 High-Z*5 High-Z*5 High-Z*5 High-Z*5 High-Z*5 High-Z*5 High-Z*6 High-Z*6 High-Z*6 High-Z*6 High-Z*6 High-Z*6 High-Z*6 High-Z*6
Notes: 1. 2. 3. 4. 5.
When BCR1.A5PCM = 0, high-Z. When BCR1.A6PCM = 0, high-Z. When BCR1.DRAMTP (2-0) 101, high-Z. When WCR2 register wait setting is 0, disabled. When BCR2.PORTEN = 0, high-Z. When BCR2.PORTEN = 1, dependent on PCTR register. 6. When BCR2.PORTEN = 0, high-Z. When BCR2.PORTEN = 1, D31 and D30 only data output.
593
Appendix B Control Registers
B.1 Register Address Map
The address map of memory-mapped control registers is shown in Table B-1. The following module abbreviations are used. MMU: UBC: CPG: BSC: RTC: INTC: TMU: SCI: CAC: Memory management unit User break controller Clock pulse generator Bus state controller Realtime clock Interrupt controller Timer unit Serial communication interface controller Cache
The Bus column shows the internal bus to which the control register is connected. S: System bus, to which the CPU, cache, TLB, multiplier, and UBC are connected. C: Cache bus, to which the BSC and cache are connected. P: Peripheral bus, to which the BSC and peripheral modules (RTC, INTC, TMU, and SCI) are connected. The Size column shows the register size in bits. The Access Size column shows the size used when the control register is accessed (read or written). If a size other than that indicated is used in an access, the result will be incorrect.
594
Table B.1
Register
Memory-Mapped Control Register Address Map
Abbreviation Module PTEH PTEL TTB TEA MMUCR BASRA BASRB CCR TRA EXPEVT INTEVT BARA BAMRA BBRA BARB BAMRB BBRB BDRB BDMRB BRCR FRQCR STBCR WTCNT WTCSR BCR1 BCR2 MMU MMU MMU MMU MMU UBC UBC CAC INTC INTC INTC UBC UBC UBC UBC UBC UBC UBC UBC UBC CPG CPG CPG CPG BSC BSC Bus S S S S S S S S S S S S S S S S S S S S S S S S C C Address H'FFFFFFF0 H'FFFFFFF4 H'FFFFFFF8 H'FFFFFFFC H'FFFFFFE0 H'FFFFFFE4 H'FFFFFFE8 H'FFFFFFEC H'FFFFFFD0 H'FFFFFFD4 H'FFFFFFD8 H'FFFFFFB0 H'FFFFFFB4 H'FFFFFFB8 H'FFFFFFA0 H'FFFFFFA4 H'FFFFFFA8 H'FFFFFF90 H'FFFFFF94 H'FFFFFF98 H'FFFFFF80 H'FFFFFF82 H'FFFFFF84 H'FFFFFF86 H'FFFFFF60 H'FFFFFF62 Acces S i z e s Size 32 32 32 32 32 8 8 32 32 32 32 32 8 16 32 8 16 32 32 16 16 8 8 8 16 16 32 32 32 32 32 8 8 32 32 32 32 32 8 16 32 8 16 32 32 16 16 8 R: 8, W: 16 R: 8, W: 16 16 16 595
Page table entry high register Page table entry low register Translation table page register TLB exception address register MMU control register Break ASID register A Break ASID register B Cache control register TRAPA exception register Exception event register Interrupt event register Break address register A Break address mask register A Break bus cycle register A Break address register B Break address mask register B Break bus cycle register B Break data register B Break data mask register B Break control register Frequency control register Standby control register Watchdog timer counter Watchdog timer control/status register Bus control register 1 Bus control register 2
Table B.1
Register
Memory-Mapped Control Register Address Map (cont)
Abbreviation Module WCR1 WCR2 MCR DCR PCR BSC BSC BSC BSC BSC BSC BSC BSC BSC BSC BSC SCI BSC RTC RTC RTC RTC RTC RTC RTC RTC RTC RTC RTC RTC RTC RTC RTC RTC Bus C C C C C C C C C C C P C P P P P P P P P P P P P P P P P Address H'FFFFFF64 H'FFFFFF66 H'FFFFFF68 H'FFFFFF6A H'FFFFFF6C H'FFFFFF6E H'FFFFFF70 H'FFFFFF72 H'FFFFFF74 H'FFFFFF76 H'FFFFFF78 H'FFFFFF7C H'FFFFD000 H'FFFFFEC0 H'FFFFFEC2 H'FFFFFEC4 H'FFFFFEC6 H'FFFFFEC8 H'FFFFFECA H'FFFFFECC H'FFFFFECE H'FFFFFED0 H'FFFFFED2 H'FFFFFED4 H'FFFFFED6 H'FFFFFED8 H'FFFFFEDA H'FFFFFEDC H'FFFFFEDE Acces S i z e s Size 16 16 16 16 16 16 16 16 16 16 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16 16 16 16 16 16 16 16 16 16 8 8
Wait state control register 1 Wait state control register 2 Individual memory control register DRAM control register PCMCIA control register
Refresh timer control/status RTCSR register Refresh timer counter Refresh timer constant counter Refresh count register Port control register Port data register Serial port register SDRAM mode register 64 Hz counter Second counter Minute counter Hour counter Day-of-week counter Day counter Month counter Year counter Second alarm register Minute alarm register Hour alarm register Day-of-week alarm register Day alarm register Month alarm register RTC control register 1 RTC control register 2 RTCNT RTCOR RFCR PCTR PDTR SCSPTR SDMR R64CNT RSECCNT RMINCNT RHRCNT RWKCNT RDAYCNT RMONCNT RYRCNT RSECAR RMINAR RHRAR RWKAR RDAYAR RMONAR RCR1 RCR2
8
8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8
596
Table B.1
Register
Memory-Mapped Control Register Address Map (cont)
Abbreviation Module ICR IPRA IPRB TOCR TSTR TCOR0 TCNT0 TCR0 TCOR1 TCNT1 TCR1 TCOR2 TCNT2 TCR2 TCPR2 SCSMR SCBRR SCSCR SCTDR SCSSR SCRDR SCSCMR INTC INTC INTC TMU TMU TMU TMU TMU TMU TMU TMU TMU TMU TMU TMU SCI SCI SCI SCI SCI SCI SCI Bus P P P P P P P P P P P P P P P P P P P P P P Address H'FFFFFEE0 H'FFFFFEE2 H'FFFFFEE4 H'FFFFFE90 H'FFFFFE92 H'FFFFFE94 H'FFFFFE98 H'FFFFFE9C H'FFFFFEA0 H'FFFFFEA4 H'FFFFFEA8 H'FFFFFEAC H'FFFFFEB0 H'FFFFFEB4 H'FFFFFEB8 H'FFFFFE80 H'FFFFFE82 H'FFFFFE84 H'FFFFFE86 H'FFFFFE88 H'FFFFFE8A H'FFFFFE8C Acces S i z e s Size 16 16 16 8 8 32 32 16 32 32 16 32 32 16 32 8 8 8 8 8 8 8 16 16 16 8 8 32 32 16 32 32 16 32 32 16 32 8 8 8 8 8 8 8
Interrupt control register Interrupt priority level setting register A Interrupt priority level setting register B Timer output control register Timer start register Timer constant register 0 Timer counter 0 Timer control register 0 Timer constant register 1 Timer counter 1 Timer control register 1 Timer constant register 2 Timer counter 2 Timer control register 2 Input capture register 2 Serial mode register Bit rate register Serial control register Transmit data register Serial status register Receive data register Smartcard mode register
597
B.2
Register Bit List
A register bit list is shown in table B.2 Table B.2 Register Bit List
Abbreviation SDMR Bit 7 -- Bit 6 -- Bit 5 -- Bit 4 -- Bit 3 Bit 2 Bit 1 Bit 0 Module BSC
SCSMR SCBRR SCSCR SCTSR SCTDR SCSSR SCRSR SCRDR SCSCMR TOCR TSTR TCOR0
C/A
CHR
PE
O/E
STOP
MP
CKS1
CKS0
SCI SCI
TIE
RIE
TE
RE
MPIE
TEIE
CKE1
CKE0
SCI SCI SCI
TDRE
RDRF
ORER
FER
PER
TEND
MPB
MPBT
SCI SCI SCI
-- -- --
-- -- --
-- -- --
-- -- --
SDIR -- --
SINV -- STR2
-- -- STR1
SMIF TCOE STR0
SCI TMU TMU TMU
TCNT0
TMU
TCR0
-- --
-- --
-- UNIE
-- CKEG1
-- CKEG0
-- TPSC2
-- TPSC1
UNF TPSC0
TMU
TCOR1
TMU
TCNT1
TMU
598
Table B.2 Register Bit List (cont)
Abbreviation TCR1 Bit 7 -- -- TCOR2 Bit 6 -- -- Bit 5 -- UNIE Bit 4 -- CKEG1 Bit 3 -- CKEG0 Bit 2 -- TPSC2 Bit 1 -- TPSC1 Bit 0 UNF TPSC0 TMU Module TMU
TCNT2
TMU
TCR2
-- ICPE1
-- ICPE0
-- UNIE
-- CKEG1
-- CKEG0
-- TPSC2
ICPF TPSC1
UNF TPSC0
TMU
TCPR2
TMU
R64CNT RSECCNT RMINCNT RHRCNT RWKCNT RDAYCNT RMONCNT RYRCNT RSECAR RMINAR RHRAR RWKAR RDAYAR RMONAR
-- -- -- -- -- -- -- 10 years ENB ENB ENB ENB ENB ENB
1Hz
2Hz
4Hz
8Hz
16Hz 1 second 1 minute 1 hour Day of week 1 day 1 month 1 year 1 second 1 minute 1 hour Day of week 1 day 1 month
32Hz 1 second 1 minute 1 hour Day of week 1 day 1 month 1 year 1 second 1 minute 1 hour Day of week 1 day 1 month
64Hz 1 second 1 minute 1 hour Day of week 1 day 1 month 1 year 1 second 1 minute 1 hour Day of week 1 day 1 month
RTC RTC RTC RTC RTC RTC RTC RTC RTC RTC RTC RTC RTC RTC
10 seconds10 seconds10 seconds1 second 10 minutes 10 minutes 10 minutes 1 minute -- -- -- -- 10 years 10 hours -- 10 days -- 10 years 10 hours -- 10 days 1 hours -- 1 day
10 months 1 month 10 years 1 year
10 seconds10 seconds10 seconds1 second 10 minutes 10 minutes 10 minutes 1 minute -- -- -- -- 10 hours -- 10 days -- 10 hours -- 10 days 1 hour -- 1 day
10 months 1 month
599
Table B.2 Register Bit List (cont)
Abbreviation RCR1 RCR2 ICR Bit 7 CF PEF NMIL -- IPRA TMU0 TMU2 IPRB WDT SCI BCR1 -- A5BST0 BCR2 -- A3SZ1 WCR1 -- A3IW1 WCR2 A6W2 A4W0 MCR TPC1 -- DCR TPC1 -- PCR -- A5TED1 RTCSR -- CMF RTCNT -- Bit 6 -- PES2 -- -- TMU0 TMU2 WDT SCI -- A6BST1 -- A3SZ0 -- A3IW0 A6W1 A3W1 TPC0 BE TPC0 BE -- A5TED0 -- CMIE -- Bit 5 -- PES1 -- -- TMU0 TMU2 WDT SCI Bit 4 CIE PES0 -- -- TMU0 TMU2 WDT SCI Bit 3 AIE RTCEN -- -- TMU1 RTC REF -- Bit 2 -- ADJ -- -- TMU1 RTC REF -- Bit 1 -- RESET -- -- TMU1 RTC REF -- A0BST0 Bit 0 AF START NMIE -- TMU1 RTC REF -- A5BST1 A6PCM A4SZ0 PORTEN A4IW0 A0IW0 A4W1 A0W0 TRAS0
EDOMODE
Module RTC RTC INTC
INTC
INTC
HIZMEM* HIZCNT ENDIAN A0BST1 A6BST0 A6SZ1 A2SZ1 A6IW1 A2IW1 A6W0 A3W0 RCD1 SZ RCD1 -- -- A6TED1 -- CKS2 --
BSC
DRAMTP2 DRAMTP1 DRAMTP0 A5PCM
A6SZ0 A2SZ0 A6IW0 A2IW0 A5W2 A1-2W1 RCD0 AMX1 RCD0 AMX1 -- A6TED0 -- CKS1 --
A5SZ1 A1SZ1 A5IW1 A1IW1 A5W1 A1-2W0 TRWL1 AMX0 -- AMX0 -- A5TEH1 -- CKS0 --
A5SZ0 A1SZ0 A5IW0 A1IW0 A5W0 A0W2 TRWL0 RFSH -- RFSH -- A5TEH0 -- OVF --
A4SZ1 -- A4IW1 A0IW1 A4W2 A0W1 TRAS1 RMODE TRAS1 RMODE -- A6TEH1 -- OVIE --
BSC
BSC
BSC
BSC
TRAS0
--
BSC
-- A6TEH0 -- LMTS --
BSC
BSC
BSC
RTCOR
--
--
--
--
--
--
--
--
BSC
RFCR
--
--
--
--
--
--
BSC
PCTR
PB7PUP PB3PUP
PB7IO PB3IO PB6DT --
PB6PUP PB6IO PB2PUP PB5DT -- PB2IO PB4DT --
PB5PUP PB5IO PB1PUP PB3DT SPB1IO PB1IO PB2DT
PB4PUP PB4IO PB0PUP PB1DT PB0IO PB0DT SPB0DT
I/O
PDTR SCSPTR
PB7DT --
I/O I/O
SPB1DT SPB0IO
600
Table B.2 Register Bit List (cont)
Abbreviation FRQCR Bit 7 Bit 6 IFC2 PSTBY -- Bit 5 PFC2 STC1 -- Bit 4 -- STC0 -- Bit 3 -- IFC1 -- Bit 2 -- IFC0 MSTP2 Bit 1 -- PFC1 MSTP1 Bit 0 CKOEN PFC0 MSTP0 Powerdown states CPG TME BDB31 BDB23 BDB15 BDB7 BDMRB BDM31 BDM23 BDM15 BDM7 BRCR CMFA DBEB BARB BAB31 BAB23 BAB15 BAB7 BAMRB BBRB -- -- -- BARA BAA31 BAA23 BAA15 BAA7 BAMRA BBRA -- -- -- WT/IT BDB30 BDB22 BDB14 BDB6 BDM30 BDM22 BDM14 BDM6 CMFB PCBB BAB30 BAB22 BAB14 BAB6 -- -- -- BAA30 BAA22 BAA14 BAA6 -- -- -- RSTS BDB29 BDB21 BDB13 BDB5 BDM29 BDM21 BDM13 BDM5 -- -- BAB29 BAB21 BAB13 BAB5 -- -- IDB1 BAA29 BAA21 BAA13 BAA5 -- -- IDA1 WOVF BDB28 BDB20 BDB12 BDB4 BDM28 BDM20 BDM12 BDM4 -- -- BAB28 BAB20 BAB12 BAB4 -- -- IDB0 BAA28 BAA20 BAA12 BAA4 -- -- IDA0 IOVF BDB27 BDB19 BDB11 BDB3 BDM27 BDM19 BDM11 BDM3 -- SEQ BAB27 BAB19 BAB11 BAB3 -- -- RWB1 BAA27 BAA19 BAA11 BAA3 -- -- RWA1 CKS2 BDB26 BDB18 BDB10 BDB2 BDM26 BDM18 BDM10 BDM2 PCBA -- BAB26 BAB18 BAB10 BAB2 BASMB -- RWB0 BAA26 BAA18 BAA10 BAA2 BASMA -- RWA0 CKS1 BDB25 BDB17 BDB9 BDB1 BDM25 BDM17 BDM9 BDM1 -- -- BAB25 BAB17 BAB9 BAB1 BAMB1 -- SZB1 BAA25 BAA17 BAA9 BAA1 BAMA1 -- SZA1 CKS0 BDB24 BDB16 BDB8 BDB0 BDM24 BDM16 BDM8 BDM0 -- -- BAB24 BAB16 BAB8 BAB0 BAMB0 -- SZB0 BAA24 BAA16 BAA8 BAA0 BAMA0 -- SZA0 UBC UBC UBC UBC UBC UBC UBC UBC CPG UBC Module CPG
STC2
PLLEN STBY
STBCR
WTCNT WTCSR BDRB
601
Table B.2 Register Bit List (cont)
Abbreviation TRA Bit 7 -- -- -- Bit 6 -- -- -- Bit 5 -- -- -- Bit 4 -- -- -- Bit 3 -- -- -- Bit 2 -- -- -- -- EXPEVT -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- CCN Bit 1 -- -- Bit 0 -- -- Module CCN
INTEVT
-- -- --
-- -- --
-- -- --
-- -- --
-- --
-- --
-- --
-- --
CCN
MMUCR
-- -- -- --
-- -- -- -- BASA6 BASB6 -- -- -- --
-- -- -- RC BASA5 BASB5 -- -- -- RA
-- -- -- RC BASA4 BASB4 -- -- -- 0
-- -- -- -- BASA3 BASB3 -- -- -- CF
-- -- -- TF BASA2 BASB2 -- -- -- CB
-- -- -- IX BASA1 BASB1 -- -- -- WT
-- -- SV AT BASA0 BASB0 -- -- -- CE
CCN
BASRA BASRB CCR
BASA7 BASB7 -- -- -- --
UBC UBC CCN
PTEH
CCN
--
--
PTEL
CCN
-- -- TTB PR PR SZ C D SH
V -- CCN
602
Table B.2 Register Bit List (cont)
Abbreviation TEA Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module CCN
Legend SCI: Serial communication interface TMU: Timer unit RTC: Real time clock INTC: Interrupt controller BSC: Bus state controller CPG: Clock pulse generator UBC: User break controller CCN: Cache controller unit
603
B.3
Register States in Reset and Power-Down States
Table B.3 Register States in Reset and Power-Down States
Reset States Module CPU Register R0-R15 MACH, MACL PR PC SR SSR SPC GBR VBR MMU PTEH PTEL TTB TEA MMUCR Cache INTC CCR ICR IPRA IPRB TRA EXPEVT INTEVT UBC BARA BASRA BAMRA Power-On Undefined Undefined Undefined H'A0000000 Initialized*1 Undefined Undefined Undefined H'00000000 Undefined Undefined Undefined Undefined Initialized*2 H'00000000 H'8000/H'0000*3 H'0000 H'0000 Undefined H'00000000 Undefined Undefined Undefined Undefined Manual Undefined Undefined Undefined H'A0000000 Initialized*1 Undefined Undefined Undefined H'00000000 Undefined Undefined Undefined Undefined Initialized*2 H'00000000 H'8000/H'0000*3 H'0000 H'0000 Undefined H'00000020 Undefined Held Held Held Power-Down States Standby Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Sleep Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held
604
Table B.3 Register States in Reset and Power-Down States (cont)
Reset States Module UBC Register BBRA BARB BAMRB BASRB BBRB BDMRB BDRB BRCR CPG STBCR FRQCR WTCNT WTCSR BSC BCR1 BCR2 WCR1 WCR2 MCR DCR PCR RTCSR RTCNT RTCOR RFCR PCTR PDTR Power-On H'0000 Undefined Undefined Undefined H'0000 Undefined Undefined H'0000 H'00 H'0102*4 H'00*4 H'00*4 H'0000 H'3FFC H'3FFF H'FFFF H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 Undefined Manual H'0000 Held Held Held H'0000 Held Held H'0000 Held Held Runs Runs Held Held Held Held Held Held Held Runs Runs Held Runs Held Held Power-Down States Standby Held Held Held Held Held Held Held Held Held Held Runs Runs Held Held Held Held Held Held Held Held Held Held Held Held Held Sleep Held Held Held Held Held Held Held Held Held Held Runs Runs Held Held Held Held Held Held Held Runs Runs Held Runs Held Held
605
Table B.3 Register States in Reset and Power-Down States (cont)
Reset States Module TMU Register TOCR TSTR TCOR0 TCNT0 TCR0 TCOR1 TCNT1 TCR1 TCOR2 TCNT2 TCR2 TCPR2 RTC R64CNT RSECCNT RMINCNT RHRCNT RWKCNT RDAYCNT RMONCNT RYRCNT RSECAR RMINAR RHRAR RWKAR RDAYAR RMONAR RCR1 RCR2 Power-On H'00 H'00 H'FFFFFFFF H'FFFFFFFF H'0000 H'FFFFFFFF H'FFFFFFFF H'0000 H'FFFFFFFF H'FFFFFFFF H'0000 Undefined Undefined Runs Runs Runs Runs Runs Runs Runs Held*6 Held*6 Held*6 Held*6 Held*6 Held*6 H'00 H'09 Manual H'00 H'00 H'FFFFFFFF H'FFFFFFFF H'0000 H'FFFFFFFF H'FFFFFFFF H'0000 H'FFFFFFFF H'FFFFFFFF H'0000 Undefined Runs Runs Runs Runs Runs Runs Runs Runs Held Held Held Held Held Held Initialized*7 Initialized*8 Power-Down States Standby Held Initialized/ Held*5 Held Held/Runs*5 Held/Runs*5 Held Held/Runs*5 Held/Runs*5 Held Held/Runs*5 Held/Runs*5 Held Runs Runs Runs Runs Runs Runs Runs Runs Held Held Held Held Held Held Held Held Sleep Held Held Held Runs Runs Held Runs Runs Held Runs Runs Held Runs Runs Runs Runs Runs Runs Runs Runs Held Held Held Held Held Held Held Held
606
Table B.3 Register States in Reset and Power-Down States (cont)
Reset States Module SCI Register SCSMR SCBRR SCSCR SCTDR SCSSR SCRDR SCSPTR SCSCMR Power-On H'00 H'FF H'00 H'FF H'84 H'00 Initialized*9 Initialized*11 Manual H'00 H'FF H'00 H'FF H'84 H'00 Held Initialized*11 Power-Down States Standby H'00 H'FF H'00 H'FF H'84 H'00 Held Initialized*11 Sleep H'00*10 H'FF*10 H'00*10 H'FF*10 H'84*10 H'00*10 Held Initialized*11
Notes: 1. MD = 1, RB = 1, BL = 1, I3-I0 = B'1111 M, Q, S, T are undefined. 2. The SV bit is undefined, other bits = 0. 3. H'8000: NMI pin is high / H'0000: NMI pin is low. 4. Initialized in a power-on reset via the RESET pin. Held in a power-on reset via the WDT. 5. Depends on the count clock mode. 6. Only the ENB bit is cleared. 7. CF bit is undefined, other bits = 0. 8. RTCEN and START are held, other bits = 0. 9. Bits 2 and 0 are undefined, other bits = 0 10. Held when SCI is operating, initialized when SCI is not used. 11. Bits 0, 2, and 3 are cleared, other bits are undefined.
607
Appendix C Delay Time Variation Due to Load Capacitance
A graph (reference data) of the variation in delay time when a load capacitance greater than that stipulated is connected to the SH7708 Series' pins. The graph shown in figure C.1 should be taken into consideration if the stipulated capacitance is exceeded in connecting an external device. The graph will not be linear if the connected load capacitance exceeds the range shown in figure C.1.
+4.0 ns
+3.0 ns
Delay Time
+2.0 ns
+1.0 ns
+0.0 ns +0 pF
+25 pF Load Capacitance
+50 pF
Figure C.1
Load Capacitance vs. Delay Time
608
Appendix D Package Dimensions
22.0 0.3 20 108 109
22.0 0.3
Unit: mm
73 72
144 1 0.22 0.05 0.20 0.04 36
37
0.17 0.05 0.15 0.04 1.70 Max
1.40
0.08 M
0.5
1.25
1.0 0 10 0.5 0.1
0.10
Dimension including the plating thickness Base material dimension
Figure D.1
Package Dimensions (FP-144F: SH7708, SH7708S, SH7708R)
0.10 0.10
609
18.0 0.2
16
Unit: mm
73 72
108 109
18.0 0.2
144 1 0.18 0.05 0.16 0.04 36
37
1.0
0.17 0.05 0.15 0.04
1.20 Max
0.07 M
1.00
0.4
1.0 0 8
0.5 0.1
0.08
Dimension including the plating thickness Base material dimension
Figure D.2
Package Dimensions (TFP-144: SH7708S)
610
0.10 0.05
SH7708 Series Hardware Manual
Publication Date: 1st Edition, November 1996 6th Edition, March 1999 Published by: Electronic Devices Sales & Marketing Group Semiconductor & Integrated Circuits Group Hitachi, Ltd. Edited by: Technical Documentation Group UL Media Co., Ltd. Copyright (c) Hitachi, Ltd., 1996. All rights reserved. Printed in Japan.
611

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